TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual
3-26
V2.0, 2007-07
Clock, V2.0
Module Enable/Disable Control
If a module is not used at all by an application, it can be completely shut off by setting bit
DISR in its CLC register. For peripheral modules with a run mode clock divider field
RMC, a second option to completely switch off the module is to set bit field RMC to 00
H
.
This also disables the module’s operation.
The status bit DISS always indicates whether a module is currently switched off
(DISS = 1) or switched on (DISS = 0). With a few exceptions (e.g. EBU_CLC), the
default state of a peripheral module after reset is “module disabled” with DISS set (see
Write operations to the registers of disabled modules are not allowed. However, the CLC
of a disabled module can be written. An attempt to write to any of the other writable
registers of a disabled module except CLC will cause the corresponding Bus Control Unit
(BCU) to generate a bus error.
A read operation of registers of a disabled module (except CAN) is allowed and does not
generate a bus error.
When a disabled module is switched on by writing an appropriate value to its MOD_CLC
register (DISR = 0 and RMC (if implemented) > 0), status bit DISS changes from 1 to 0.
During the phase in which the module becomes active, any write access to
corresponding module registers (when DISS is still set) will generate a bus error.
Therefore, when enabling a disabled module, application software should check after
activation of the module once (read back of the CLC register) to find out whether DISS
is already reset, before a module register (including the CLC register) will be written to.
Note: A read access occurring while a module is disabled is treated as a normal read
access. This means, if a module register or a bit of it is cleared as a side-effect of
a read access of an enabled module, it will not be cleared by this read access
while the module is disabled.
Sleep Mode Control
The EDIS bit in the CLC register controls whether or not a module is stopped during
sleep mode. If EDIS is 0 (default after reset), a sleep mode request can be recognized
by the module and, when received, its clock is shut off.
If EDIS is set to 1, a sleep mode request is disregarded by the module and the module
continues its operation.
Debug Suspend Mode Control
During emulation and debugging of TC1796 applications, the execution of an application
program can be suspended. When an application is suspended, normal operation of the
application’s program is halted, and the TC1796 begins (or resumes) executing a special
debug monitor program. When the application is suspended, a suspend request signal
is generated by the TC1796 and sent to all modules. If bit SPEN is set to 1, the operation
