TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual
23-124
V2.0, 2007-07
MLI, V2.0
23.5
Implementation of the MLI0/MLI1 in TC1796
This section describes the MLI0/MLI1 module related external functions such as port
connections, interrupt and service request control, connections to other on-chip
modules, clock control, and the address map.
23.5.1
Interfaces of the MLI Modules
Each MLI module is supplied with separate clock control, address decoding, and
interrupt control logic. Four (for MLI0) and two (for MLI1) of the eight module service
request outputs are connected to service request nodes. Four service request outputs of
each MLI module are connected as DMA request to the DMA controller.
The data, clock, and control lines of each MLI receiver and transmitter are connected to
GPIO lines. Alternate functions of Port 1 and Port 5 lines are assigned to the MLI0
module I/O lines while alternate functions of Port 8 lines are assigned to the MLI1 module
I/O lines. Additionally, within one MLI module transmitter and receiver signals can be
dynamically connected among each other without using pins; this is useful for test
purposes in the local loop back mode. In this mode, the connections of the signals in pair
are:
•
TCLK/RCLKD
•
TREADYD/RREADYD
•
TVALIDD/RVALIDD
•
TDATA/RDATAD
show how the MLI0 and MLI1 modules are
interconnected to port lines and other on-chip functional blocks.
