TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual
12-3
V2.0, 2007-07
DMA, V2.0
12.1.1
Features
•
16 independent DMA channels
– 8 DMA channels in each DMA Sub-Block
– Up to 8 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within a DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
•
Programmable priority of the DMA Sub-Blocks on the bus interfaces
•
Buffer capability for move actions on the buses (at least 1move per bus is buffered)
•
Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous Mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated
– Programmable address modification
•
Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Support of circular buffer addressing mode
•
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
•
Micro Link bus interface support
•
Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
•
Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
•
All buses connected to the DMA module must work at the same frequency
•
Read/write requests of the System Bus side to the Remote Bus peripherals are
bridged to the Remote Peripheral Bus (only the DMA is master on the RPB)
