TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual
12-91
V2.0, 2007-07
DMA, V2.0
12.3
DMA Module Implementation
This section describes the TC1796 DMA module interfaces with the clock control,
interrupt control, and address decoding.
shows the TC1796-specific implementation details and interconnections of
the DMA module. The DMA module is supplied by a separate clock control, address
decoding, interrupt control, and the request input wiring matrix.
Figure 12-30 DMA Module Implementation and Interconnections
The request sources of the peripheral modules (ADC0/1, MSC0/1, MLI0/1, FADC,
MultiCAN, and SCU) are associated with Interrupt Node Pointers and individual interrupt
enable bits. As a result, each of the internal requests of a module can be routed
independently to any of the interrupt output lines (INT_Ox) of the module. The modules
ASC0/1 and SSC0/1 have interrupt output lines that are directly connected to a specific
request source.
MCA05707
f
DMA
SR[7:0]
DMA Controller
DMA
Channels
00-07
DMA Sub-Block 0
Request
Selection/
Arbitration
DMA Sub-Block 1
Arbiter/
Switch
Control
Bus
Switch
FP
I B
u
s
Int
e
rf
ace
0
3
DMA
Channels
10-17
FP
I B
u
s
In
te
rf
ac
e 1
ML
I
In
ter
fa
c
e
Memory
Checker
MLI0
MLI1
System
Peripheral
Bus
Remote
Peripheral
Bus
System Interrupt Nodes
DMA Interrupt Control
CH0n_OUT
MLI Interrupt Nodes
Transaction
Control Unit
CH1n_OUT
Request
Selection/
Arbitration
Transaction
Control Unitl
1
4
2
DMA
Interrupt
Nodes
Clock
Control
DMA
Requests
of
On-chip
Periph.
Units
Address
Decoder
SCU
Flash
