TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual
12-6
V2.0, 2007-07
DMA, V2.0
12.1.4
DMA Channel Functionality
Each of the 2
×
8 DMA channels has one associated register set containing seven 32-bit
registers. These registers are numbered by two indexes to indicate the related DMA
channel: Index “m” refers to the DMA Sub-Block number (m = 0-1) and index “n” refers
to the channel number (n = 0-7) within a DMA Sub-Block.
Example: CHCR14 is the Control Register of DMA channel 4 in Sub-Block 1.
The register set of a DMA channel register contains the following registers:
•
Channel mn Control Register CHCRmn (for details, see
)
•
Channel mn Status Register CHSRmn (for details, see
•
Channel mn Interrupt Control Register CHICRmn (for details, see
•
Channel mn Address Control Register ADRCRmn (for details, see
•
Channel mn Source Address Register SADRmn (for details, see
•
Channel mn Destination Address Register DADRmn (for details, see
)
•
Channel mn Shadow Address Register SHADRmn (for details, see
12.1.4.1 Shadowed Source or Destination Address
As a typical application, an ASC module that receives data (fixed source address) has
to deliver it to a memory buffer using a DMA transaction (variable destination address).
After a certain amount of data has been transferred, a new DMA transaction should be
initiated to deliver further ASC data into another memory buffer. While the destination
address register is updated during a running DMA transaction with the actual destination
address, a shadow mechanism allows programming of a new destination address
without disturbing the content of the destination address register. In this case, the new
destination address is written into a buffer registers, i.e. the shadow address register. At
the start of the next DMA transaction, the new address is transferred from this shadow
address register to the destination address register without CPU intervention. This
shadow mechanism avoids the CPU having to check for the end of a DMA transaction
before reprogramming address registers.
The shadow address register can be used also to store a source address. However, it
cannot store source and destination address at the same time. This means that the
shadow mechanism makes it possible to automatically update either a new source
address, or a new destination address at the start of a DMA transaction. If both address
registers (for source and destination address) have to be updated for the next DMA
transaction, a running DMA transaction for this channel must be finished. After that,
source and destination address registers can be written before the next DMA transaction
is started.
shows the actions that take place when a source address register is
updated. The update of a destination register happens in an equivalent manner.
When writing a new address to the (address of) the source or destination address
register and no DMA transaction is running, the new address value is directly written into
