TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual
23-66
V2.0, 2007-07
MLI, V2.0
exceed one cycle of
f
SYS
.
The frequency in fractional divider mode is defined according the following equation:
(23.2)
The baud rate of MLI transmissions equals
f
TCLK
, that is defined by the frequency of clock
signal
f
MLI
divided by 2 to create the 50% duty cycle of the shift clock signal TCLK. The
signal TCLK toggling with each period of
f
MLI
, a jitter due to fractional dividing is
propagated to TCLK.
(23.3)
23.2.8
Automatic Register Overwrite
The value of register OICR and bit RCR.RCVRST is overwritten by hardware in the next
two clock cycles after a reset (first OICR, followed by RCR). The value applied during
reset is given in the register description. This automatic overwrite allows adapting the
module to different application requirements without changing the module itself. For
example, during reset the receiver is set to a defined state and can be used afterwards
for reception without the need to modify it by a write action (if the bit RCVRST is modified
to 0).
The values applied after the overwrite can be identical to the indicated reset values.
Please refer to the implementation chapter for the modified values (see
f
MLI
=
f
SYS
×
STEP
1024
f
TCLK
=
f
MLI
2
