TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual
3-22
V2.0, 2007-07
Clock, V2.0
3.3
Module Power Management and Clock Gating
Because power dissipation is related to the frequency of gate transitions, the TC1796
performs power management principally by clock gating – that is, controlling whether the
clock is supplied to its various functional units. Gating off the clock to unused functional
modules also reduces electro-magnetic interference (EMI) since EMI is related to both
the frequency and the number of gate transitions.
Clock gating is done either dynamically or statically. Dynamic clock gating in this context
means that the TC1796 itself enables or disables clock signals within some functional
modules to conserve power. Static gating means that software must enable or disable
clock signals to functional modules. Clock gating is performed differently at different
levels of system scope: Dynamic gating is generally performed at the lowest levels,
either within a small region of logic, or at functional-unit boundaries for uncomplicated
functions where hardware can dynamically determine whether that functionality is
required, and can enable or disable it appropriately without software intervention. Static
gating - which requires software intervention - is used to enable or disable clock delivery
to individual high-level functional units, or to disable clock delivery globally at the clock’s
source. When the clock to individual functional units is gated off, they are said to be in
Sleep Mode.
The TC1796 implements three levels of clock gating:
1.
Gated dynamically at the register:
The clock is shut off to a particular local resource in a functional module when this
resource is not being used in that clock cycle. This operation is done primarily in the
CPU and the PCP data paths, where unused resources are easily identified and
controlled in each clock cycle.
2.
Gated dynamically at the functional unit (Idle Mode):
The clock is shut off at the functional unit boundary when the unit has nothing useful
to do. This operation is done primarily in the CPU and the PCP. For the CPU, idle
mode is controlled via software. The PCP disables its own clock when no program is
running.
3.
Gated statically at each functional unit (Sleep Mode):
Software can send a global sleep request to individual functional units requesting that
they enter Sleep Mode. Software must determine when conditions are such that
entering Sleep Mode is appropriate. The individual units can be programmed to
ignore or respond to this signal. If programmed to respond, units will first complete
pending operations, then will shut off their own clocks according to their own criteria.
