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Infineon Technologies TC1796, User Manual

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TC1796

System Units (Vol. 1 of 2)

Direct Memory Access Controller

 

User’s Manual

12-114

V2.0, 2007-07

DMA, V2.0

 

The Memory Checker Write Register is a dummy write-only register that is located within
the memory checker address range. This register is near by (above) the MLI address
range of the TC1796. It has no meaning for memory checker operation.
The Memory Checker Write Register can be used as dummy write register at the write
back action of the DMA or MLI controller Move Engines when the pattern detection
feature of the DMA controller is used. Accessing MCHK_WR with the Move Engines of
the MLI or DMA controller via the Bus Switch of the DMA controller (see 

Figure 12-14

)

does not request the two FPI buses of the TC1796, SPB and RPB, because it is near the
MLI modules address ranges.

MCHK_WR 
Memory Checker Write Register

(20

H

)

Reset Value: 0000 0000

H

31

0

WO

w

Field

Bits

Type Description

WO

[31:0]

w

Write-Only

This write-only bit field is used to write dummy data 
during DMA pattern detection. The data written to 
WO is not taken into account for any action. Any read 
action of WO will deliver 0000 0000

H

.

Summary of Contents for TC1796

Page 1: ...User s Manual V2 0 July 2007 Microcontrollers TC1796 32 Bit Single Chip Microcontroller Volume 1 of 2 System Units Volume 2 of 2 Peripheral Units ...

Page 2: ...y terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written a...

Page 3: ...User s Manual V2 0 July 2007 Microcontrollers TC1796 32 Bit Single Chip Microcontroller Volume 1 of 2 System Units Volume 2 of 2 Peripheral Units ...

Page 4: ... 1 34 Figure 1 11 is updated 1 37 1 38 Footnote marking for EBU pins is removed pad driver class for BFCLKI is added 1 53 Pad driver classes for several System I O pins are updated added 1 58 Table 1 6 is added 2 10 CPU_ID is added 2 12 MMU_CON long register name is updated 2 13 CPS_ID is added 2 14 CPU_SRCn TOS bit description is updated 2 21 Offset addresses in Table 2 6 are updated by absolute ...

Page 5: ...egister 8 7 Section 8 5 2 is updated 8 10 8 11 DMU_ID is added 9 5 9 7 9 9 Short name for SBRAM and SPRAM is updated 11 52 11 54 PCP_ID is added 11 59 PCP_ES bit 5 is updated 11 74 Counter Reload Value COPY in Table 11 13 is updated 11 78 Figure 11 14 is updated 11 103 Syntax description of ST PI is updated 12 9 Figure 12 5 is updated 12 10 Figure 12 6 is updated 12 16 Section 12 1 4 5 is updated ...

Page 6: ...n Figure 20 11 corrected TB write operation in Section 20 1 2 11 is updated 20 24 20 31 20 33 SSC error interrupt control in Section 20 1 2 12 and bit description STIP EN are updated 20 27 20 29 SSC0_ID and SSC1_ID registers are added 20 37 20 39 Notes below register SSOC and SSOTC are updated 21 26 Figure 21 18 is updated sampling start 21 36 21 38 MSC0_ID and MSC1_ID registers are added 21 42 Bi...

Page 7: ...ter description of RPxBAR x 0 3 is updated 23 129 Equation 23 6 is added 23 142 Selected address range for AEN21 corrected 24 31 24 32 24 33 24 34 Figure 24 20 Figure 24 21 Figure 24 22 and Figure 24 23 are updated 24 61 24 77 Cell Enabling on Event sections for GTC and LTC are updated 24 76 Header of Table 24 4 is updated 24 150 24 151 24 154 GPTA0_ID and GPTA1_ID registers are added 24 233 24 23...

Page 8: ...29 FADC_ID register is added TC1796 User s Manual Volume 1 of 2 System Units Volume 2 of 2 Peripheral Units Revision History V2 0 2007 07 We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to m...

Page 9: ... Controller 1 21 1 1 3 1 5 Micro Link Serial Bus Interface 1 24 1 1 3 2 General Purpose Timer Array 1 26 1 1 3 2 1 Functionality of GPTA0 and GPTA1 1 27 1 1 3 2 2 Functionality of LTCA2 1 29 1 1 3 3 Analog to Digital Converters 1 30 1 1 3 3 1 Analog to Digital Converters ADC0 and ADC1 1 30 1 1 3 3 2 Fast Analog to Digital Converter Unit FADC 1 32 1 1 4 TC1796 Pin Definitions and Functions 1 34 1 1...

Page 10: ...on specific Memory Protection Registers 2 23 1 2 5 Program Memory Interface PMI 2 24 1 2 5 1 PMI Features 2 24 1 2 5 2 Parity Protection for PMI Memories 2 25 1 2 5 3 PMI Registers 2 26 1 2 5 3 1 PMI Module Identification Register 2 27 1 2 5 3 2 PMI Control Register 0 2 28 1 2 5 3 3 PMI Control Register 1 2 29 1 2 5 3 4 PMI Control Register 2 2 30 1 2 6 Data Memory Interface DMI 2 31 1 2 6 1 DMI F...

Page 11: ...ock Recovery 3 19 1 3 2 3 Power on Startup Operation 3 21 1 3 3 Module Power Management and Clock Gating 3 22 1 3 3 1 Module Clock Generation 3 23 1 3 3 2 Clock Control Register CLC 3 24 1 3 3 3 Fractional Divider Operation 3 29 1 3 3 3 1 Overview 3 29 1 3 3 3 2 Fractional Divider Operating Modes 3 32 1 3 3 3 3 Fractional Divider Register 3 35 1 3 3 4 Module Clock Register Implementations 3 39 1 3...

Page 12: ...Idle Mode 5 5 1 5 1 3 2 Sleep Mode 5 6 1 5 1 3 3 States of TC1796 Units in Power Management Modes 5 7 1 5 2 Configuration Input Sampling 5 8 1 5 3 External Request Unit ERU 5 9 1 5 3 1 Input Channel 5 10 1 5 3 2 Output Channel 5 12 1 5 3 3 External Request Unit Implementation 5 14 1 5 3 4 External Request Unit Registers 5 16 1 5 4 Special System Interrupts 5 35 1 5 4 1 FPU Interrupts 5 35 1 5 4 2 ...

Page 13: ...LMB Basic Operation 6 4 1 6 2 Local Memory Bus Controller Units 6 5 1 6 2 1 Basic Operation 6 5 1 6 2 2 LMB Bus Arbitration 6 5 1 6 2 2 1 LMB Bus Default Master 6 6 1 6 2 3 LMB Bus Error Handling 6 6 1 6 2 4 DLMB and PLMB Bus Registers 6 7 1 6 3 Local Memory to FPI Bus Interface LFI Bridge 6 15 1 6 3 1 Functional Overview 6 15 1 6 3 2 LFI Register 6 16 1 6 4 System and Remote Peripheral Bus 6 19 1...

Page 14: ...tions 7 14 1 7 2 5 1 Reset to Read Command 7 15 1 7 2 5 2 Enter Page Mode Command 7 15 1 7 2 5 3 Load Page Buffer Command 7 16 1 7 2 5 4 Write Page Command 7 18 1 7 2 5 5 Write User Configuration Page Command 7 19 1 7 2 5 6 Erase Sector Command 7 20 1 7 2 5 7 Erase User Configuration Block Command 7 22 1 7 2 5 8 Disable Write Protection Command 7 23 1 7 2 5 9 Disable Read Protection Command 7 24 1...

Page 15: ...2 Emulation Memory Overlay 8 7 1 8 5 3 Switching between Internal and Emulation Memory Overlay 8 7 1 8 5 4 Region Priority 8 7 1 8 5 5 Access Performance 8 7 1 8 6 Program Local Memory Bus Interface LMI 8 8 1 8 6 1 Data Read Buffer 8 8 1 8 7 DMU Registers 8 10 1 9 Memory Maps 9 1 1 9 1 How to Read the Address Maps 9 1 1 9 2 Contents of the Segments 9 4 1 9 3 Address Map of the FPI Bus System 9 6 1...

Page 16: ... Output Register 10 37 1 10 5 3 2 Port 2 Output Modification Register 10 37 1 10 5 3 3 Port 2 Input Output Control Register 0 10 38 1 10 5 3 4 Port 2 Input Register 10 38 1 10 5 3 5 Port 2 Emergency Stop Register 10 38 1 10 5 3 6 Port 2 Pad Driver Mode Register and Pad Classes 10 39 1 10 6 Port 3 10 40 1 10 6 1 Port 3 Configuration 10 40 1 10 6 2 Port 3 Function Table 10 41 1 10 6 3 Port 3 Registe...

Page 17: ... 1 10 11 3 Port 8 Register 10 73 1 10 11 3 1 Port 8 Output Register 10 73 1 10 11 3 2 Port 8 Output Modification Register 10 73 1 10 11 3 3 Port 8 Input Register 10 73 1 10 11 3 4 Port 8 Emergency Stop Register 10 73 1 10 11 3 5 Port 8 Pad Driver Mode Register and Pad Classes 10 74 1 10 12 Port 9 10 75 1 10 12 1 Port 9 Configuration 10 75 1 10 12 2 Port 9 Function Table 10 76 1 10 12 3 Port 9 Regi...

Page 18: ...1 11 3 2 4 Context Save Operation for CR6 and CR7 11 21 1 11 3 2 5 Initialization of the Contexts 11 24 1 11 3 2 6 Context Save Optimization 11 24 1 11 3 3 Channel Programs 11 25 1 11 3 3 1 Channel Restart Mode 11 25 1 11 3 3 2 Channel Resume Mode 11 26 1 11 4 PCP Operation 11 28 1 11 4 1 PCP Initialization 11 28 1 11 4 2 Channel Invocation and Context Restore Operation 11 28 1 11 4 3 Channel Exit...

Page 19: ...k Control Register PCP_CLC 11 55 1 11 10 3 PCP Control and Status Register PCP_CS 11 56 1 11 10 4 PCP Error Debug Status Register PCP_ES 11 59 1 11 10 5 PCP Interrupt Control Register PCP_ICR 11 61 1 11 10 6 PCP Interrupt Threshold Register PCP_ITR 11 63 1 11 10 7 PCP Interrupt Configuration Register PCP_ICON 11 64 1 11 10 8 PCP Stall Status Register PCP_SSR 11 66 1 11 10 9 PCP Service Request Con...

Page 20: ...R Logical OR 11 97 1 11 11 28 PRI Prioritize 11 98 1 11 11 29 PRAM Bit Operations 11 99 1 11 11 30 RL Rotate Left 11 100 1 11 11 31 RR Rotate Right 11 100 1 11 11 32 SET Set Bit 11 101 1 11 11 33 SHL Shift Left 11 101 1 11 11 34 SHR Shift Right 11 102 1 11 11 35 ST Store 11 103 1 11 11 36 SUB 32 Bit Subtract 11 104 1 11 11 37 XCH Exchange 11 105 1 11 11 38 XOR 32 Bit Logical Exclusive OR 11 106 1 ...

Page 21: ...iption 12 2 1 12 1 1 Features 12 3 1 12 1 2 Definition of Terms 12 4 1 12 1 3 DMA Principles 12 5 1 12 1 4 DMA Channel Functionality 12 6 1 12 1 4 1 Shadowed Source or Destination Address 12 6 1 12 1 4 2 DMA Channel Request Control 12 10 1 12 1 4 3 DMA Channel Operation Modes 12 11 1 12 1 4 4 Error Conditions 12 15 1 12 1 4 5 Channel Reset Operation 12 16 1 12 1 4 6 Transfer Count and Move Count 1...

Page 22: ... MLI Service Request Control Registers 12 107 1 12 3 3 4 System Interrupt Service Request Control Register 12 108 1 12 3 4 DMA Controller Address Map 12 109 1 12 4 Memory Checker Module 12 110 1 12 4 1 Functional Description 12 110 1 12 4 2 Registers 12 111 1 12 4 2 1 Memory Checker Registers 12 112 1 13 LMB External Bus Unit 13 1 1 13 1 Block Diagram 13 2 1 13 2 EBU Interface Signals 13 3 1 13 2 ...

Page 23: ...ccess Modes 13 36 1 13 5 6 PLMB Bus Width Translation 13 37 1 13 5 7 Address Alignment During Bus Accesses 13 38 1 13 6 PLMB Data Buffering 13 39 1 13 6 1 Data Read Buffer 13 39 1 13 6 2 Code Prefetch Buffer 13 40 1 13 6 3 Data Write Buffer 13 40 1 13 7 Standard Access Phases 13 41 1 13 7 1 Address Phase AP 13 41 1 13 7 2 Command Delay Phase CD 13 43 1 13 7 3 Command Phase CP 13 43 1 13 7 4 Data H...

Page 24: ...ion Register CON 13 83 1 13 10 4 Burst Flash Control Register BFCON 13 86 1 13 10 5 Address Select Register ADDRSELx 13 90 1 13 10 6 Bus Configuration Register BUSCONx 13 92 1 13 10 7 Bus Access Parameter Register BUSAPx 13 97 1 13 10 8 Emulator Address Select Register EMUAS 13 101 1 13 10 9 Emulator Bus Configuration Register EMUBC 13 102 1 13 10 10 Emulator Bus Access Parameter Register EMUBAP 1...

Page 25: ...Interrupt Priority 1 14 22 1 14 8 7 Software Initiated Interrupts 14 22 1 14 8 8 External Interrupts 14 22 1 14 9 Service Request Node Table 14 23 1 14 10 Non Maskable Interrupt 14 25 1 14 10 1 External NMI Input 14 25 1 14 10 2 Phase Locked Loop NMI 14 25 1 14 10 3 Watchdog Timer NMI 14 25 1 14 10 4 SRAM Parity Error NMI 14 26 1 14 10 5 NMI Enable 14 27 1 14 10 6 NMI Status Register 14 27 1 15 Sy...

Page 26: ...ower Saving Modes 16 21 1 16 5 Handling the Watchdog Timer 16 22 1 16 5 1 System Initialization 16 22 1 16 5 2 Re opening Access to Critical System Registers 16 23 1 16 5 3 Servicing the Watchdog Timer 16 23 1 16 5 4 Handling the User Definable Password Field 16 24 1 16 5 5 Determining the Required Values for a WDT Access 16 27 1 16 6 Watchdog Timer Registers 16 28 1 16 6 1 Watchdog Timer Control ...

Page 27: ... 17 4 Debug Interface Cerberus 17 12 1 17 4 1 RW Mode 17 12 1 17 4 2 Communication Mode 17 13 1 17 4 3 Triggered Transfers 17 13 1 17 4 4 Multi Core Break Switch 17 13 1 17 5 JTAG Interface 17 15 1 17 6 Cerberus and JTAG Registers 17 16 1 18 Register Overview 18 1 1 18 1 Address Map of Segment 15 18 2 1 18 2 Registers Tables 18 7 1 ...

Page 28: ... Synchronous Mode 19 16 2 19 1 6 Hardware Error Detection Capabilities 19 17 2 19 1 7 Interrupts 19 17 2 19 2 ASC Kernel Registers 19 19 2 19 2 1 Identification Register 19 20 2 19 2 2 Control Registers 19 21 2 19 2 3 Data Registers 19 28 2 19 3 ASC0 ASC1 Module Implementation 19 30 2 19 3 1 Interfaces of the ASC Modules 19 30 2 19 3 2 ASC0 ASC1 Module Related External Registers 19 31 2 19 3 2 1 A...

Page 29: ...ers 20 59 2 20 3 3 DMA Requests 20 60 2 21 Micro Second Channel MSC 21 1 2 21 1 MSC Kernel Description 21 3 2 21 1 1 Overview 21 3 2 21 1 2 Downstream Channel 21 5 2 21 1 2 1 Frame Formats and Definitions 21 6 2 21 1 2 2 Shift Register Operation 21 12 2 21 1 2 3 Transmission Modes 21 14 2 21 1 2 4 Downstream Counter and Enable Signals 21 19 2 21 1 2 5 Baud Rate 21 20 2 21 1 2 6 Abort of Frames 21 ...

Page 30: ...Controller Service Requests 21 77 2 21 3 6 Interrupt Control Registers 21 78 2 22 Controller Area Network MultiCAN Controller 22 1 2 22 1 CAN Basics 22 2 2 22 1 1 Addressing and Bus Arbitration 22 2 2 22 1 2 CAN Frame Formats 22 3 2 22 1 2 1 Data Frames 22 3 2 22 1 2 2 Remote Frames 22 5 2 22 1 2 3 Error Frames 22 7 2 22 1 3 The Nominal Bit Time 22 8 2 22 1 4 Error Detection and Error Handling 22 ...

Page 31: ...it Acceptance Filtering 22 38 2 22 3 9 Message Postprocessing 22 40 2 22 3 9 1 Message Object Interrupts 22 40 2 22 3 9 2 Pending Messages 22 42 2 22 3 10 Message Object Data Handling 22 44 2 22 3 10 1 Frame Reception 22 44 2 22 3 10 2 Frame Transmission 22 47 2 22 3 11 Message Object Functionality 22 50 2 22 3 11 1 Standard Message Object 22 50 2 22 3 11 2 Single Data Transfer Mode 22 50 2 22 3 1...

Page 32: ... 22 142 2 22 6 4 1 Instructions During a Basic Cycle 22 142 2 22 6 4 2 Instructions at the End of a Basic Cycle 22 143 2 22 6 5 Scheduler Instruction Sequence 22 145 2 22 6 5 1 BCC and CSM 22 145 2 22 6 5 2 General Instruction Sequence Rules 22 146 2 22 6 5 3 Scheduler Sequence Example 22 147 2 22 7 TTCAN Operation 22 148 2 22 7 1 Configuration 22 148 2 22 7 2 Configuration Error 22 148 2 22 7 3 S...

Page 33: ...2 23 1 1 1 MLI Overview 23 2 2 23 1 1 2 Naming Conventions 23 3 2 23 1 1 3 MLI Communication Principles 23 6 2 23 1 2 MLI Frame Structure 23 10 2 23 1 2 1 General Frame Layout 23 11 2 23 1 2 2 Copy Base Address Frame 23 12 2 23 1 2 3 Write Offset and Data Frame 23 13 2 23 1 2 4 Optimized Write Frame 23 14 2 23 1 2 5 Discrete Read Frame 23 15 2 23 1 2 6 Optimized Read Frame 23 16 2 23 1 2 7 Command...

Page 34: ...vent 23 61 2 23 2 6 3 Normal Frame Received Move Engine Terminated Event 23 62 2 23 2 6 4 Interrupt Command Frame Event 23 63 2 23 2 6 5 Command Frame Received Event 23 64 2 23 2 7 Baud Rate Generation 23 65 2 23 2 8 Automatic Register Overwrite 23 66 2 23 3 Operating the MLI 23 67 2 23 3 1 Connection Setup 23 68 2 23 3 2 Local Transmitter and Pipe Setup 23 69 2 23 3 3 Remote Receiver Setup 23 69 ...

Page 35: ...0 and GPTA1 24 3 2 24 1 2 Functionality of LTCA2 24 5 2 24 2 GPTA0 GPTA1 Kernel Description 24 6 2 24 2 1 GTPA Units 24 7 2 24 2 2 Clock Generation Unit 24 8 2 24 2 2 1 Filter and Prescaler Cell FPC 24 10 2 24 2 2 2 Phase Discrimination Logic PDL 24 19 2 24 2 2 3 Duty Cycle Measurement Unit DCM 24 24 2 24 2 2 4 Digital Phase Locked Loop Cell PLL 24 28 2 24 2 2 5 Clock Distribution Unit CDU 24 35 2...

Page 36: ...egisters 24 194 2 24 3 12 Service Request Registers 24 206 2 24 4 LTCA2 Kernel Description 24 217 2 24 4 1 Local Timer Cell LTC00 to LTC62 24 218 2 24 4 2 Input Output Line Sharing Unit IOLS 24 218 2 24 4 2 1 Output Multiplexer 24 221 2 24 4 2 2 LTC Input Multiplexing Scheme 24 225 2 24 4 2 3 Multiplexer Register Array Programming 24 229 2 24 4 3 Interrupt Sharing Unit IS 24 231 2 24 5 LTCA2 Kerne...

Page 37: ...n Request Source External Event 25 11 2 25 1 2 5 Parallel Conversion Request Source Software 25 14 2 25 1 2 6 Parallel Conversion Request Source Auto Scan 25 15 2 25 1 2 7 Sequential Conversion Request Source Channel Injection 25 21 2 25 1 2 8 Sequential Conversion Request Source Queue 25 25 2 25 1 3 Conversion Request Arbitration 25 29 2 25 1 3 1 Source Arbitration Level 25 30 2 25 1 3 2 Arbitrat...

Page 38: ... 2 25 2 4 Queue Registers 25 69 2 25 2 5 External Trigger Registers 25 73 2 25 2 6 Auto Scan Registers 25 75 2 25 2 7 Other Control Status Registers 25 78 2 25 2 8 Channel Inject Register 25 90 2 25 2 9 Software Request Registers 25 92 2 25 2 10 Service Request Registers 25 94 2 25 3 Implementation of ADC0 ADC1 25 100 2 25 3 1 Interface Connections of the ADC Modules 25 100 2 25 3 2 ADC0 ADC1 Modu...

Page 39: ...Result Registers 26 20 2 26 1 7 Neighbor Channel Trigger 26 21 2 26 1 8 Offset and Gain Calibration 26 22 2 26 1 8 1 Offset Calibration 26 23 2 26 1 8 2 Gain Calibration 26 23 2 26 1 9 Interrupt Generation 26 24 2 26 2 FADC Kernel Registers 26 27 2 26 2 1 Identification Register 26 29 2 26 2 2 Global Registers 26 30 2 26 2 3 Channel Registers 26 41 2 26 2 4 Filter Registers 26 48 2 26 3 Implementa...

Page 40: ...ure For example where the TriCore Architecture specifies up to four Memory Protection Register Sets the TC1796 implements but two Such differences between the TC1796 and the TriCore Architecture are documented in the text covering each such subject 1 1 1 Related Documentations A complete description of the TriCore architecture is found in the document entitled TriCore Architecture Manual The archi...

Page 41: ...iven where the register expression is first used for example n 31 0 and are repeated as needed in the rest of the text The default radix is decimal Hexadecimal constants are suffixed with a subscript letter H as in 100H Binary constants are suffixed with a subscript letter B as in 111B When the extent of register fields groups of signals or groups of pins are collectively named in the body of the ...

Page 42: ...ndicating that the behavior of the TC1796 is undefined for that combination of bits Setting the register to such undefined bit or bit field combinations may lead to unpredictable results Such bit combinations are reserved When writing software must always set such bit fields to legal values as defined for it rw The bit or bit field can be read and written rwh As rw but bit or bit field can be also...

Page 43: ...y 32 bit word accesses are permitted to this register address range E Endinit protected register address PW Password protected register address NC No change indicated register is not changed BE Indicates that an access to this address range generates a Bus Error nBE Indicates that no Bus Error is generated when accessing this address range even though it is either an access to an undefined address...

Page 44: ...CAN Controller Area Network CMEM PCP Code Memory CISC Complex Instruction Set Computing CPS CPU Slave Interface CPU Central Processing Unit CSA Context Save Area CSFR Core Special Function Register DBCU Data Local Memory Bus Control Unit DFLASH Data Flash Memory DGPR Data General Purpose Register DMA Direct Memory Access DMI Data Memory Interface DMU Data Memory Unit DPRAM Dual Port RAM EBU Extern...

Page 45: ...ocal Timer Cell Array MLI Micro Link Interface MMU Memory Management Unit MSB Most Significant Bit MSC Micro Second Channel NMI Non Maskable Interrupt OCDS On Chip Debug Support OVRAM Code Overlay Memory PBCU Program Local Memory Bus Control Unit PCP Peripheral Control Processor PFLASH Program Flash Memory PMI Program Memory Interface PMU Program Memory Unit PLL Phase Locked Loop PLMB Program Loca...

Page 46: ...SBCU System Peripheral Bus Control Unit SBRAM Stand by Data Memory SCU System Control Unit SFR Special Function Register SPB System Peripheral Bus SPRAM Scratch Pad RAM SRAM Static Data Memory SRN Service Request Node SSC Synchronous Serial Controller STM System Timer WDT Watchdog Timer ...

Page 47: ...des Peripheral Control Processor standalone data operations and interrupt servicing DMA Controller DMA operations and interrupt servicing General purpose timers High performance on chip buses On chip debugging and emulation facilities Flexible interconnections to external components Flexible power management The TC1796 is a high performance microcontroller with TriCore CPU program and data memorie...

Page 48: ...DPRAM BROM PFLASH DFLASH SBRAM SRAM PRAM CMEM PLMB DLMB RPB SPB shaded DMA BI0 BI1 SMIF DMI 56 KB LDRAM 8 KB DPRAM CPS EBU Scratch Pad RAM Instruction cache Local data RAM Dual port RAM Boot ROM Program Flash Memory Data Flash Memory Stand by Data Memory Data Memory PCP Parameter Memory PCP Code Memory Program Local Memory Bus Data Local Memory Bus Remote Peripheral Bus System Peripheral Bus only ...

Page 49: ...tructions for reduced code size Data types include Boolean array of bits character signed and unsigned integer integer with saturation signed fraction double word integers and IEEE 754 single precision floating point Data formats include Bit 8 bit byte 16 bit half word 32 bit word and 64 bit double word data formats Powerful instruction set Flexible and efficient addressing mode for high code dens...

Page 50: ... memory or I O locations Data move until predefined limit reached supported Read Modify Write capabilities Full computation capabilities including basic MUL DIV Read move data and accumulate it to previously read data Read two data values and perform arithmetic or logical operation and store result Bit handling capabilities testing setting clearing Flow control instructions conditional uncondition...

Page 51: ... detection Two Synchronous Serial Channels SSC with programmable data length and shift direction Two Micro Second Channel Interfaces MSC for serial communication One CAN Module with four CAN nodes MultiCAN for high efficiency data handling via FIFO buffering and gateway data transfer Two Micro Link Serial Bus Interfaces MLI for serial multiprocessor communication Two General Purpose Timer Arrays G...

Page 52: ...ineon 32 bit microcontroller includes the following tools Embedded Development Environment for TriCore Products The TC1796 On chip Debug Support OCDS provides a JTAG port for communication between external hardware and the system Two Flexible Peripheral Interconnect Buses FPI Bus for on chip interconnections and its FPI Bus control units SBCU RBCU The System Timer STM with high precision long rang...

Page 53: ...orld The peripherals mentioned in this overview section are all described in detail in the chapters of the TC1796 Peripheral Units Vol 2 of 2 User s Manual part 1 3 1 Serial Interfaces The TC1796 includes eight four CAN serial peripheral interface units Two Asynchronous Synchronous Serial Interfaces ASC0 and ASC1 Two high speed Synchronous Serial Interfaces SSC0 and SSC1 Two Micro Second Channel I...

Page 54: ... selected Parity framing and overrun error detection are provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism is included to distinguish address bytes from data bytes Testing is supported by a loop back option A 13 bit baud rate generator provides the ASC with a separate serial clock signal which c...

Page 55: ... 4 69 MBaud to 1 12 Baud 75 MHz clock Multiprocessor mode for automatic address data byte detection Loop back capability Half duplex 8 bit synchronous operating mode Baud rate from 9 38 Mbit s to 763 Bit s 75 MHz clock Double buffered transmitter receiver Interrupt generation On a transmit buffer empty condition On a transmit last bit of a frame condition On a receive buffer full condition On an e...

Page 56: ...and reception of data are double buffered A shift clock generator provides the SSC with a separate serial clock signal One slave select input are available for Slave Mode operation Eight programmable slave select outputs chip selects are supported in Master Mode Note The SSC0 contains an 8 stage Receive and Transmit FIFO The SSC1 does not provide any FIFO functionality Features Master and Slave Mo...

Page 57: ...ition On an error condition receive phase baud rate transmit error Flexible SSC pin configuration Seven slave select inputs SLSI 7 1 in Slave Mode Eight programmable slave select outputs SLSO 7 0 in Master Mode Automatic SLSO generation with programmable timing Programmable active level and enable control SSC0 only 8 stage Receive FIFO RXFIFO and 8 stage Transmit FIFO TXFIFO Independent control of...

Page 58: ... enable signals One out of eight input lines SDI 7 0 is used as serial data input signal for the upstream channel The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided on the ALTINL ALTINH input lines These input lines are typically connected to other on chip peripheral units for example with a timer unit such as the GPTA An...

Page 59: ...erial clock fMSC Command data and passive frame types Start of serial frame Software controlled timer controlled or free running Programmable upstream data frame length 16 or 12 bits Transmission with or without SEL bit Flexible chip select generation indicates status during serial frame transmission Emergency stop without CPU intervention Low speed asynchronous serial reception on upstream channe...

Page 60: ...e and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers All four CAN nodes share a common set of message objects Each message object can be individually allocated to one of the CAN nodes Besides serving as a storage container for incoming and outgoing frames message objects can be combined to build gateways between the CAN nodes or to set up a FIFO...

Page 61: ...ame counter Full CAN functionality A set of 128 message objects can be individually Allocated assigned to any CAN node Configured as transmit or receive object Set up to handle frames with 11 bit or 29 bit identifier Identified by a timestamp via a frame counter Configured to remote monitoring mode Advanced acceptance filtering Each message object provides an individual acceptance mask to filter i...

Page 62: ...ed for CAN node 0 by an extension module that supports TTCAN functionality The TTCAN protocol is compliant with the confirmed standardization proposal for ISO 11898 4 and fully conforms to the existing CAN protocol The time triggered functionality is added as higher layer extension session layer to the CAN protocol in order to be able to operate in safety critical applications The new features all...

Page 63: ...ro Link Interface Connection Features Synchronous serial communication between MLI transmitters and MLI receivers located on the same or on different microcontroller devices Automatic data transfer request transactions between local remote controller Fully transparent read write access supported remote programming Complete address range of remote controller available Specific frame protocol to tra...

Page 64: ...ing A B C and D The transmitter signals are named with the prefix T and the receiver signals are named with the prefix R Data read and write operations from to remote window areas can be handled by a Move Engine that is able to operate as a bus master Clock control address decoding and interrupt service request control are managed outside the MLI module kernel Eight service request outputs can be ...

Page 65: ... applications Figure 1 8 General Block Diagram of the GPTA Modules Signal Generation Unit MCB05580 GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GTC01 GTC00 GTC31 Global Timer Cell Array GTC03 GTC30 Clock Bus GPTA0 Clock Generation Unit Signal Generation Unit GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GTC01 GTC00 GT...

Page 66: ...nternal compare operation GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform Local Timer Cells LTC operating in Timer Capture or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform LTCs enabled in Timer Mode or Capture Mode can be clocked or triggered by various external or internal...

Page 67: ...LTC prescaler clock Signal Generation Unit Global Timers GT Two independent units Two operating modes Free Running Timer and Reload Timer 24 bit data width fGPTA maximum resolution fGPTA 2 maximum input signal frequency Global Timer Cell GTC 32 units related to the Global Timers Two operating modes Capture Compare and Capture after Compare 24 bit data width fGPTA maximum resolution fGPTA 2 maximum...

Page 68: ...ng inputs and outputs from internal clocks FPC GTC LTC ports and MSC interface 1 3 2 2 Functionality of LTCA2 64 Local Timer Cells LTCs Three basic operating modes Timer Capture and Compare for 63 units Special compare modes for one unit 16 bit data width fGPTA maximum resolution fGPTA 2 maximum input signal frequency ...

Page 69: ...ding sample hold functionality The A D converters operate by the method of successive approximation A multiplexer selects up to 32 analog inputs that can be connected to the 16 conversion channels in each ADC module An automatic self calibration adjusts the ADC modules to changing temperatures or process variations Features 8 bit 10 bit 12 bit A D conversion Conversion time below 2 5 µs 10 bit res...

Page 70: ... module kernel A synchronization bridge is used for synchronization of two ADC modules External trigger conditions are controlled by an External Request Unit This unit generates the control signals for auto scan control ASGT software trigger control SW0TR SW0GT the event trigger control ETR EGT queue control QTR QGT and timer trigger control TTR TGT Interrupt Control Clock Control Address Decoder ...

Page 71: ...ain calibration support for each channel Differential input amplifier with programmable gain of 1 2 4 and 8 for each channel Free running Channel Timers or triggered conversion modes Trigger and gating control for external signals Built in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable programmable antialiasing and data red...

Page 72: ...ialiasing and data reduction filters The Channel Trigger Control block determines the trigger and gating conditions for the four FADC channels The Channel Timers can independently trigger the conversion of each FADC channel The A D Control block is responsible for the overall FADC functionality The FADC module is supplied by the following power supply and reference voltage lines VDDMF VDDMF FADC A...

Page 73: ...r Supply VDDP 11 VDDFL3 VDDSBRAM TC1796 VFAREF VFAGND VDDMF VSSMF FADC Analog Power Supply VAREFx VAGNDx VDDM VSSM ADC0 ADC1 Analog Power Supply AN 43 0 ADC Analog Inputs Port 0 Port 1 Port 2 Port 4 Port 5 Port 3 GPTA SSC0 SSC1 GPTA D 31 0 A 23 0 Chip Select External Bus Unit Interface Control BFCLKI BFLCKO Port 6 Port 7 Port 8 Port 9 Port 10 MLI0 SCU ASC0 ASC1 MSC0 MSC1 MLI0 ASC0 ASC1 SSC1 CAN AD...

Page 74: ...D25 D28 D15 D20 D21 D11 D17 D22 D10 D14 D18 D7 D12 D16 D4 D8 D13 D2 D5 D9 D0 D3 D1 D6 D19 VSS A0 A1 A2 A21 A23 A22 A19 A20 A18 A16 A17 A14 A12 A11 A10 A13 A7 A8 A6 A3 A4 A9 A5 A15 VSS BRK OUT TDO TCK TDI TRST BRK IN TMS XTAL 2 XTAL 1 TST RES VSS OSC VDD OSC VDD OSC3 P0 14 P0 9 P0 5 P0 6 P0 2 P0 4 P0 8 P0 1 P0 3 P0 7 P0 12 P0 10 P0 13 P0 11 P0 0 P3 15 P3 7 P3 14 P3 6 P3 10 P3 8 P3 9 P3 12 P3 4 P3 1...

Page 75: ... I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O B1 VDDEBU EBU Data Bus Lines The EBU Data Bus Lines D 31 0 serve as external data bus Data bus line 0 Data bus line 1 Data bus line 2 Data bus line 3 Data bus line 4 Data bus line 5 Data bus line 6 Data bus line 7 Data bus line 8 Data bus line 9 Data bus line 10 Data bus line 11 Data bus line 12 Data b...

Page 76: ... line 6 Address bus line 7 Address bus line 8 Address bus line 9 Address bus line 10 Address bus line 11 Address bus line 12 Address bus line 13 Address bus line 14 Address bus line 15 Address bus line 16 Address bus line 17 Address bus line 18 Address bus line 19 Address bus line 20 Address bus line 21 Address bus line 22 Address bus line 23 CS0 CS1 CS2 CS3 AE21 AD21 AD20 AD19 O O O O B1 VDDEBU C...

Page 77: ...lid Output BC0 BC1 BC2 BC3 AE17 AD17 AF18 AE18 O O O O B1 Byte Control Lines Byte control line 0 Byte control line 1 Byte control line 2 Byte control line 3 MR W AF19 O B1 Motorola style Read Write Control Signal WAIT AE20 I Wait Input for inserting Wait States BAA AF23 O B1 Burst Address Advance Output HOLD AF17 I Hold Request Input HLDA AD18 O B1 Hold Acknowledge Output BREQ AD22 O B1 Bus Reques...

Page 78: ...1 Port 0 I O line 2 Port 0 I O line 3 Port 0 I O line 4 Port 0 I O line 5 Port 0 I O line 6 Port 0 I O line 7 Port 0 I O line 8 Port 0 I O line 9 Port 0 I O line 10 Port 0 I O line 11 Port 0 I O line 12 Port 0 I O line 13 Port 0 I O line 14 Port 0 I O line 15 The states of the Port 0 pins are latched into the software configuration input register SCU_SCLIR at the rising edge of HDRST In the differ...

Page 79: ... TVALID0A TDATA0 RCLK0A RREADY0A RVALID0A RDATA0A SYSCLK RCLK0B RVALID0B RDATA0B External trigger input 0 External trigger input 1 External trigger input 3 External trigger input 2 MLI0 transmit channel ready input B MLI0 transmit channel clock output MLI0 transmit channel ready input A MLI0 transmit channel valid output A MLI0 transmit channel data output MLI0 receive channel clock input A MLI0 r...

Page 80: ...O6 SLSO7 Slave select output line 2 Slave select output line 3 Slave select output line 4 Slave select output line 5 Slave select output line 6 Slave select output line 7 P2 8 P2 9 P2 10 P2 11 P2 12 P2 13 P2 14 P2 15 C2 A2 B3 C3 C4 A3 B4 A4 I O I O I O I O I O I O I O I O A1 A1 A1 A1 A1 A1 A1 A1 IN0 OUT0 line of GPTA IN1 OUT1 line of GPTA IN2 OUT2 line of GPTA IN3 OUT3 line of GPTA IN4 OUT4 line o...

Page 81: ...eneral purpose I O port which can be alternatively used for GPTA I O lines IN8 OUT8 line of GPTA IN9 OUT9 line of GPTA IN10 OUT10 line of GPTA IN11 OUT11 line of GPTA IN12 OUT12 line of GPTA IN13 OUT13 line of GPTA IN14 OUT14 line of GPTA IN15 OUT15 line of GPTA IN16 OUT16 line of GPTA IN17 OUT17 line of GPTA IN18 OUT18 line of GPTA IN19 OUT19 line of GPTA IN20 OUT20 line of GPTA IN21 OUT21 line o...

Page 82: ...4 Port 4 is a 16 bit bi directional general purpose I O port which can be alternatively used for GPTA I O lines IN24 OUT24 line of GPTA IN25 OUT25 line of GPTA IN26 OUT26 line of GPTA IN27 OUT27 line of GPTA IN28 OUT28 line of GPTA IN29 OUT29 line of GPTA IN30 OUT30 line of GPTA IN31 OUT31 line of GPTA IN32 OUT32 line of GPTA IN33 OUT33 line of GPTA IN34 OUT34 line of GPTA IN35 OUT35 line of GPTA ...

Page 83: ...A TXD1A EN00 RREADY0B SDI0 EN10 TVALID0B SDI1 ASC0 receiver input output A ASC0 transmitter output A ASC1 receiver input output A ASC1 transmitter output A P5 3 is latched with the rising edge of PORST if BYPASS 1 and stored in inverted state as bit OSC_CON MOSC MSC0 device select output 0 MLI0 receive channel ready output B MSC0 serial data input MSC1 device select output 0 MLI0 transmit channel ...

Page 84: ...XD1B TXDCAN1 TXD1B RXDCAN2 TXDCAN2 RXDCAN3 TXDCAN3 SSC1 master transmit output SSC1 slave receive input SSC1 master receive input SSC1 slave transmit output SSC1 clock input output SSC1 slave select input CAN node 0 receiver input ASC0 receiver input output B CAN node 0 transmitter output ASC0 transmitter output B CAN node 1 receiver input ASC1 receiver input output B CAN node 1 transmitter output...

Page 85: ...2 U4 U3 T3 T2 T1 U2 I I O O O I I O O REQ4 REQ5 AD0EMUX2 AD0EMUX0 AD0EMUX1 REQ6 REQ7 AD1EMUX0 AD1EMUX1 External trigger input 4 External trigger input 5 ADC0 external multiplexer control output 2 ADC0 external multiplexer control output 0 ADC0 external multiplexer control output 1 External trigger input 6 External trigger input 7 ADC1 external multiplexer control output 0 ADC1 external multiplexer...

Page 86: ...TREADY1A IN41 OUT41 TVALID1A IN42 OUT42 TDATA1 IN43 OUT43 RCLK1A IN44 OUT44 RREADY1A IN45 OUT45 RVALID1A IN46 OUT46 RDATA1A IN47 OUT47 MLI1 transmit channel clock output line of GPTA MLI1 transmit channel ready input A line of GPTA MLI1 transmit channel valid output A line of GPTA MLI1 transmit channel data output A line of GPTA MLI1 receive channel clock input A line of GPTA MLI1 receive channel ...

Page 87: ...OUT48 EN12 IN49 OUT49 EN11 IN50 OUT50 SOP1B IN51 OUT51 FCLP1B IN52 OUT52 EN03 IN53 OUT53 EN02 IN54 OUT54 EN01 IN55 OUT55 SOP0B FCLP0B line of GPTA MSC1 device select output 2 line of GPTA MSC1 device select output 1 line of GPTA MSC1 serial data output line of GPTA MSC1 clock output line of GPTA MSC0 device select output 3 line of GPTA MSC0 device select output 2 line of GPTA MSC0 device select ou...

Page 88: ...e modified from the reset configuration state Their actual state can be read via software P10_IN register During normal operation input HWCFG1 serves as emergency shut off control input for certain I O lines e g GPTA related outputs Dedicated Peripheral I Os SLSO0 AE14 O A2 VDDP SSC0 Slave Select Output Line 0 SLSO1 AC15 O SSC0 Slave Select Output Line 1 MTSR0 AF15 O I SSC0 Master Transmit Output ...

Page 89: ... positive A MSC0 differential driver clock output negative MSC0 differential driver serial data output positive A MSC0 differential driver serial data output negative MSC1 differential driver clock output positive A MSC1 differential driver clock output negative MSC1 differential driver serial data output positive A MSC1 differential driver serial data output negative Table 1 3 Pin Definitions and...

Page 90: ...ut Port provides 44 analog input lines for the A D converters ADC0 ADC1 and FADC Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11 Analog input 12 Analog input 13 Analog input 14 Analog input 15 Analog input 16 Analog input 17 Analog input 18 Analog input 19 Analog in...

Page 91: ...R12 TR13 TR14 TR15 U12 T12 U11 T11 U10 R12 R10 R11 M11 M10 L11 L10 K10 K11 L12 K12 O O O O O O O O O O O O O O O O O A3 VDDP OCDS Level 2 Debug Trace Lines2 located on center balls Trace output line 0 Trace output line 1 Trace output line 2 Trace output line 3 Trace output line 4 Trace output line 5 Trace output line 4 Trace output line 7 Trace output line 8 Trace output line 9 Trace output line 1...

Page 92: ... Input Reset Indication Output PORST B22 I 4 Power on Reset Input BYPASS A24 I PLL Bypass Select Input This input has to be held stable between two power on resets With BYPASS 1 the spike filters in the HDRST PORST and NMI inputs are switched off TEST MODE B23 I 6 Test Mode Select Input For normal operation of the TC1796 this pin should be connected to high level TSTRES G24 I 6 Test Reset Input Fo...

Page 93: ...F VDDAF AC9 FADC Analog Part Logic Power Supply 1 5 V VSSAF AD9 FADC Analog Part Log Ground for VDDAF VAREF0 AE5 ADC0 Reference Voltage VAGND0 AF5 ADC0 Reference Ground VAREF1 AD6 ADC1 Reference Voltage VAGND1 AC6 ADC1 Reference Ground VFAREF AF8 FADC Reference Voltage VFAGND AE8 FADC Reference Ground VDDOSC F26 Main Oscillator Power Supply 1 5 V VDDOSC3 E26 Main Oscillator Power Supply 3 3 V VSSO...

Page 94: ...C25 D9 D16 D24 E23 H4 P23 R4 V23 AB23 AC11 AC20 Core Power Supply 1 5 V VDDP A25 B24 C23 D7 D14 D22 K4 AC16 AD16 AE16 AF16 Port Power Supply 3 3 V also for OCDS VSS see Table 1 4 Ground 15 VSS lines are located on outer balls 47 VSS lines are located on center balls Table 1 3 Pin Definitions and Functions cont d Symbol Pins I O Pad Driver Class Power Supply Functions ...

Page 95: ...output driving level may occur at these pins 3 In case of a power fail condition one or more power supply voltages drop below the specified voltage range an undefined output driving level may occur at these pins even if they are input only pins 4 Input pad with input spike filter 5 Open drain pad with input spike filter 6 Input pad test function only without input spike filter Table 1 4 VSS Balls ...

Page 96: ... termination recommended A3 e g Traceoutputs serial I Os 75 MHz 50 pF Series termination recommended for f 25 MHz A4 e g Trace Clock 150 MHz 25 pF Series termination recommended B 2 375 3 6 V1 1 AC characteristics for EBU pins are valid for 2 5 V 5 and 3 3 V 5 LVTTL I O B1 e g Bus Interface 40 MHz 50 pF No B2 e g Bus Clock 75 MHz 35 pF Series termination recommended for f 25 MHz C 3 3 V LVDS 50 MH...

Page 97: ... GPIOs RD RD WR ADV BC 3 0 MR W WAIT BAA HOLD HLDA BREQ D 31 0 A 23 0 CS 3 0 CSCOMB Weak pull up device active NMI PORST Weak pull down device active BYPASS SLSO0 SLSO1 MTSR0 MRST0 SCLK0 SLSI0 TDO BFCLKI Weak pull up device active High impedance BFCLKO Weak pull up device active Push pull driver active HDRST Open drain device drives 0 strong pull down Weak pull up device active Open drain device a...

Page 98: ... 16 KB BROM 2 MB PFLASH 128 KB DFLASH Data Memory Unit DMU 16 KB SBRAM 64 KB SRAM Local Memory to FPI Bus Interface LFI Bridge PBCU DBCU Remote Peripheral Bus PLMB DLMB RPB Program Local Memory Bus Data Local Memory Bus System Peripheral Bus SPB MCB05585 Emulation Memory Interface To Emulation Memory Emulation device only LMI Floating Point Unit FPU TriCore CPU Data Memory Interface DMI 56 KB LDRA...

Page 99: ...rcular bit reverse long short base offset with pre and post update Instruction types Arithmetic address arithmetic comparison address comparison logical MAC shift coprocessor bit logical branch bit field load store packed data system General Purpose Register Set GPRS Sixteen 32 bit data registers Sixteen 32 bit address registers Three 32 bit status and program counter registers PSW PC PCXI Core De...

Page 100: ... Execution Unit a General Purpose Register File GPR a CPU Slave interface CPS and optional Floating Point Unit FPU Figure 2 2 CPU Block Diagram Execution Unit MCB05586 To Program Memory Interface PMI Integer Pipeline General Purpose Register File GPR Instruction Fetch Unit Core Register Access Address Registers Data Registers To Data Memory Interface DMI 64 Coprocessor Interface Floating Point Uni...

Page 101: ...nit directs the instruction to the appropriate pipeline The Instruction Protection Unit checks the validity of accesses to the PMI and also checks for instruction breakpoint conditions The PC Unit is responsible for updating the program counters Figure 2 3 Instruction Fetch Unit MCA05587 Issue Unit To Load Store Pipeline Injection PC Unit Align Prefetch Instruction Protection To Loop Pipeline To I...

Page 102: ...lti cycle operations such as load instructions The Loop Pipeline has two stages Decode and Write back All three pipelines operate in parallel permitting up to three instructions to be executed in one clock cycle Figure 2 4 Execution Unit MCA05588 Loop Exec To Register File EA Address ALU ALU Bit Processor MAC Load Store Decode IP Decode Integer Pipeline Loop Pipeline Load Store Pipeline Decode Exe...

Page 103: ... D15 The data flow for instructions issued to the Load Store Pipeline is steered through the Address Register File The data flow for instructions issued to from the Integer Pipeline and for data load store instructions issued to the Load Store Pipeline is steered through the Data Register File Figure 2 5 General Purpose Register File General Purpose Register File MCA05589 Data Register File Addres...

Page 104: ...rs are full the upper context save takes up to five cycles On the average an upper context save takes 2 7 cycles Shadow registers are automatically restored from memory when required 2 3 3 Reset System Several events can cause the TC1796 system to be reset The CPU does not differ in its behavior on reset The status register RST_SR allows the CPU to determine which event caused the reset Refer to C...

Page 105: ...aps have implementation specific properties For a complete description of the trap system refer to the TriCore 1 Architecture Manual Trap System UOPC Unimplemented Opcode TIN 2 The TC1796 UOPC trap is raised on optional MMU instructions coprocessor two and coprocessor three instructions OPD Invalid Operand TIN 3 The TC1796 CPU does not raise OPD traps DSE Data Access Synchronous Error TIN 2 The Da...

Page 106: ...responding pages Table 2 1 CPU and Processor Subsystem Registers Registers Purpose Description Address Map Core Special Function Registers CSFRs Program state information context and stack management interrupt and trap control system control Architecture Manual see Page 18 108 CPU Slave Interface Registers CPSs Software break control and software service request control see Page 18 104 Core Genera...

Page 107: ...08H SYSCON System Configuration Register F7E1 FE14H CPU_ID CPU Identification Register F7E1 FE18H BIV Interrupt Vector Table Pointer F7E1 FE20H BTV Trap Vector Table Pointer F7E1 FE24H ISP Interrupt Stack Pointer F7E1 FE28H ICR ICU Interrupt Control Register F7E1 FE2CH FCX Free Context List Head Pointer F7E1 FE38H LCX Free Context List Limit Pointer F7E1 FE3CH MCA05590_mod PC Program State Informa...

Page 108: ...s also an implementation specific CSFR Its Arbitration Cycle Control implementation specific details are described on Page 14 8 PSW Program Status Word F7E1FE04H Reset Value 0000 0B80H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C or FS V or FI SV or FV AV or FZ SAV or FU FX RM 0 rwh rwh rwh rwh rwh rwh rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PRS IO IS GW CDE CDC r rwh rwh rwh rwh rwh rwh...

Page 109: ... always set MMU_CON MMU Configuration Register F7E18000H Reset Value 0000 8000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NO MMU 0 TSZ SZB SZA V r r r rw rw rw Field Bits Type Description NOMMU 15 r No MMU Available 0B MMU is available 1B MMU is not available All other bits of MMU_CON are undefined 0 14 0 31 16 r Reserved Read as 0 should be written ...

Page 110: ...BSRC0 and CPU_SRC 3 0 are not bit addressable Table 2 3 CPS Registers Register Short Name Register Long Name Address CPS_ID CPS Module Identification Register F7E0 FF08H CPU_SBSRC01 1 CPU_SBSRC 3 1 are not implemented in the TC1796 Implementation specific details see Page 2 19 CPU Software Breakpoint Service Request Control Register 0 F7E0 FFBCH CPU_SRC3 CPU Service Request Control Register 3 F7E0...

Page 111: ... The non shaded areas in the CPU_SRCn register description defines the implementation specific bits bit fields CPU_SRCn n 0 3 CPU Service Request Control Register n F7E0FFFCH n 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description TOS 10 rw Type of Service ...

Page 112: ...E1 FF10H D5 Data Register 5 F7E1 FF14H D6 Data Register 6 F7E1 FF18H D7 Data Register 7 F7E1 FF1CH D8 Data Register 8 F7E1 FF20H D9 Data Register 9 F7E1 FF24H D10 Data Register 10 F7E1 FF28H MCA05592 A15 implicit address D15 implicit data Address General Purpose Registers AGPR Data General Purpose Registers DGPR A14 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E14 E12 E10 E8 E6 E4 E2 E0 64 Bi...

Page 113: ...A3 Address Register 3 F7E1 FF8CH A4 Address Register 4 F7E1 FF90H A5 Address Register 5 F7E1 FF94H A6 Address Register 6 F7E1 FF98H A7 Address Register 7 F7E1 FF9CH A8 Address Register 8 Global Address Register F7E1 FFA0H A9 Address Register 9 Global Address Register F7E1 FFA4H A10 Address Register 10 Stack Pointer F7E1 FFA8H A11 Address Register 11 Return Address F7E1 FFACH A12 Address Register 1...

Page 114: ... Register F7E1 FD00H EXEVT External Break Input Event Specifier Register F7E1 FD08H CREVT Core SFR Access Break Event Specifier Register F7E1 FD0CH SWEVT Software Break Event Specifier Register F7E1 FD10H TR0EVT Trigger Event 0 Specifier Register F7E1 FD20H TR1EVT Trigger Event 1 Specifier Register F7E1 FD24H DMS Debug Monitor Start Address Register F7E1 FD40H DCX Debug Context Save Area Pointer F...

Page 115: ... Software Breakpoint Service Request Control Register 0 The non shaded areas in the register description define the implementation specific bits bit fields TR0EVT Trigger Event 0 Specifier Register F7E1 FD20H Reset Value 0000 0000H TR1EVT Trigger Event 1 Specifier Register F7E1 FD20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 116: ...trol Register 0 F7E0 FFBCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description TOS 10 rw Type of Service Control 0B Service Provider CPU 1B Reserved 0 11 r Reserved Read as 0 should be written with 0 ...

Page 117: ...ction System Figure 2 10 Memory Protection Register Sets of the TC1796 Data Memory Protection Set 0 MCA05594 DPM0 31 24 DPR0_3U DPR0_3L Range 3 DPM0 23 16 DPR0_2U DPR0_2L Range 2 DPM0 15 8 DPR0_1U DPR0_1L Range 1 DPM0 7 0 DPR0_0U DPR0_0L Range 0 Code Memory Protection Set 0 CPM0 15 8 CPR0_1U CPR0_1L Range 1 CPM0 7 0 CPR0_0U CPR0_0L Range 0 Data Memory Protection Set 1 DPM1 31 24 DPR1_3U DPR1_3L Ra...

Page 118: ...pper Boundary F7E1 C014H DPR0_3L Data Segment Protection Register Set 0 Range 3 Lower Boundary F7E1 C018H DPR0_3U Data Segment Protection Register Set 0 Range 3 Upper Boundary F7E1 C01CH DPR1_0L Data Segment Protection Register Set 1 Range 0 Lower Boundary F7E1 C400H DPR1_0U Data Segment Protection Register Set 1 Range 0 Upper Boundary F7E1 C404H DPR1_1L Data Segment Protection Register Set 1 Rang...

Page 119: ...L Code Segment Protection Register Set 1 Range 0 Lower Boundary F7E1 D400H CPR1_0U Code Segment Protection Register Set 1 Range 0 Upper Boundary F7E1 D404H CPR1_1L Code Segment Protection Register Set 1 Range 1 Lower Boundary F7E1 D408H CPR1_1U Code Segment Protection Register Set 1 Range 1 Upper Boundary F7E1 D40CH DPM0 Data Protection Mode Register Set 0 F7E1 E000H DPM1 Data Protection Mode Regi...

Page 120: ...ptions define the implementation specific bits bit fields Therefore the uppermost 16 bits of CPMx are of type 0 r CPMx x 0 1 Code Protection Mode Register Set x Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XE 1 0 XS 1 0 BL 1 0 0 BU 1 XE 0 0 XS 0 0 BL 0 0 0 BU 0 rw rr rw rr rw rr rr rw rw rr rw r rw rr rr rw Field Bits Type Descrip...

Page 121: ...idity granularity 4 double words per cache line ICACHE can be globally invalidated to provide support for software cache coherency to be handled by the programmer ICACHE can be bypassed to provide a direct fetch from the CPU to on chip and off chip resources MCB05595 To From Program Local Memory Bus 128 Data Switch Data Alignment Interface Control PMI Control Registers 64 PLMB Interface Slave Mast...

Page 122: ...ord aligned functions only PMI SRAMs SPRAM ICACHE and Tag SRAM are parity protected 2 5 2 Parity Protection for PMI Memories In the TC1796 the PMI memory blocks SPRAM ICACHE and Tag RAM are equipped with a parity error detection logic that makes it possible to detect parity errors separately for SPRAM ICACHE or the ICACHE Tag RAM In case of a parity error a NMI is generated Note that before using ...

Page 123: ...ection Figure 2 12 PMI Registers Table 2 7 PMI Registers Register Short Name Register Long Name Address Description PMI_ID PMI Module Identification Register F87F FD08H Page 2 27 PMI_CON0 PMI Control Register 0 F87F FD10H Page 2 28 PMI_CON1 PMI Control Register 1 F87F FD14H Page 2 29 PMI_CON2 PMI Control Register 2 F87F FD18H Page 2 30 PMI_CON0 MCA05596_mod PMI_CON1 Control Registers PMI_CON2 Modu...

Page 124: ... 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module identification number for the PMI 0...

Page 125: ...20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CC BYP CC2 SPR r rw rw Field Bits Type Description CC2SPR 0 rw Code Cache Memory to SPR This bit is used for cache test mode purposes CC2PR must be written with 0 Setting it to 1 may lead to unpredictable program behavior CCBYP 1 rw Code Cache Bypass 0B Cache enabled 1B Cache bypassed disabled 0 31 2 r Reserved Returns 0 when read should b...

Page 126: ...9 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CC INV r rw Field Bits Type Description CCINV 0 rw Code Cache Invalidate 0B Normal code cache ICACHE operation 1B All cache lines are invalidated As long as CCINV is set all instruction fetch accesses generate a cache refill It is recommended that CCINV be kept set until ICACHE coherency is guaranteed 0 31 1 r Reserved Returns 0 when read shou...

Page 127: ...ption PCSZ 1 0 r Program Cache Size This bit field indicates the ICACHE size and TAGRAM configuration of the PMI The TC1796 has a fixed ICACHE size of 16 Kbyte Therefore PCSZ is always read as 11B 11B 16 Kbyte cache PMEMSZ 6 4 r Program Memory Size ICACHE SPRAM This bit field indicates the ICACHE plus SPRAM size of the PMI program memory The TC1796 has a fixed ICACHE and SPRAM size of 64 KB PMEMSZ...

Page 128: ...ing unaligned accesses 16 bit aligned with a minimum penalty of one cycle for unaligned accesses crossing 2 lines Data Local Memory Bus DLMB interface Allows access to the rest of the system 8 KB DPRAM CPU Interface DMI Control Registers MCB05597 To From Data Local Memory Bus 128 Data Switch Data Alignment Interface Control 64 DLMB Interface Slave Master 128 56 KB LDRAM BPI Interface To From Remot...

Page 129: ...ime For DPRAM operations such as semaphore handling it is necessary to ensure that at least two non DMI memory related instructions or another ST instruction are executed between the ST LDMST instruction and the following LD instruction to the semaphore location If the data written to a DPRAM location has to be available immediately on the RPB bus side of the DPRAM two non DMI memory related instr...

Page 130: ... logic that makes it possible to detect parity errors separately for LDRAM or DPRAM In case of a parity error a NMI is generated Note that before using parity protection for DMI memory blocks the first time after a power on reset operation before setting the corresponding parity error enable bit the LDRAM and DPRAM memories must be completely initialized by a user program that writes every memory ...

Page 131: ...ction or a write access to a read only register will lead to a bus error if the access was from the LMB Bus or to a trap flagged in DMI_STR DMI_ATR register in case of a CPU load store access Table 2 9 DMI Registers Register Short Name Register Long Name Address Description DMI_ID DMI Module Identification Register F87F FC08H Page 2 35 DMI_CON DMI Control Register F87F FC10H Page 2 36 DMI_STR DMI ...

Page 132: ...tion Register F87FFC08H Reset Value 0008 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines ...

Page 133: ... 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DMEMSZ 0 DCSZ r rh r rh Field Bits Type Description DCSZ 1 0 r Data Cache Size This bit field indicates the DMI data cache configuration In the TC1796 no data cache is available therefore DCSZ is always read as 00B 00B No cache available DMEMSZ 6 4 r Data Memory Size This bit field indicates the DMI data memory size In the TC1796 DMEMSZ is always rea...

Page 134: ...ompleteness DMI_CON1 DMI Control Register 1 F87FFC28H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DC2 SPR r rw Field Bits Type Description DC2SPR 0 rw Cache Test Mode Enable This bit must always be written with 0 Setting to 1 will have no effect in TC1796 0 31 1 r Reserved Returns 0 when read should be written with 0 ...

Page 135: ... user mode returns the contents of the register but does not clear its contents DMI_STR DMI Synchronous Trap Flag Register F87FFC18H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 LBE STF 0 LRE STF r rh r rh Field Bits Type Description LRESTF 0 rh Load Range Synchronous Error 0B No error 1B Load range synchronous error has occurre...

Page 136: ...ode returns the contents of the register but does not clear its contents DMI_ATR DMI Asynchronous Trap Flag Register F87FFC20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SBE ATF 0 SRE ATF 0 r rh r rh r Field Bits Type Description SREATF 1 rh Store Range Asynchronous Error 0B No error 1B Store range asynchronous error has occur...

Page 137: ...suing a different subsequent instruction Result Latency The number of clock cycles from the cycle when the instruction is issued to the cycle when the result value is available to be used as an operand to a subsequent instruction or written into a GPR Result latency is not meaningful for instructions that do not write a value into a GPR Address Latency The number of clocks cycles from the cycle wh...

Page 138: ...Repeat Rate Integer Pipeline Arithmetic Instructions ABS 1 1 MAX H 1 1 ABS B 1 1 MAX HU 1 1 ABS H 1 1 MAX U 1 1 ABSDIF 1 1 MIN 1 1 ABSDIF B 1 1 MIN B 1 1 ABSDIF H 1 1 MIN BU 1 1 ABSDIFS 1 1 MIN H 1 1 ABSDIFS H 1 1 MIN HU 1 1 ABSS 1 1 MIN U 1 1 ABSS H 1 1 RSUB 1 1 ADD 1 1 RSUBS 1 1 ADD B 1 1 RSUBS U 1 1 ADD H 1 1 SAT B 1 1 ADDC 1 1 SAT BU 1 1 ADDI 1 1 SAT H 1 1 ADDIH 1 1 SAT HU 1 1 ADDS 1 1 SEL 1 1...

Page 139: ...EQANY H 1 1 LT W 1 1 GE 1 1 LT WU 1 1 GE U 1 1 NE 1 1 LT 1 1 Count Instructions CLO 1 1 CLS H 1 1 CLO H 1 1 CLZ 1 1 CLS 1 1 CLZ H 1 1 Extract Instructions DEXTR 1 1 INS T 1 1 EXTR 1 1 INSN T 1 1 EXTR U 1 1 INSERT 1 1 IMASK 1 1 Logical Instructions AND 1 1 OR EQ 1 1 AND AND T 1 1 OR GE 1 1 AND ANDN T 1 1 OR GE U 1 1 AND EQ 1 1 OR LT 1 1 AND GE 1 1 OR LT U 1 1 Table 2 10 Simple Arithmetic Instructio...

Page 140: ...NOR 1 1 XOR GE U 1 1 NOR T 1 1 XOR LT 1 1 OR 1 1 XOR LT U 1 1 OR AND T 1 1 XOR NE 1 1 OR ANDN T 1 1 XOR T 1 1 Move Instructions CMOV 1 1 MOV U 1 1 CMOVN 1 1 MOVH 1 1 MOV 1 1 Shift Instructions SH 1 1 SH NE 1 1 SH AND T 1 1 SH NOR T 1 1 SH ANDN T 1 1 SH OR T 1 1 SH EQ 1 1 SH ORN T 1 1 SH GE 1 1 SH XNOR T 1 1 SH GE U 1 1 SH XOR T 1 1 SH H 1 1 SHA 1 1 SH LT 1 1 SHA H 1 1 SH LT U 1 1 SHAS 1 1 Table 2 ...

Page 141: ... DVINIT WU 1 1 DVADJ 1 1 DVSTEP S 4 4 DVINIT 1 1 DVSTEP U 4 4 DVINIT U 1 1 IXMAX 1 1 DVINIT B 1 1 IXMAX U 1 1 DVINIT H 1 1 IXMIN 1 1 DVINIT BS 1 1 IXMIN U 1 1 DVINIT BU 1 1 PACK 1 1 DVINIT HS 1 1 PARITY 1 1 DVINIT HU 1 1 UNPACK 1 1 Table 2 10 Simple Arithmetic Instruction Timing cont d Instruction Result Latency Repeat Rate Instruction Result Latency Repeat Rate ...

Page 142: ...n is single issued For MUL Q Instruction Table 2 11 Multiple Instruction Timing Instruction Result Latency Repeat Rate Instruction Result Latency Repeat Rate IP Arithmetic Instructions MUL 3 2 MUL H 2 1 MUL U 3 2 MUL Q 1 2 3 1 1 2 MULS 3 2 MULM H 2 1 MULS U 3 2 MULR H 2 1 MULR Q 2 1 Result Latency Repeat Rate 16 16 1 1 16 32 2 1 32 32 3 2 ...

Page 143: ...MSUB 3 2 MADD U 3 2 MSUB U 3 2 MADDS 3 2 MSUBS 3 2 MADDS U 3 2 MSUBS U 3 2 MADD H 2 1 MSUB H 2 1 MADD Q 2 3 1 2 MSUB Q 2 3 1 2 MADDM H 2 1 MSUBM H 2 1 MADDMS H 2 1 MSUBMS H 2 1 MADDR H 2 1 MSUBR H 2 1 MADDR Q 2 1 MSUBR Q 2 1 MADDRS H 2 1 MSUBRS H 2 1 MADDRS Q 2 1 MSUBRS Q 2 1 MADDS H 2 1 MSUBS H 2 1 MADDS Q 2 3 1 2 MSUBS Q 2 3 1 2 MADDSU H 2 1 MSUBAD H 2 1 MADDSUM H 2 1 MSUBADM H 2 1 MADDSUMS H 2 ...

Page 144: ...text operations no pending stores For All Control Flow Instructions Result Latency Repeat Rate 16 16 2 1 16 32 2 1 32 32 3 2 Table 2 13 Integer Pipeline Control Flow Instruction Timing Instruction Flow Latency Repeat Rate Instruction Flow Latency Repeat Rate Branch Instructions JEQ 1 2 3 1 2 3 JLTZ 1 2 3 1 2 3 JGE 1 2 3 1 2 3 JNE 1 2 3 1 2 3 JGE U 1 2 3 1 2 3 JNED 1 2 3 1 2 3 JGEZ 1 2 3 1 2 3 JNEI...

Page 145: ... AT 1 1 NEZ A 1 1 EQ A 1 1 SUB A 1 1 EQZ A 1 1 NOP 1 1 Trap and Interrupt Instructions DEBUG 1 TRAPSV1 1 Execution cycles when no TRAP is taken The execution timing in the case of raising these TRAPs is the same as other TRAPs such as SYSCALL 1 DISABLE 1 TRAPV3 1 ENABLE 1 RSTV 1 Move Instructions MFCR 1 1 MOV A 1 1 MTCR 1 MOV AA 1 1 MOVH A 1 1 MOV D 1 1 Sync Instructions DSYNC2 2 Repeat rate assum...

Page 146: ...2 JNE A 1 2 3 1 2 3 JL 2 2 JNZ A 1 2 3 1 2 3 JLA 2 2 JZ A 1 2 3 1 2 3 CSA Instructions CALL1 1 Latency of CSA related instructions varies according to preceding instruction and status of the shadow register file Average latency is 2 7 cycles 2 5 2 5 SYSCALL1 2 5 CALLA1 2 5 2 5 SVLCX1 4 9 CALLI1 2 5 2 5 RSLCX1 4 RET1 2 5 RFE1 2 5 BISR1 4 9 RFM2 2 Not strictly a CSA operation but retrieves from memo...

Page 147: ...truction is single issued The memory references is naturally aligned The memory accessed takes a single cycle to return a data item Timing is best case no cache misses no pending stores Flow Latency Repeat Rate Correctly predicted not taken 1 1 Correctly predicted taken 2 2 Wrongly predicted 3 2 Table 2 16 Load Instruction Timing Instruction Addr Latency Result Latency Repeat Rate Instruction Addr...

Page 148: ...aligned The memory accessed takes a single cycle to accept a data item Timing is best case no cache misses no pending stores Table 2 17 Cache and Store Instruction Timing Instruction Addr Latency Repeat Rate Instruction Address Latency Repeat Rate Cache Instructions CACHEA I 1 1 CACHEA WI1 1 Repeat rate assumes that no memory writeback operation occurs Otherwise the repeat rate will depend upon th...

Page 149: ...l Floating Point Unit is implemented Each instruction is single issued Table 2 18 Floating Point Instruction Timing Instruction Result Latency Repeat Rate Instruction Result Latency Repeat Rate Floating Point Instructions ADDF 2 2 MSUB F 3 3 CMP F 1 1 MUL F 2 2 DIV F 15 15 Q31TOF 2 2 FTOI 2 2 QSEED F 1 1 FTOQ31 2 2 SUBF 2 2 FTOU 2 2 UPDFL 1 ITOF 2 2 UTOF 2 2 MADD F 3 3 ...

Page 150: ...re the TC1796 can function so it contains special logic to handle power up and reset operations Its services are fundamental to the operation of the entire system so it contains special fail safe logic Figure 3 1 shows the structure of the TC1796 clock system The system clock fSYS is generated by the oscillator circuit and the PLL phase locked loop unit Each peripheral module operates with its mod...

Page 151: ... 1 MSC0 MSC1 fMSC0 fCLC0 fMSC1 fCLC1 MLI0 MLI1 fMLI0 fMLI1 ADC0 fADC fCLC ADC1 FADC fFADC fCLC SCU_ SCLKFDR fSYSCLK P1 12 SYSCLK DMA DMA_CLC fDMA PCP PCP_CLC fPCP STM STM_CLC fSTM CPU Clock fCPU SCU RBCU SBCU WDT ICU fEBU The module clock for these modules is switched off after reset module is disabled For these modules fMOD fSYS Its module clock can only be switched on or off no clock divider ASC...

Page 152: ...ration Unit CGU in the TC1796 shown in Figure 3 2 consists basically of an oscillator circuit and a Phase Locked Loop PLL The operation of the CGU is controlled by two registers OSC_CON and PLL_CLC which are located in the System Control Unit SCU Figure 3 2 CGU Detailed Block Diagram MCB05600 Phase Detect VCO N Divider PLL KDIV BYPASS P5 3 TXD1A Main Osc Circuit XTAL1 XTAL2 Osc Run Detect fVCO fN ...

Page 153: ... vendor The CX1 and CX2 values shown in Figure 3 3 can be used as starting points for the negative resistance evaluation and for non productive systems The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative resistance method Oscillation measurement with the final target system i...

Page 154: ...derived from an external clock signal which is applied to XTAL1 The MOSC bit can be set in two ways By software Writing a 1 to bit MOSC of register OSC_CON By hardware at a power on reset operation If pin BYPASS 1 the state of the pin P5 3 TXD1A is latched with the rising edge of PORST and determines the inverted state of the MOSC bit If P5 3 0 at the rising edge of PORST MOSC is set and the oscil...

Page 155: ...minal count value The 5 bit Counter B is running at fN the divided N Divider VCO clock frequency Always at the terminal count of Counter B the state of Counter A is latched in a flip flop bit OSCR is updated and both counters a reset This means if Counter A does not reaches its terminal count value 8 fOSC clock periods within a counter period of Counter B 32 fN clock periods the oscillator is desi...

Page 156: ...inning force the crystal oscillation When a stable oscillation has been reached after oscillation start up the gain of the oscillator can be reduced This reduces the oscillator s power consumption which is especially important in the power saving modes This gain reduction is selected by OSC_CON OGC 1 Note Oscillator measurement margin or negative resistance and XTAL1 input amplitude for the oscill...

Page 157: ...ain oscillator 0B The oscillator is running The oscillator signal of the main oscillator or an external clock input signal is used as fOSC 1B The oscillator circuitry is bypassed An external clock input signal at XTAL1 must be provided and is used as fOSC It is 1 if the BYPASS pin is high and TXD1A is zero Its state is latched with the rising edge of PORST OSCR 1 rh Oscillator Run Status Bit This ...

Page 158: ...ontrol This bit determines the main oscillator gain 0B High gain is selected default after reset 1B Low gain is selected 0 3 31 5 r Reserved Read as 0 should be written with 0 Table 3 1 Reset Values of Register OSC_CON Condition Function Reset Values BYPASS TXD1A 0 X The system is driven by the PLL clock which is derived from the oscillator clock 0000 0000H 1 0 The system is driven directly by the...

Page 159: ...y A PLL lock detection unit monitors and signals this condition The phase detection logic continues to monitor the two clock signals and adjusts the VCO clock if required The CGU output clocks fCPU and fSYS are derived from the VCO clock by the K Divider 3 2 2 1 Clock Source Control The CPU clock fCPU and the system clock fSYS are generated from fOSC in one of four hardware software selectable mod...

Page 160: ...he system clock fSYS can be equal to fCPU PLL_CLC SYSFS 1 or equal to fCPU 2 PLL_CLC SYSFS 0 3 2 PLL Base Mode In PLL Base Mode the PLL is running at its VCO base frequency and fCPU and fSYS are derived from fVCO only by the K Divider In this mode PLL_CLC VCOBYP must be 0 and pin BYPASS must have been latched as 0 at the end of the last power on reset operation In this mode the system clock fSYS c...

Page 161: ... Table 3 2 shows the P factor values of the P Divider which are selected by programming the PLL_CLC PDIV bit field It also lists the resulting fP frequency for some dedicated values of fOSC but the complete range of 4 to 40 MHz can be applied and used for fOSC Note that the P Divider factor is always PLL_CLC PDIV 1 Table 3 2 P Divider Selections PLL_CLC PDIV P Divider P PDIV 1 Resulting fP Frequen...

Page 162: ...s of the N Divider which are selected by programming the PLL_CLC NDIV bit field It also lists the resulting N divider output clock fN depending on N and dedicated VCO frequencies Note that the N Divider factor is always PLL_CLC NDIV 1 For proper operation of the PLL only N Divider values of 20 to 100 are allowed Table 3 3 N Divider Selections PLL_CLC NDIV1 1 These columns include decimal values N ...

Page 163: ...der Selections PLL_CLC KDIV K Divider K KDIV 1 Resulting fCPU Frequency in MHz for fCPU fVCO 400 MHz fVCO 500 MHz fVCO 600 MHz fVCO 700 MHz Duty Cycle Max Value MHz 0 1 400 500 600 700 1 1 These KDIV selections are not allowed in PLL Mode of the TC1796 1 1 2 200 250 300 350 2 3 133 33 166 67 200 233 33 33 33 1002 2 This is a restriction in fCPUmax for odd K divider factors 3 4 100 125 150 175 50 1...

Page 164: ...ncy when no PLL input clock fP is connected Table 3 5 VCO Operating Range Selection Bit PLL_CLC VCOSEL fVCOmin fVCOmax fVCObase 1 1 fVCObase is the free running operation frequency of the PLL when no input clock is available fOSCmin 2 2 This is the minimum oscillator frequency to allow oscillator run detection to work properly Unit 00B 400 500 approx 140 320 1 5 MHz 01B 500 600 approx 150 400 1 75...

Page 165: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDIV 0 KDIV VCOSEL VCO BYP 0 SYS FS RES LD LO CK rw r rw rw rw r rw rwh rh Field Bits Type Description LOCK 0 rh PLL Lock Status Flag 0B PLL is not locked default after reset 1B PLL is locked RESLD 1 rwh Restart Lock Detection Writing a 1 to this bit will clear the LOCK flag and restart the PLL lock detection After written with a 1 this bit is reset automatic...

Page 166: ...alues between 19D and 99D means N Divider values of 20D and 100D are allowed OSCDISC 24 rwh Oscillator Disconnect This bit is used to disconnect the divided fOSC clock from the PLL in order to avoid unstable operation due to noise or sporadic clock pulses coming from the oscillator circuit while the PLL is still trying to lock to invalid clock pulses 0B Oscillator clock fOSC is connected to the PL...

Page 167: ...ntil the PLL becomes locked After changing PDIV or NDIV wait for the PLL lock condition This procedure is typically used for increasing the VCO clock step by step 3 2 2 5 Setting up the PLL after Reset After reset the system clock will be running at the VCO base frequency fVCObase divided by factor K Now the following actions must be executed next 1 Wait until the oscillator is running OSC_CON OSC...

Page 168: ...ounter difference less than or equal 2 the counters are further incremented up to a maximum counter value of 232 clock pulses After 232 clock pulses with no unlock condition of the counter values the two counters are reset slow unlock check The PLL may become unlocked caused by a break of the crystal or the external clock line In such a case an NMI trap is generated by setting the NMISR PLLNMI fla...

Page 169: ...L_CLC VCOBYP 1 Re connect the oscillator to the PLL PLL_CLC OSCDISC 0 Set the restart lock detection bit PLL_CLC RESLD 1 Wait until the PLL becomes locked PLL_CLC LOCK 1 When the PLL_CLC LOCK is set again the VCO Bypass Mode can be deselected PLL_CLC VCOBYP 0 and normal PLL operation is resumed The note in Section 3 2 2 4 is also valid for this procedure ...

Page 170: ...t is provided by another clock source with faster startup characteristics the PORST low level can be released earlier If the BYPASS pin is at low level during power on reset PLL Mode is selected see Page 3 11 and the procedure to start up the PLL is as described in the next paragraph With PORST 0 the oscillator is disconnected from the PLL The PLL starts running at the VCO base frequency fVCObase ...

Page 171: ...ic gating which requires software intervention is used to enable or disable clock delivery to individual high level functional units or to disable clock delivery globally at the clock s source When the clock to individual functional units is gated off they are said to be in Sleep Mode The TC1796 implements three levels of clock gating 1 Gated dynamically at the register The clock is shut off to a ...

Page 172: ...C is typically used by a peripheral module for clocking its FPI Bus interface and registers while the module clock fMOD is dedicated for kernel operation or timer clocks The output signal RST_EXT_DIV makes it possible to enable disable external divider stages which are connected to the module clock fMOD The fractional divider divides the fCLC either by the factor 1 n or by a fraction of n 1024 for...

Page 173: ...iated with the CLC register Peripheral clock static on off control Module clock behavior in Sleep Mode Operation during Debug Suspend Mode Fast Shut off Mode control MOD_CLC Clock Control Register 00H Reset Value Module specific 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMC 0 FS OE SB WE E DIS SP EN DIS S DIS R rw r rw w rw rw rh rw Field Bits Type D...

Page 174: ...ines whether SPEN and FSOE are write protected 0B Bits SPEN and FSOE are write protected 1B Bits SPEN and FSOE are overwritten by respective value of SPEN or FSOE This bit is a write only bit The value written to this bit is not stored Reading this bit returns always 0 FSOE 5 rw Fast Switch Off Enable Used for fast clock switch off in OCDS suspend mode 0B Clock switch off in OCDS suspend mode via ...

Page 175: ...ich the module becomes active any write access to corresponding module registers when DISS is still set will generate a bus error Therefore when enabling a disabled module application software should check after activation of the module once read back of the CLC register to find out whether DISS is already reset before a module register including the CLC register will be written to Note A read acc...

Page 176: ...ftware can not accidentally alter the value of the SPEN bit that has been set by a debugger Note The operation of the Watchdog Timer is always automatically stopped in debug suspend mode Entering Disabled Mode Software can request that a peripheral unit be put into Disabled Mode by setting DISR A module will also be put into Disabled Mode if the sleep mode is requested and the module is configured...

Page 177: ...example the analog to digital converter might allow the converter to finish a running analog conversion before it can be suspended Otherwise the conversion might be corrupted and a wrong value could be produced when Debug Suspend Mode is exited and the unit is enabled again This would affect further emulation and debugging of the application s program On the other hand if a problem is observed to ...

Page 178: ...LC register may result in a longer read cycle access time on the FPI Buses for peripheral units with destructive read access e g the ASC 3 3 3 Fractional Divider Operation This section describes the module clock generation using the Fractional Divider 3 3 3 1 Overview The fractional divider makes it possible to generate a module clock from an input clock using a programmable divider The fractional...

Page 179: ...r overflow Fractional Divider Mode Adder that adds a STEP value to the RESULT value and generates an output clock pulse on counter overflow The fractional divider is further controlled by several input and output signals The purpose of these signals is described in Table 3 7 MCB05604 fIN fOUT RESULT 10 bit STEP 10 bit Mux Adder Mux 1 Debug Suspend Request Debug Suspend Acknowledge External Clock E...

Page 180: ...nel This disable acknowledge signal is activated by the module kernel as a response to a suspend request that has been generated by the fractional divider via the Kernel Disable Request signal External Clock Enable This input can be used to synchronize the fractional divider clock generation to external events Module Disable Request This input is connected to the disable request output from the CL...

Page 181: ...nsition from 3FFH to 000H FDR RESULT represents the counter value and FDR STEP determines the reload value The output frequencies in normal divider mode are defined according to the following formulas 3 5 In order to get fOUT fIN STEP must be programmed with 3FFH Figure 3 7 shows the operation of the normal divider mode with a reload value of FDR STEP 3FDH The clock signal fOUT is the AND combinat...

Page 182: ... the addition FDR RESULT FDR STEP If the addition leads to an overflow over 3FFH a pulse is generated at fOUT Note that in fractional divider mode the clock fOUT can have a maximum period jitter of one fIN clock period The output frequencies in fractional divider mode are defined according to the following formulas with n 0 1023 3 6 Figure 3 8 shows the operation of the fractional divider mode wit...

Page 183: ...ate suspend mode The state of the Debug Suspend Request and Debug Suspend Acknowledge signal is latched in two status flags of register FDR SUSREQ and SUSACK Debug Suspend Request and Debug Suspend Acknowledge or bit SM must remain set both to maintain the suspend mode Figure 3 9 Suspend Mode Configuration The Kernel Disable Request signal becomes always active when the Module Disable Request sign...

Page 184: ...ESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value In normal divider mode STEP contains the reload value for RESULT In fractional divider mode this bit field determines the 10 bit value that is added to RESULT with each input clock cycle SM 11 rw Suspend Mode SM selects between granted or immediate suspend ...

Page 185: ...r Mode This bit fields determines the functionality of the fractional divider block 00B Fractional divider is switched off no output clock is generated The Reset External Divider signal is 1 RESULT is not updated default after reset 01B Normal divider mode selected 10B Fractional divider mode selected 11B Fractional divider is switched off no output clock is generated RESULT is not updated RESULT ...

Page 186: ...e by a high level of the External Clock Enable input signal 1B Bit DISCLK is cleared by hardware while the External Clock Enable input signal is at high level DISCLK 31 rwh Disable Clock 0B Clock generation of fOUT is enabled according to the setting of bit field DM 1B Fractional divider is stopped Signal fOUT becomes inactive No change except when writing bit field DM In case of a conflict betwee...

Page 187: ...l Divider Function Table Mode SC DM Reset Ext Divider Signal Result fOUT Operation of Fractional Divider Normal Mode 00B 1 unchanged inactive switched off 01B 0 continuously updated1 active normal divider mode 10B fractional divider mode 11B unchanged inactive switched off Suspend Mode 00B 00B 1 unchanged inactive switched off 01B 0 continuously updated1 active normal divider mode 10B fractional d...

Page 188: ...Generation Implementation of the TC1796 Peripheral Modules Module DISR Bit 0 DISS Bit 1 SPEN Bit 2 EDIS Bit 3 SBWE Bit 4 FSOE Bit 5 RMC Fract Divider 1 1 Further info on FDR implementations see Table 3 10 Name State after Reset ADC0 ADC1 off FADC off ASC0 and ASC1 off 8 bit SSC0 off SSC1 off MultiCAN off DMA on EBU on GPTA0 GPTA1 LTCA2 off MLI0 off not implemented MLI is connected to DMA_CLC MLI1 ...

Page 189: ...endently from the suspend acknowledge answer from the module ENHW2 2 This column shows whether the External Clock Enable input of a fractional divider is controlled by on chip hardware source module see comment or not Reset Ext Divider3 3 This column shows whether the Reset External Divider output of the fractional divider is used purpose see comment or not CAN_FDR Acknowledge depends on module st...

Page 190: ... in normal divider mode is defined according to the following formula with n 1024 STEP 3 7 In fractional divider mode fOUT is derived from the input clock fIN by division of a fraction of n 1024 for any value of n from 0 to 1023 In general the fractional divider mode makes it possible to program the average output clock frequency with a higher accuracy than in normal divider mode Note that in frac...

Page 191: ... 11 rw Suspend Mode SM selects granted or immediate suspend mode DM 15 14 rw Divider Mode DM selects normal or fractional divider mode SC 13 12 rw Suspend Control SC determines the behavior of the fractional divider in suspend mode RESULT 25 16 rh Result Value Bit field for the addition result SUSACK 28 rh Suspend Mode Acknowledge Indicates state of SPNDACK signal SUSREQ 29 rh Suspend Mode Request...

Page 192: ... 3 43 V2 0 2007 07 Clock V2 0 Note This is only a short summary of the fractional divider behavior The details on the fractional divider register functionality are described on Page 3 29 0 10 27 26 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 193: ...o the CPU this allows the CPU to gather debug information and then resets the device after a predefined time out period After a reset has been executed the Reset Status RST_SR register provides information on the type of the last reset and the selected boot configuration The external reset pin HDRST has a double function It serves as a reset input from the external world to reset the device and it...

Page 194: ... TagRAM memories in the PMI In the emulation device the EEC is initialized upon thecompletion of a power on reset Therefore activation of the HDRST signal earlier than the maximum Power on Reset Boot Time must be prevented Please refer to the maximum Power on Reset Boot Time defined in the Power Pad and Reset Timing section of the TC1796 Data Sheet ...

Page 195: ...pled with the HDRST inactive low to high transition Register RST_SR is a read only register RST_SR Reset Status Register F0000014H Reset Values see Table 4 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 WDT RST SFT RST HD RST PWO RST 0 TMP LS HW BRK IN 0 HWCFG r rh rh rh rh r rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RS EXT 0 RS STM r rh r rh Field Bits Type Description RSSTM 0 rh Sy...

Page 196: ...reset 1B The last reset was a power on reset HDRST 28 rh Hardware Reset Status Flag 0B The last reset was not a hardware reset 1B The last reset was a hardware reset SFTRST 29 rh Software Reset Status Flag 0B The last reset was not a software reset 1B The last reset was a software reset WDTRST 30 rh Watchdog Reset Status Flag 0B The last reset was not a watchdog reset 1B The last reset was a watch...

Page 197: ...quested software reset RST_REQ Reset Request Register F0000010H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SW BO OT 0 SW BRK IN 0 SWCFG r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RR EXT 0 RR STM r rw r rw Field Bits Type Description RRSTM 0 rw Reset Request for the System Timer 0B Do not reset the System Timer 1B Reset the System Timer RREXT 2 rw Reset Req...

Page 198: ... SWCFG bit field as well as for SWBRKIN and SWBOOT bits SWBOOT 24 rw Software Boot Configuration Selection 0B The previously latched hardware configuration stored in RST_SR HWCFG is used as boot selection 1B The software configuration as programmed in bit field SWCFG is used as boot selection 0 1 20 15 3 23 22 31 25 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 199: ...lds in the Reset Status Register RST_SR are set to inform the user about this complete reset of the device The power on reset indication flag is set while all other reset cause indication flags are cleared Fields in this register which are set include the power on reset indication flag PWORST as well as the reset status flags for the System Timer RSSTM and the reset output pin state RSEXT The time...

Page 200: ...ude exclude optionally the system timer reset and the external reset output HDRST generation from becoming active To exclude one of these two system functions from software reset the corresponding bits in RST_REQ RRSTM or RREXT must be set to 0 Additionally a software reset can be executed with a programmable software boot configuration value bit field RST_REQ SWCFG instead of the last hardware bo...

Page 201: ...evented by initialization software will eventually time out Ordinarily initialization software will configure the Watchdog Timer and commence servicing it on a regular basis to indicate that it is functioning properly Should the system be malfunctioning such that initialization and service are not performed in a timely fashion the Watchdog Timer will time out causing a Watchdog Timer reset If the ...

Page 202: ...s The reset circuitry then puts the TC1796 in Reset Lock This state can only be deactivated again through a power on reset 4 2 5 Debug System Reset The debug system is not automatically reset by the regular resets except for the power on reset It is not effected by a software resets and by a Watchdog Timer reset A hardware reset becomes only effective if at the same time the OCDS reset is active a...

Page 203: ...cted EBU EBU Pins Depending on Reset Configuration Port Pins Tri stated weak pull up active5 NMI Pin Not affected Disabled Disabled Disabled Reset Out Pin HDRST Optional OCDS L1 Debug System Only if JTAG reset is also active6 1 For two of the SCU registers PLL_CLC RST_SR the reset value depends on the reset source 2 Affected or not affected depends on bit RST_REQ RRSTM 3 If only the PCP accesses i...

Page 204: ...n Table 4 3 shows the boot options selections which are available in the TC1796 The source for BRKIN and HWCFG 3 0 can be either the corresponding bits HWBRKIN and HWCFG 3 0 from register RST_SR sampled from configuration pins or the software configuration bits SWBRKIN and SWCFG 3 0 from register RST_REQ The target boot address program counter start address DFFF FFFCH is located at the end of the ...

Page 205: ... EBU as participant using CS0 enter a serial bootstrap loader mode1 if CRC checks fails automatic EBU configuration2 as defined in ABM header or D400 0000H 1000B Start from emulation memory if emulation device TC1796ED is available in case of TC1796 execute stop loop if TC1796ED AFF0 0000H 1111B Enter bootstrap loader mode 3 Serial ASC0 boot via CAN pins D400 0000H others Reserved execute stop loo...

Page 206: ...0H start address of the PMI scratchpad RAM and begins executing the program code that has been loaded Further details about the BSL are described in Section 4 4 External Boot In external boot modes code execution is started in external memory via the EBU at a fixed address A100 0000H In Alternate Boot Modes the code start address is defined by one of the two ABM headers see Page 4 30 In order to a...

Page 207: ...i state chip Starting code execution from external emulator memory Execution of an endless stop loop Tri state Chip If HWCFG 3 0 0000B all pins of the TC1796 are put into tri state mode In this mode all pins are deactivated including the oscillator and internal circuitry is held in a low power mode This mode allows e g board level test equipment or emulator probes to actively drive lines which are...

Page 208: ...s DFFF FFFCH At this location within the BROM a jump to start address AFFF F180H is programmed to guarantee continuation of start program execution after reset Because the reset start address is fixed the Boot ROM is mapped to the upper part of the internal BROM at locations E000 FFFFH and the TestROM is mapped to the lower part of internal BROM C000 DFFFH 4 3 2 Program Structure The different sec...

Page 209: ...een loaded Further details about the BSL are described in Section 4 4 Alternate Boot Modes The alternate boot modes will only branch to an user program in PFLASH or external code memory if a CRC checksum test shows no error If the CRC check fails a bootstrap loader mode is entered instead of user program execution Tuning Protection Tuning protection is supported to protect user software in externa...

Page 210: ...ecute bootstrap loader mode 3 ASC0 1111B yes no Boot from emulation memory 1000B yes no 0010B yes no 01X0B yes no 0011B yes no 01X1B yes no Execute stop loop Jump to AFF00000H Jump to D4000000H Jump to A0000000H Alternate boot from internal PFLASH after CRC check Check CFG data Alternate boot from external memory after CRC check CRC ok no Boot from ext memory X 0 EBU as master X 1 EBU as participa...

Page 211: ...000FH updated with unique Chip ID D000 0010H D000 0107H updated with Boot ROM data SCU_STAT 15 13 are set to 001B FLASH_MARP TRAPDIS and FLASH_MARD TRAPDIS are cleared FLASH_FCON WSWLHIT is set to 110B Branch to test modes Only applicable for test purposes Execute debug boot options The following registers have been changed CPR0_0L CPM0 and TR0EVT Exit of Bootstrap loader mode 1 ASC0 P5_IOCR0 has ...

Page 212: ...tion of Table 4 5 is detected the bootstrap loader is started and the selected bootstrap loader mode is entered The bootstrap loader can also be started by a software reset For this purpose bit RST_REQ SWBRKIN and bit field RST_REQ SWCFG must be loaded with the corresponding BRKIN HWCFG 3 0 code and bit RST_REQ SWBOOT must be set see also RST_REQ register description at Page 4 5 When a boot option...

Page 213: ...n byte is built up by one low level start bit eight low level data bits and 1 stop bit a low pulse with a width of nine serial bit cells The bootstrap loader software measures the width of the initialization byte calculates the baud rate and writes the corresponding ASC0 registers with the values that select the detected baud rate After the baud rate calculation and initialization receive pin rema...

Page 214: ...op waits until it has received four bytes The outer loop writes one word four bytes to the scratchpad RAM SPRAM program memory of the PMI These loops are running until 128 bytes have been received After the reception of the 128 bytes the bootstrap loader software is finished and a jump to address D400 0000H is executed This address is the 32 bit word location in the SPRAM at which the first four b...

Page 215: ...k WDT Initialize ASC0 port pins Calculate baud rate search for best values for FDV and BG registers Initialize ASC0 registers Data byte received no yes Store data byte in buffer Decrement byte counter Byte counter 0 no yes Write word to SPRAM Increment data pointer Byte counter 4 Decrement word counter Word counter 0 no yes Execute jump to address D4000000H Enable receiver Initialize data pointer ...

Page 216: ...ternal host is based on the following three CAN standard frames Initialization frame sent by the external host to the TC1796 Acknowledge frame sent by the TC1796 to the external host Data frame s sent by the external host to the TC1796 The initialization frame is used in the TC1796 for baud rate detection After a successful baud rate detection is reported to the external host by the acknowledge fr...

Page 217: ...owledge phase the bootstrap loader waits until it receives the next correctly recognized initialization frame from the external host and acknowledges this frame by generating a dominant bit in its ACK slot Afterwards the bootstrap loader transmits an acknowledge frame back to the external host indicating that it is now ready to receive Acknowledge Frame Identifier Acknowledge message identifier AC...

Page 218: ... in SPRAM at D400 0000H Consecutive data bytes are stored at incrementing addresses Both communication partners evaluate the data message count DMSGC until the requested number of CAN data frames has been transmitted After the reception of the last CAN data frame the bootstrap loader software is finished and executes a jump to address D400 0000H This address is the first 32 bit word location in th...

Page 219: ...t Frame and checking ACK slot Sampling RXDCAN0 for 5555H pattern Setting dominant bit in the ACK slot Programming of CAN registers for detected baud rate yes Transmitting CAN message with eight data bytes Last message received no Execute jump to address D4000000H no End of data transfers Waiting for reception of the next CAN message Transferring received data bytes to SPRAM Last message transmitte...

Page 220: ...of the memory range which has to be checked with CRC checksum The checksums for the checked memory range and for the ABM header itself Basically the CRC check procedure of the Boot ROM program consists of three steps Step 1 The first CRC check is executed with the parameters of the primary ABM header If the first CRC check passes the user program is started at the address as defined in the first w...

Page 221: ...ers have a size of 32 bytes 8 words and are located at fix addresses in the internal or external Flash as shown in Table 4 8 Alternatively cached addressing segment 8 or non cached addressing segment 10 can be used 1 This value is default after reset without connecting P0 2 0 to a low or high level Port 0 pins are inputs after reset with a pull up device connected Table 4 8 ABM Header Locations In...

Page 222: ...e also Table 4 8 Value Function XXXX XXE0H 32 bit start address Program code start address XXXX XXE4H DEAD BEEFH Identifier string XXXX XXE8H 32 bit address checksum start 32 bit aligned start address of memory range to be checked XXXX XXECH 32 bit address checksum end 32 bit aligned end address last word address of memory range to be checked XXXX XXF0H 32 bit CRC value CRCRANGE Expected 32 bit CR...

Page 223: ...this chapter are Power Management see Page 5 2 Configuration Input Sampling see Page 5 8 External Request Unit see Page 5 9 Special System Interrupts see Page 5 35 On chip SRAM Parity Control see Page 5 37 Pad Driver Temperature Compensation Control see Page 5 41 Die Temperature Sensor see Page 5 48 GPTA1 Input IN1 Control see Page 5 49 Pad Test Mode Control see Page 5 50 Emergency Stop Output Con...

Page 224: ... Stopping the CPU clock Stopping the clocks of other system components individually Clock speed reduction of some peripheral components individually Table 5 1 Power Management Mode Summary Mode Description Run The system is fully operational All clocks and peripherals are enabled as determined by software Idle The CPU clock is disabled waiting for a condition to return it to Run Mode Idle Mode can...

Page 225: ...Mode and Sleep Mode may be entered and exited frequently during the run time of an application For example system software will typically cause the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its tasks In Sleep Mode and Idle Mode wake up is performed automatically when any enabled interrupt signal is detected or if the Watchdog Timer signals the CPU an NMI tr...

Page 226: ...un Mode 01B Request Idle Mode 10B Request Sleep Mode 11B Reserved do not use this combination In Idle Mode or Sleep Mode these bits are cleared in response to an enabled interrupt or when bit 15 of the Watchdog Timer count register the WDT_SR TIM 15 bit changes from 0 to 1 PMST 10 8 rh Power Management State Machine Status 000B Waiting for PLL lock condition 001B Normal Run Mode 010B Idle Mode req...

Page 227: ...a the local memory buses DLMB and PLMB cause these units to awaken automatically to handle the transactions When memory transactions are complete the DMI and PMI return to Idle Mode again The system will return to Run Mode through the occurrence of any of the following conditions An interrupt signal is received from an enabled interrupt source A NMI request is received either from an external sour...

Page 228: ...signal will cause this unit to enter Sleep Mode Two actions then occur The unit s bus interface finishes whatever transaction was in progress when the signal was received The unit s functions are suspended The TriCore architecture qualifies the actions in step 2 as follows Depending on the module s clock control register Fast Shut Off Enable bit FSOE the module s clocks are either immediately stop...

Page 229: ... Idle Idle DMI PMI Active Idle but accessible Idle but accessible DMU PMU Active Accessible Accessible Flash Module Active Active Powered down Watchdog Timer Functioning as programmed Functioning as programmed Functioning as programmed FPI Bus Peripherals Functioning as programmed Functioning as programmed Peripherals with suspend enabled are shut down Debug Units Functioning Functioning Functioni...

Page 230: ... HDRST or PORST Table 5 3 Configuration Input Sampling Configuration Type Reset Signal Pins Remark Software Configuration HDRST P0 15 0 The states of these pins are latched in register SCU_SCLIR see also Section 10 3 3 2 on Page 10 24 Hardware Configuration HDRST P10 3 0 HWFCG 3 0 The states of these pins are used for selection of the Boot option see Table 4 3 on Page 4 12 Its state is latched in ...

Page 231: ...s or to reroute trigger events from one block to another In the TC1796 a flexible External Request Unit ERU makes it possible to generate trigger events that are able to generate interrupts trigger a DMA transfers or start analog to digital conversions Features Edge detection of an input signal rising falling or both edges Event generation with combined conditions of input signals Pattern detectio...

Page 232: ...one part located in the ERS and one part located in the ETL Two of the four input channels are always controlled by one External Input Channel Register EICRn n 0 1 n 0 applies to input channel 0 and 1 n 1 applies to input channel 2 and 3 In the following description the index number x indicates the input channel number Figure 5 2 External Request Unit Input Channel An input channel of the ERS cont...

Page 233: ...ected by the edge detection logic at least once In this mode bit EIFRn INTFx can be cleared only by software EIFRn LDENx 1 In this mode flag EIFRn INTFx becomes cleared by hardware if an edge is detected at the INx signal that has not been selected This means EIFRn INTFx is cleared by hardware at a INx rising edge when EICRn FENx 1 and EIFRn INTFx is cleared by hardware at a INx falling edge when ...

Page 234: ...onversions The output PDOUTy is active as long as the programmed condition of input signals INTFx is met Each INTFx output signal from input channel x is connected to each output channel y Bit IPENy 3 0 determine whether flag INTFx of input channel x takes part in the pattern detection of output channel y The output signal PDOUTy is an AND combination of all INTFx inputs that are enabled by IPENyx...

Page 235: ...e gating functionality GOUTy programmed level of PDOUTy and the trigger functionality of TOUTy It can also be used to trigger module actions such as DMA requests or GPTA actions IOUTy outputs pulses Output Channel Control Logic A very useful additional feature is the possibility to gate the incoming interrupt requests with the indication flags INTFx x 0 3 coming from the Event Trigger Logic of the...

Page 236: ...ure 5 5 additional trigger lines ROUT are generated by the GPTA0 module These lines detect rising edges at three dedicated GPTA0 outputs and can be used to trigger ADC actions for example The GPTA0 outputs are connected to an edge detection logic to obtain a trigger pulse each time a rising edge is detected P7 0 REQ4 MCA05616 FCLP IN00 IN01 IN02 IN03 IN10 IN11 IN12 IN13 IN20 IN21 IN22 IN23 IN30 IN...

Page 237: ...TOUT 0 1 2 3 PDOUT ASGT QGT TGT 1 1 1 Gating Inputs TGADCx ETRSEL 0 TGADCx SW0TRSEL 0 TGADCx TTRSEL 0 TGADCx QTRSEL 0 1 2 ROUT 0 SCU_REQ0 SCU_REQ1 SCU_REQ2 SCU_REQ3 GPTA_INT1 GPTA_INT3 GPTA_INT2 GPTA0_OUT3 GPTA0_OUT28 GPTA0_OUT11 rising edge detection ETR SW0 TR TTR QTR 0 1 2 3 IOUT PDOUT3 GOUT3 IOUT3 TOUT3 Output Channel 3 N C PDOUT2 GOUT2 IOUT2 TOUT2 Output Channel 2 N C PDOUT1 GOUT1 IOUT1 TOUT1...

Page 238: ... Request Unit Kernel Registers Register Short Name Register Long Name Description see ERU Kernel Registers EICR0 External Input Channel Register 0 Page 5 17 EICR1 External Input Channel Register 1 Page 5 20 EIFR External Input Flag Register Page 5 23 FMR Flag Modification Register Page 5 24 PDRR Pattern Detection Result Register Page 5 25 IGCR0 Interrupt Gating Register 0 Page 5 26 IGCR1 Interrupt...

Page 239: ... 9 8 7 6 5 4 3 2 1 0 0 INP0 EI EN0 LD EN0 R EN0 F EN0 0 EXIS0 0 r rw rw rw rw rw r rw r Field Bits Type Description EXIS0 5 4 rw External Input Selection 0 This bit field determines which input line is selected for signal IN0 00B Input IN00 is selected 01B Input IN01 is selected 10B Input IN02 is selected 11B Input IN03 is selected FEN0 8 rw Falling Edge Enable 0 This bit determines if the falling...

Page 240: ...it field determines the destination output channel for trigger event 0 if enabled by EIEN0 X00B The event of input channel 0 triggers output channel 0 signal INT00 X01B The event of input channel 0 triggers output channel 1 signal INT01 X10B The event of input channel 0 triggers output channel 2 signal INT02 X11B The event of input channel 0 triggers output channel 3 signal INT03 EXIS1 21 20 rw Ex...

Page 241: ...TF1 will be cleared EIEN1 27 rw External Interrupt Enable 1 This bit enables the generation of a trigger event for request channel 1 e g for interrupt generation when a selected edge is detected 0B The trigger event is disabled 1B The trigger event is enabled INP1 30 28 rw Interrupt Node Pointer This bit field determines the destination output channel for trigger event 1 if enabled by EIEN1 X00B T...

Page 242: ...Selection 2 This bit field determines which input line is selected for signal IN2 00B Input IN20 is selected 01B Input IN21 is selected 10B Input IN22 is selected 11B Input IN23 is selected FEN2 8 rw Falling Edge Enable 2 This bit determines if the falling edge of signal IN2 is used to set bit INTF2 0B The falling edge is not used 1B The detection of a falling edge of IN2 generates a trigger event...

Page 243: ...it field determines the destination output channel for trigger event 2 if enabled by EIEN2 X00B The event of input channel 2 triggers output channel 0 signal INT20 X01B The event of input channel 2 triggers output channel 1 signal INT21 X10B The event of input channel 2 triggers output channel 2 signal INT22 X11B The event of input channel 2 triggers output channel 3 signal INT23 EXIS3 21 20 rw Ex...

Page 244: ...TF3 will be cleared EIEN3 27 rw External Interrupt Enable 3 This bit enables the generation of a trigger event for request channel 3 e g for interrupt generation when a selected edge is detected 0B The trigger event is disabled 1B The trigger event is enabled INP3 30 28 rw Interrupt Node Pointer This bit field determines the destination output channel for trigger event 3 if enabled by EIEN3 X00B T...

Page 245: ...Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 INT F3 INT F2 INT F1 INT F0 r rh rh rh rh Field Bits Type Description INTFx x 0 3 x rh External Interrupt Flag of Channel x This bit monitors the status flag of the event trigger condition for the input channel x This bit is automatically cleared when the selected condition see RENx F...

Page 246: ...24 23 22 21 20 19 18 17 16 0 FC 3 FC 2 FC 1 FC 0 r w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS 3 FS 2 FS 1 FS 0 r w w w w Field Bits Type Description FSx x 0 3 x w Set Flag INTFx for Channel x Setting this bit will set the corresponding bit INTFx in register EIFR Reading this bit always delivers a 0 0B The bit x in register EIFR is not modified 1B The bit x in register EIFR is set FCx x 0 3...

Page 247: ...ern Detection Result Register F0000090H Reset Value 0000 000FH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PDR 3 PDR 2 PDR 1 PDR 0 r rh rh rh rh Field Bits Type Description PDRy y 0 3 y rh Pattern Detection Result of Channel y This bit monitors the output status of the pattern detection for the output channel y 0 31 4 r Reserved Read as 0 should be w...

Page 248: ... x rw Interrupt Pattern Enable for Channel 0 Bit IPEN0x determines the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy 0B The bit INTFx does not take part in the pattern detection 1B The bit INTFx is taken into consideration for the pattern detection GEEN0 13 rw Generate Event Enable 0 Bit GEEN0 enables the generatio...

Page 249: ...ile the pattern is not detected IPEN1x x 0 3 16 x rw Interrupt Pattern Enable for Channel 1 Bit IPEN1x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy 0B The bit INTFx does not take part in the pattern detection 1B The bit INTFx is taken into consideration for the pattern detection GEEN1 29 rw Gener...

Page 250: ... is always possible due to a trigger event 01B The detected pattern is not taken into account An activation of IOUT1 is not possible 10B The detected pattern is taken into account An activation of IOUT1 is only possible due to a trigger event while the pattern is detected 11B The detected pattern is taken into account An activation of IOUT1 is only possible due to a trigger event while the pattern...

Page 251: ... takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy 0B The bit INTFx does not take part in the pattern detection 1B The bit INTFx is taken into consideration for the pattern detection GEEN2 13 rw Generate Event Enable 2 Bit GEEN2 enables the generation of a trigger event for output channel 2 when the result of the pattern detection changes Whe...

Page 252: ...ile the pattern is not detected IPEN3x x 0 3 16 x rw Interrupt Pattern Enable for Channel 3 Bit IPEN3x determines if the flag INTFx of channel x takes part in the pattern detection for the gating of the requests for the output signals GOUTy and IOUTy 0B The bit INTFx does not take part in the pattern detection 1B The bit INTFx is taken into consideration for the pattern detection GEEN3 29 rw Gener...

Page 253: ... is always possible due to a trigger event 01B The detected pattern is not taken into account An activation of IOUT3 is not possible 10B The detected pattern is taken into account An activation of IOUT3 is only possible due to a trigger event while the pattern is detected 11B The detected pattern is taken into account An activation of IOUT3 is only possible due to a trigger event while the pattern...

Page 254: ...gger Gating ADC0 Register F000009CH Reset Value 0000 0000H TGADC1 Trigger Gating ADC1 Register F00000A0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SW0GTSEL 0 EGTSEL r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TTRSEL 0 QTRSEL 0 SW0TRSEL 0 ETRSEL r rw r rw r rw r rw Field Bits Type Description ETRSEL 2 0 rw External Trigger Request Selection This bit determines w...

Page 255: ...rigger source will be used for the queue trigger request input QTR of ADCx 000B QTR is constant at 0 level trigger function switched off 001B ROUT0 is connected to QTR 010B ROUT1 is connected to QTR 011B ROUT2 is connected to QTR 100B TOUT0 is connected to QTR 101B TOUT1 is connected to QTR 110B TOUT2 is connected to QTR 111B TOUT3 is connected to QTR TTRSEL 14 12 rw Timer Trigger Request Selectio...

Page 256: ...abled 101B PDOUT1 is connected to EGT 110B PDOUT2 is connected to EGT 111B PDOUT3 is connected to EGT SW0GTSEL 22 20 rw SW0 Gating Selection This bit determines which trigger source will be used for the SW0 gating input SW0GT of ADCx 000B SW0GT is constant at 0 level SW0 triggered conversions permanently disabled 001B PDOUT0 is connected to SW0GT 010B PDOUT2 is connected to SW0GT 011B PDOUT3 is co...

Page 257: ...t flag FX is set Both interrupts are combined to one interrupt request output that is controlled by register DMA_SYSSCR0 in the DMA controller Bit SCU_CON FIEN determines whether an inexact condition will lead to an interrupt or not When an FPU interrupt is generated the related FPU status flags are latched into the corresponding bits of the SCU Status Register SCU_STAT see Page 5 67 Thus the stat...

Page 258: ...e error Single bit ECC error Each source can be individually enabled and disabled The detailed description of the flash interrupt generation can be found at Flash Interrupt Generation and Control on Page 7 36 The Flash interrupt uses the system interrupt node DMA_SYSSRC1 located in the DMA module 5 4 3 External Interrupts As shown in Figure 5 5 on Page 5 15 the External Request Unit provides two i...

Page 259: ... Note that if PARAV 0 the SRAM parity error logic cannot be enabled anymore except by a power on reset operation Before the parity logic of an SRAM memory block can be used the first time after a power on reset operation before setting its SCU_PETCR PENx enable bit the corresponding memories must be completely initialized by writing every memory location of it once exceptions MultiCAN module memor...

Page 260: ...ser s Manual 5 38 V2 0 2007 07 SCU V2 0 Figure 5 7 Control of SRAM Parity Error Detection in SCU MCA06448 PEN0 PFL0 Set Data Memory Parity Error Non Maskable Interrupt PEN6 PFL6 Set CAN Module Memory Parity Error SCU_PETCR SCU_PETCR SCU_PETSR SCU_PETSR 1 ...

Page 261: ...ue 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PEN 6 PEN 5 PEN 4 PEN 3 PEN 2 PEN 1 PEN 0 r rw rw rw rw rw rw rw Field Bits Type Description PENx x 0 6 x rw Parity Error Trap Enable for SRAM Module x These bits determine whether an NMI trap is generated if a parity error is detected in the associated SRAM memory module The assignment of the...

Page 262: ...0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PFL 6 PFL 5 PFL 4 PFL 3 PFL 2 PFL 1 PFL 0 r rh rh rh rh rh rh rh Field Bits Type Description PFLx x 0 6 x rh Parity Error Flag for SRAM Module x These bits indicate whether a parity error has been detected in the associated SRAM memory module The assignment of the error flags to the SRAM modules is defined in Table 5 5 0B No parity error detected 1B Pari...

Page 263: ...er each overflow of SCOUNT the pad oscillator circuit fPOSC which is located in the pad area and an 8 bit counter THCOUNT are enabled for one clock period of the reference clock The oscillator circuit is temperature sensitive and typically has a much higher frequency 8 16 MHz than fREF The 8 bit counter counts the fPOSC pulses and its count value THCOUNT when stopped again is compared against thre...

Page 264: ... Temperature compensation is initialized by programming register SCU_TCCON enable and prescaler for 100 kHz reference clock and register SCU_TCLR0 and SCU_TCLR1 levels values The temperature dependent counter value THCOUNT is compared against three thresholds values correspond to a certain temperature level at which the 2 bit output signals to the pad logic are switched see Figure 5 9 The three th...

Page 265: ...s have not been initialized Note Reprogramming of the threshold levels in registers SCU_TCLR0 and SCU_TCLR1 should only be executed while the temperature compensation is disabled Figure 5 9 Temperature Compensation Switching Thresholds Table 5 6 Switching Threshold Hierarchy Output Driver Control Relationship between THCOUNT and THMAX THMED THMIN Maximum Level THCOUNT THMAX High Level THMED THCOUN...

Page 266: ...escription TCV0 1 0 rh Temperature Compensation 0 Value This bit field indicates the compensation value that is generated for the temperature compensation logic 0 TCV0 is fed to the temperature compensation logic 0 outputs while bit TCS0 0 00B Minimum driving strength required i e very low temperature B 11B Maximum driving strength required i e very high temperature default after reset TCE0 3 rw T...

Page 267: ...S1 0 00B Minimum driving strength required i e very low temperature B 11B Maximum driving strength required i e very high temperature default after reset TCE1 19 rw Temperature Compensation 1 Enable 0B Temperature compensation logic 1 is deactivated default after reset The port drivers are at maximum driver level 1B Temperature compensation logic 1 is active THCOUNT is periodically updated TCC1 21...

Page 268: ...D0 THMIN0 rw rw Field Bits Type Description THMIN0 7 0 rw Minimum Threshold for Temp Compensation 0 Driver level Low or Min THMED0 15 8 rw Medium Threshold for Temp Compensation 0 Driver level High or Low THMAX0 23 16 rw Maximum Threshold for Temp Compensation 0 Driver level Max or High THCOUNT 31 24 rh Threshold Counter Returns the actual count value of the counter that counts the fPOSC clock pul...

Page 269: ...D1 THMIN1 rw rw Field Bits Type Description THMIN1 7 0 rw Minimum Threshold for Temp Compensation 1 Driver level Low or Min THMED1 15 8 rw Medium Threshold for Temp Compensation 1 Driver level High or Low THMAX1 23 16 rw Maximum Threshold for Temp Compensation 1 Driver level Max or High THCOUNT 31 24 rh Threshold Counter Returns the actual count value of the counter that counts the fPOSC clock pul...

Page 270: ...nt Bit ADC1_CHCON15 EMUX 0 has to be set to 1 for channel 15 of ADC1 The analog input AIN31 of ADC1 has to be requested for conversion corresponding GRPS 1 With this request the reference voltages of the DTS VAREF_DTS VANGD_DTS and the sensor output signal VDTS are connected to ADC1 for AD conversion Figure 5 10 Die Temperature Sensor Selection The die temperature can be determined according to th...

Page 271: ...U SCU_CON GIN1S Bit GIN1S controls a 4 to 1 multiplexer that makes it possible to switch several port lines to the IN1 input of the GPTA1 module After reset the nominal GPTA input IN1 P2 9 is connected to IN1 of GPTA Figure 5 11 GPTA1 Input IN1 Control Table 5 7 GPTA1 Input Line IN1 Connections SCU_CON GIN1S GPTA1 Input IN1 Connected to 00B P2 9 IN1 default after reset 01B P5 0 RXD0A 10B P6 8 RXD0...

Page 272: ...le to access at maximum sixteen of the dedicated pins independently from each other Figure 5 12 Pad Test Mode Control in the SCU When the pad test mode is disabled PTMEN 0 the dedicated pads are in their normal operating mode The pad output drivers are controlled by the hardware part that determines whether the dedicated pad pin is used for input output or for I O purposes When the pad test mode i...

Page 273: ...as defined through ENOUTn and RDSSn can be changed without leaving the pad test mode by writing SCU_PTCON with new values for bits ENOUTn and RDSSn and PTMLC A5H In pad test mode any other write operation to SCU_PTCON with lock code PTMLC not equal to A5H terminates the pad test mode After pad test mode has been enabled via the two word write operation to SCU_PTCON it can be disabled again by any ...

Page 274: ...tput for Pad Test Data Register n In pad test mode PTMEN 1 these bits determine whether or not the logic level state as defined by the bits in the SCU_PTDATn register is switched as inverted state to the pad pin 0B Pad drivers of the pad test data register n related pads are disabled 1B Pad drivers of the pad test data register n related pads are enabled and the bits in the pad test data register ...

Page 275: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MR W ADV RD WR RD BC3 BC2 BC1 BC0 A23 A22 A21 A20 A19 A18 A17 A16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description An n 0 23 n rwh Pad Test Value for of ...

Page 276: ... rwh rwh rwh rwh rwh rwh Field Bits Type Description TRn n 0 15 n rwh Pad Test Value for of TRn BRKIN 16 rwh Pad Test Value for of BRKIN BRKOUT 17 rwh Pad Test Value for of BRKOUT TRCLK 18 rwh Pad Test Value for of TRCLK HDRST 19 rwh Pad Test Value for of HDRST NMI 20 rh Pad Test Value of NMI HOLD 21 rwh Pad Test Value for of HOLD HLDA 22 rwh Pad Test Value for of HLDA BREQ 23 rwh Pad Test Value f...

Page 277: ...ASS r rh rh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description BYPASS 0 rwh Pad Test Value for of BYPASS BFCLKI 1 rwh Pad Test Value for of BFCLKI BFCLKO 2 rwh Pad Test Value for of BFCLKO TRST 3 rwh Pad Test Value for of TRST TCK 4 rwh Pad Test Value for of TCK TDI 5 rwh Pad Test Value for of TDI TDO 6 rwh Pad Test Value for of TDO TMS 7 rwh Pad Test Value for of TMS TESTMODE 8 rh Pad Te...

Page 278: ...ad pin SCLK0 30 rwh Pad Test Value for of SCLK0 SLSI0 31 rwh Pad Test Value for of SLSI0 SCU_PTDAT3 SCU Pad Test Data Register 3 F00000C0H Reset Value XXXX XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 ...

Page 279: ...stead of an actual data value The emergency case is indicated to the TC1796 by an emergency input signal with selectable polarity that has to be connected to input HWCFG1 P10 1 Figure 5 13 shows a diagram of the emergency stop input logic This logic is controlled by the SCU Emergency Stop Register SCU_EMSR Figure 5 13 Emergency Stop Input Control The emergency stop control logic can basically oper...

Page 280: ...F flag can be enabled disabled for setting control bit ENON and it can be set or cleared by software too bit field EMSFM 5 10 1 GPTA Output Emergency Control in the GPIO Ports The selection of which port line of a GPIO port is affected by an active EMGSTOP signal is done in the Emergency Stop Registers Pn_ESR which are located in the port logics Each of the GPIO lines that can be assigned as GPTA ...

Page 281: ...ld Bits Type Description POL 0 rw Input Polarity This bit determines the polarity of the emergency input line HWCFG1 0B HWCFG1 is high active 1B HWCFG1 is low active MODE 1 rw Mode Selection This bit determines the operating mode of the EMGSTOP signal 0B Synchronous mode selected EMGSTOP is derived from the state of flag EMSF 1B Asynchronous mode selected EMGSTOP is directly derived from the state...

Page 282: ...ency Stop Flag This bit indicates if an emergency stop condition has occurred 0B An emergency stop has not occurred 1B An emergency stop has occurred and signal EMGSTOP becomes active if MODE 0 EMSFM 25 24 w Emergency Stop Flag Modification This bit field makes it possible to set or clear flag EMSF by software In case of a simultaneous hardware and software modification request the hardware operat...

Page 283: ...U Registers Register Short Name Register Long Name Offset Address Description see SCU_ID SCU Module IDentification Register 08H Page 5 69 SCU_SCLKFDR SCU System Clock Fractional Divider Register 0CH Page 3 42 RST_REQ Reset Request Register 10H Page 4 5 RST_SR Reset Status Register 14H Page 4 3 MCA05625_mod Identification Registers MANID CHIPID RTID OSC_CON PLL_CLC SCU_SCLKFDR RST_SR RST_REQ Clock ...

Page 284: ... 64 SCU_STAT SCU Status Register 54H Page 5 67 SCU_TCLR0 SCU Temperature Compensation 0 Level Register 58H Page 5 46 SCU_TCLR1 SCU Temperature Compensation 1 Level Register 5CH Page 5 47 MANID Manufacturer Identification Register 70H Page 5 69 CHIPID Chip Identification Register 74H Page 5 70 RTID Redesign Tracing Identification Register 78H Page 5 71 EICR0 External Input Channel Register 0 80H Pa...

Page 285: ...e 5 53 SCU_PTDAT1 SCU Pad Test Data Register 1 B8H Page 5 54 SCU_PTDAT2 SCU Pad Test Data Register 2 BCH Page 5 55 SCU_PTDAT3 SCU Pad Test Data Register 3 C0H Page 5 56 SCU_PETCR SCU Parity Error Trap Control Register D0H Page 5 39 SCU_PETSR SCU Parity Error Trap Status Register D4H Page 5 40 Table 5 9 SCU Registers cont d Register Short Name Register Long Name Offset Address Description see ...

Page 286: ...000050H Reset Value FF00 0002H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ONE ZERO GIN1S SSC 0 PDR SLS PDR rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RPA RAV LD EN DTS ON 0 AN7 TM NMI EN EPU D CS GEN CS OEN CS EEN FIEN r rw rw rw r rw rws rw rw rw rw rw Field Bits Type Description FIEN 0 rw FPU Inexact Interrupt Enable 0B Inexact error condition setting FX flag after a FPU calcula...

Page 287: ...d with any reset It can be only set by software and will remain in this state until the next reset Writing a zero to this bit has no effect The NMI is described in detail at Section 14 10 on Page 14 25 AN7TM 6 rw Analog Input 7 Test Mode 0B Pull down of analog input 7 is disabled default after reset 1B Pull down of analog input 7 is enabled DTSON 9 rw Die Temperature Sensor On 0B Die temperature s...

Page 288: ...1B RxD0A 10B RxD0B 11B RxD1B Details of GIN1S control are described in Section 5 8 on Page 5 49 ZERO 23 20 rw Spare 0 Control Bits This bit field contains bits that are reserved for future SCU control tasks Field ZERO is set to 00H after reset ZERO bits should be written with 00H Reading ZERO bits will return the value last written ONE 31 24 rw Spare 1 Control Bits This bit field contains bits tha...

Page 289: ...hardware resources is left after a specific Boot ROM exit SCU_STAT SCU Status Register F0000054H Reset Value 0000 E000H 1 1 The initial value of SCU_STAT after Boot ROM exit is 0000 2000B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PAR AV 0 EEA 0 FII FVI FZI FUI FXI r rh r rh r rh rh rh rh rh Field Bits Type Description FXI 0 rh FPU Inexact Result In...

Page 290: ...ates if the emulation extension 1796ED is available or not production device 0B EEC is not available 1B EEC is available PARAV 13 rh Parity Available 0B SRAM parity logic is disabled 1B SRAM parity logic is enabled This bit is set with any power on reset It can be cleared by software by writing bit SCU_CON RPARAV It cannot be set by software More details about PARAV are described below Table 5 5 o...

Page 291: ...dule Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module identification number for the SCU 002CH MANID Manufacturer Identification Register F0000070H Reset Value 0000 1820H 31 16 ...

Page 292: ... Identification Register F0000074H Reset Value 0000 8AXXH 31 16 15 8 7 0 0 CHID CHREV r r r Field Bits Type Description CHREV 7 0 r Chip Revision Number This bit field indicates the revision number of the TC1796 device 01H first revision CHREV can be used e g for major step identification purposes The value of this bit field is defined in the TC1796 Data Sheet CHID 15 8 r Chip Identification Numbe...

Page 293: ...racing Identification Register F0000078H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RT 15 RT 14 RT 13 RT 12 RT 11 RT 10 RT 9 RT 8 RT 7 RT 6 RT 5 RT 4 RT 3 RT 2 RT 1 RT 0 r r r r r r r r r r r r r r r r Field Bits Type Description RTn n 0 15 n r Redesign Trace Bit n 0B No change indicated 1B A change has been made without changin...

Page 294: ... SBRAM 64 KB SRAM Local Memory to FPI Bus Interface LFI Bridge PBCU DBCU Remote Peripheral Bus PLMB DLMB RPB Program Local Memory Bus Data Local Memory Bus System Peripheral Bus SPB MCB05626_mod Emulation Memory Interface To Emulation Memory Emulation device only LMI Floating Point Unit FPU TriCore CPU Data Memory Interface DMI 56 KB LDRAM 8 KB DPRAM Program Memory Interface PMI 48 KB SPRAM 16 KB ...

Page 295: ... used for these buses 6 1 1 Overview The LMB is a synchronous and pipelined bus with variable block size transfer support The protocol supports 8 16 32 and 64 bit single transactions and 2 4 wide 64 bit block transfers The LMB has the following features Optimized for high speed and high performance data transfers 32 bit address bus 64 bit data bus Simple central arbitration per cycle Slave control...

Page 296: ...ated by instructions that require two single transfers e g read modify write instructions such as LDMST ST T and SWAP W During an atomic transfer any other LMB master is blocked for gaining bus ownership 6 1 3 Address Alignment Rules Depending on the data size there are rules that determine the address alignment of an LMB transfer 1 Byte accesses must be always located on byte address boundaries 2...

Page 297: ...quest grant cycle the master puts the address on the LMB and all LMB slave devices check whether they are addressed for the following data cycle 3 Data Cycle In the data cycle either the LMB master puts write data on the LMB which is read by the LMB slave write cycle or vice versa read cycle Transfers 2 and 3 show the conflict when two masters try to use the LMB and how the conflict is resolved In...

Page 298: ...nt data such as bus address bus data and bus status information in register where the information can be analyzed by software 6 2 2 LMB Bus Arbitration All LMB master devices requesting the LMB will participate in an arbitration round Arbitration rounds are performed in each cycle that preceeds a possible address cycle Each LMB master device has a fixed priority as shown in Table 6 2 For all the m...

Page 299: ...als of the transaction causing the error are captured and stored in the following registers The LMB Error Address Register LEADDR stores the LMB address that has been captured during the last erroneous LMB transaction The LMB Error Data Low High Registers LEDATL LEDTAH store the 64 bit LMB data bus information that has been captured during the last erroneous LMB transaction The LMB Error Attribute...

Page 300: ... PBCU F87F FE00H F87F FEFFH Table 6 4 Registers Overview LMB Bus Control Unit Registers Register Short Name1 1 Prefix x D stands for DBCU and x P for PBCU Register Long Name Offset Address Description see xBCU_ID xBCU Module Identification Register 08H Page 6 8 xBCU_LEATT xBCU LMB Error Attribute Register 20H Page 6 9 xBCU_LEADDR xBCU LMB Error Address Register 24H Page 6 12 xBCU_LEDATL xBCU LMB E...

Page 301: ...eset Value 000F C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module identification...

Page 302: ...LMB bus error will be captured 1B The error capture mechanism is locked The registers LEADDR LEDATL LEDATH and bits 31 4 of LEATT contain valid data LEC is automatically set when an LMB bus error has been captured Any further LMB bus error is not captured if LEC 1 When writing a 1 to LEC the error capture mechanism becomes unlocked and is ready for the next LMB bus error capture event FPITAG 7 4 r...

Page 303: ...ddress occurred SVM 21 rh LMB Bus Supervisor Mode This bit indicates whether the LMB bus error occurred in supervisor mode or in user mode 0B Transfer was initiated in supervisor mode 1B Transfer was initiated in user modes WR 22 rh LMB Bus Write Error Indication This bit indicates whether the LMB bus error occurred at a write cycle see Table 6 5 RD 23 rh LMB Bus Read Error Indication This bit ind...

Page 304: ...fer 0010B 32 bit data single transfer 0011B 64 bit data single transfer 1000B 2 64 bit data block transfer 1001B 4 64 bit data block transfer other Reserved 0 3 1 14 8 20 27 r Reserved Read as 0 should be written with 0 Table 6 5 LMB Read Write Error Indication RD WR LMB Bus Cycle 0 0 LMB bus error occurred at the read cycle of an atomic transfer 0 1 LMB bus error occurred at a read cycle of a sin...

Page 305: ... been captured at an LMB bus error LEADDR only contains valid read data when bit LEC in the corresponding register LEATT is set DBCU_LEDATL DBCU LMB Error Data Low Register 28H Reset Value XXXX XXXXH PBCU_LEDATL PLMB LMB Error Data Low Register 28H Reset Value XXXX XXXXH 31 0 LEDAT 31 0 rh Field Bits Type Description LEDAT 31 0 31 0 rh LMB Bus Address Bits 31 0 This bit field holds the lower 32 bi...

Page 306: ...n captured at an LMB bus error LEDAT 63 32 only contains valid read data when bit LEC in the corresponding register LEATT is set DBCU_SRC DLMB Service Request Control Register FCH Reset Value 0000 0000H PBCU_SRC PBCU Service Request Control Register FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE TOS 0 SRPN w ...

Page 307: ... on interrupt handling and processing are described in Chapter 14 of this TC1796 System Units Vol 1 of 2 User s Manual SRE 12 rw Service Request Enable SRR 13 rh Service Request Flag CLRR 14 w Request Flag Clear Bit SETR 15 w Request Flag Set Bit 0 9 8 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 308: ... by the PCP DMA controller or Cerberus via the LFI Bridge that address a DLMB or PLMB slave device are translated into a DLMB address according Table 6 6 Bus Errors at Writes via the LFI Bridge When a write operation has been initiated and directed to the LFI Bridge by a SPB bus master the LFI Bridge handles the write transaction at the LMBs DLMB and PLMB autonomously If the write operation at the...

Page 309: ...LFI Register This section describes the kernel register of the LFI Bridge LFI Register Figure 6 5 LFI Register The complete and detailed address map of LFI is described in Table 18 42 on Page 18 126 of this TC1796 System Units Vol 1 of 2 User s Manual Table 6 7 Registers Address Space LFI Bridge Module Base Address End Address Note LFI F87F FF00H F87F FFFFH Table 6 8 Registers Overview LFI Registe...

Page 310: ...on starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module identification number for the LFI 000CH LFI_CON LFI Configuration Register 10H Reset Value 0000 0B02H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FTAG 0 LTAG 0 1 0 r...

Page 311: ...0 2007 07 Buses V2 0 LTAG 6 4 rh LMB Bus DLMB Tag ID In the TC1796 the bit field LTAG 000B FTAG 11 8 rh FPI Bus SPB Tag ID In the TC1796 the bit field FTAG 1011B which reflects the tag number of the LFI Bridge on the SPB 0 3 2 7 31 12 r Reserved Returns 0 if read Field Bits Type Description ...

Page 312: ...Bus acquisition which is required for time critical applications The FPI Bus is designed to sustain high transfer rates For example a peak transfer rate of up to 160 Mbyte s can be achieved with the 32 bit data bus at 40 MHz bus clock Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth Additional features of the FPI Bus include Optimized fo...

Page 313: ... the various modules FPI Bus arbitration is performed by the Bus Control Unit BCU of the FPI Bus In case of bus errors the BCU generates an interrupt request to the CPU and provides debugging information about the actual bus error to the CPU In the TC1796 device external memory peripheral accesses are handled via the EBU as part of the PMU Therefore the FPI Buses are not required for such type of ...

Page 314: ...T D and ST DA The BCOPY instruction of the PCP also initiates a block transfer transaction on the FPI Bus Atomic Transfers Atomic transfers are generated by LDMST ST T and SWAP W instructions that require two single transfers The read and write transfer of an atomic transfer are always locked and cannot be interrupted by another bus masters Atomic transfers are also referenced as read modify write...

Page 315: ...e FPI Bus controller 2 Address Cycle After the request grant cycle the master puts the address on the FPI Bus and all FPI Bus slave devices check whether they are addressed for the following data cycle 3 Data Cycle In the data cycle either the master puts write data on the FPI Bus which is read by the FPI Bus slave write cycle or vice versa read cycle Transfers 2 and 3 show the conflict when two m...

Page 316: ...Bus Bridges User s Manual 6 23 V2 0 2007 07 Buses V2 0 Figure 6 8 FPI Bus Block Transactions Request Grant Data Cycle Address Cycle Bus Cycle 1 2 3 4 Request Grant Address Cycle 5 MCA05635 Transfer 1 Transfer 2 6 Data Cycle 7 Data Cycle Data Cycle Data Cycle ...

Page 317: ... SPB bus master Each agent is supplied a arbitration priority as shown in Table 6 9 DMA controller and OCDS agents can be assigned to low or high priorities by software If there is no request from a SPB bus master the SPB is granted to a default master PCP or LFI Bridge which has been at last the default master 6 5 1 2 Arbitration on the Remote Peripheral Bus The TC1796 RPB has only one bus master...

Page 318: ...ll be granted service If there are several masters to which this starvation condition applies they are served in the order of their hard wired priority ranking Starvation protection can be enabled and disabled through bit SBCU_CON SPE The sample period of the counter is programmed through bit field SBCU_CON SPC SPC should be set to a value at least greater than or equal to the number of masters It...

Page 319: ...CU_EDAT respectively are self explanatory the captured FPI Bus control information needs some more explanation Register xBCU_ECON captures the state of the read RDN write WRN Supervisor Mode SVM acknowledge ACK ready RDY abort ABT time out TOUT bus master identification lines TAG and transaction operation code OPC lines of the FPI Bus The SVM signal is set to 1 for an access in Supervisor Mode and...

Page 320: ...off its clock and return to idle mode Automatic power management is controlled through the xBCU_CON PSE bit When cleared to 0 power management is disabled and the BCU clock is always active This might be required for instance to debug both the active and idle FPI Bus states of an application via an external emulator or other debugging hardware Table 6 11 FPI Bus Master TAG Assignments TAG Number F...

Page 321: ...Address triggers Signal triggers Grant triggers 6 5 4 1 Address Triggers The address debug trigger event conditions are defined by the contents of the xBCU_DBADR1 xBCU_DBADR2 and xBCU_DBCNTL registers A wide range of possibilities arise for the creation of debug trigger events based on addresses The following debug trigger events can be selected Match on one signal address Match on one of two sign...

Page 322: ... The selection whether or not a single match condition is selected can be enabled disabled selectively for each condition via the xBCU_DBCNTL ONBOSx bits Figure 6 10 Signal Status Trigger Generation 6 5 4 3 Grant Triggers The signal status debug trigger event conditions are defined via the registers xBCU_DBGRNT and xBCU_DBCNTL Depending on the configuration of these registers any combination of FP...

Page 323: ... AND or OR combination can be selected for the BCU breakpoint trigger generation Figure 6 12 BCU Breakpoint Trigger Combination Logic MCA05638 Grant Trigger SBCU_DBGRNT DMA H LFI DMA L CBL Cerberus is granted as bus master low priority DMA is granted as bus master low priority PCP CBH LFI Bridge is granted as bus master DMA is granted as bus master high priority PCP is granted as bus master Cerber...

Page 324: ...ettings of bits RD and WR in register SBCU_DBBOS Debug trigger event generation for supervisor mode signal match and opcode signal match condition is disabled ONA2 01B means that the equal match condition for debug address 2 register is selected ONA1 01B means that the equal match condition for debug address 1 register is selected ONG 1 means that the grant debug trigger is enabled CONCOM 2 0 101B...

Page 325: ...led CONCOM 2 0 110B means that the address trigger is created by address trigger 1 AND address trigger 2 CONCOM1 1 and that the grant trigger is OR ed with the address trigger CONCOM0 0 and that the signal status trigger is ANDed with the address trigger CONCOM2 1 RA 1 means that the BCU breakpoint logic is rearmed 4 Writing SBCU_DBGRNT FFFFFFFFH means that no grant trigger for SPB masters is sele...

Page 326: ...s created by address trigger 1 OR address trigger 2 CONCOM1 0 and that the grant trigger is ANDed with the address trigger CONCOM0 1 and that the signal status trigger is ANDed with the address trigger CONCOM2 1 RA 1 means that the BCU breakpoint logic is rearmed 4 Writing SBCU_DBGRNT FFFFFFF7H means that the grant trigger for the SPB bus master PCP is enabled 5 Writing SBCU_DBBOS is don t care No...

Page 327: ...FH Table 6 14 Registers Overview SBCU Registers Register Short Name1 Register Long Name Offset Address Description see xBCU_ID xBCU Module Identification Register 08H Page 6 36 xBCU_CON xBCU Control Register 10H Page 6 37 xBCU_ECON xBCU Error Control Capture Register 20H Page 6 39 xBCU_EADD xBCU Error Address Capture Register 24H Page 6 41 xBCU_EDAT xBCU Error Data Capture Register 28H Page 6 41 x...

Page 328: ...xBCU Debug Bus Operation Signals Register 0040H Page 6 49 SBCU_DBGNTT SBCU Debug Trapped Master Register 0044H Page 6 51 RBCU_DBGNTT RBCU Debug Trapped Master Register Page 6 53 xBCU_DBADRT xBCU Debug Trapped Address Register 0048H Page 6 54 xBCU_DBBOST xBCU Debug Trapped Bus Operation Signals Register 004CH Page 6 55 xBCU_SRC xBCU Service Request Control Register 00FCH Page 6 58 1 Prefix x S stan...

Page 329: ...ample period the bus time out period enabling starvation protection mode and error handling SBCU_ID SBCU Module Identification Register 08H Reset Value 0000 6AXXH RBCU_ID RBCU Module Identification Register 08H Reset Value 0000 6AXXH 31 16 15 8 7 0 0 MODNUM MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module r...

Page 330: ...ral Bus time out cycles Default after reset is FFFFH 65536 bus cycles 1 DBG 16 rw BCU Debug Trace Enable 0B BCU debug trace disabled 1B BCU debug trace enabled default after reset PSE 18 rw BCU Power Saving Automatic Clock Control Enable 0B BCU power saving disabled default after reset 1B BCU power saving enabled SPE 19 rw BCU Starvation Protection Enable 0B BCU starvation protection disabled 1B B...

Page 331: ...N DBG 0 the BCU error capture registers remain untouched Note The BCU error capture registers store only the parameters of the first error In case of multiple bus errors an error counter BCU_ECON ERRCNT shows the number of bus errors since the first error occurred A hardware reset clears this bit field to zero but the counter can be set to any value through software This counter is prevented from ...

Page 332: ...er ERRCNT is incremented on every occurrence of an FPI Bus error ERRCNT is reset to 0000H after the ECON register is read 1 TOUT 16 rwh State of FPI Bus Time Out Signal This bit indicates the state of the time out signal at an FBI Bus error 0B No time out occurred 1B Time out has occurred RDY 17 rwh State of FPI Bus Ready Signal This bit indicates the state of the ready signal at an FBI Bus error ...

Page 333: ...ndicates whether the FPI Bus error occurred at a read cycle see Table 6 15 TAG 27 24 rwh FPI Bus Master Tag Number Signals This bit field indicates the FPI Bus master TAG number definitions see Table 6 11 OPC 31 28 rwh FPI Bus Operation Code Signals The FPI Bus operation codes are defined in Table 6 12 1 For the SBCU_ECON ERRCNT bit field the following additional sentence must be added in the TC17...

Page 334: ...he 32 bit FPI Bus address that has been captured at an FPI Bus error Note that if multiple bus errors occurred only the address of the first bus error is captured SBCU_EDAT SBCU Error Data Capture Register 28H Reset Value 0000 0000H RBCU_EDAT RBCU Error Data Capture Register 28H Reset Value 0000 0000H 31 0 FPIDAT rwh Field Bits Type Description FPIDAT 31 0 rwh Captured FPI Bus Address This bit fie...

Page 335: ... 0 RA 0 OA EO r rw rw rw r w r r r Field Bits Type Description EO 0 r Status of BCU Debug Support Enable This bit is controlled by the Cerberus and enables the BCU debug support 0B BCU debug support is disabled 1B BCU debug support is enabled default after reset OA 1 r Status of BCU Breakpoint Logic 0B The BCU breakpoint logic is disarmed Any further breakpoint activation is discarded 1B The BCU b...

Page 336: ...th a logical AND for further control see Figure 6 12 CONCOM2 14 rw Address and Signal Trigger Relation 0B Address trigger condition and signal trigger condition are combined with a logical OR for further control 1B Address trigger condition and the signal trigger condition are combined with a logical AND for further control see Figure 6 12 ONG 16 rw Grant Trigger Enable 0B No grant debug event tri...

Page 337: ...fined in DBBOS OPC see Figure 6 10 ONBOS1 29 rw Supervisor Mode Signal Trigger Condition 0B The signal status trigger generation for the FPI Bus supervisor mode signal is disabled 1B A signal status trigger is generated if the FPI Bus supervisor mode signal state is equal to the value of DBBOS SVM see Figure 6 10 ONBOS2 30 rw Write Signal Trigger Condition 0B The signal status trigger generation f...

Page 338: ...rberus Grant Trigger Enable High Priority 0B FPI Bus transactions on SPB with high priority Cerberus as bus master are enabled for grant trigger event generation 1B FPI Bus transactions on SPB with high priority Cerberus as bus master are disabled for grant trigger event generation 1 2 1 15 8 rw Reserved Read as 1 after reset reading these bits will return the value last written PCP 3 rw PCP Grant...

Page 339: ... transactions on SPB with LFI Bridge as bus master are disabled for grant trigger event generation DMAL 6 rw DMA Grant Trigger Enable Low Priority 0B FPI Bus transactions on SPB with high priority DMA channels as bus master are enabled for grant trigger event generation 1B FPI Bus transactions on SPB with high priority DMA channels as bus master are disabled for grant trigger event generation CBL ...

Page 340: ... rw DMA Grant Trigger Enable High Priority 0B FPI Bus transactions on RPB with low priority DMA channels as bus master are enabled for grant trigger event generation 1B FPI Bus transactions on RPB with low priority DMA channels as bus master are disabled for grant trigger event generation DMAL 6 rw DMA Grant Trigger Enable Low Priority 0B FPI Bus transactions on RPB with high priority DMA channels...

Page 341: ... 31 0 ADR1 rw Field Bits Type Description ADR1 31 0 rw Debug Trigger Address 1 This register contains the address for the address 1 trigger event generation SBCU_DBADR2 SBCU Debug Address 2 Register 3CH Reset Value 0000 0000H RBCU_DBADR2 RBCU Debug Address 2 Register 3CH Reset Value 0000 0000H 31 0 ADR2 rw Field Bits Type Description ADR2 31 0 rw Debug Trigger Address 2 This register contains the ...

Page 342: ... of a FPI Bus transaction for which a signal status debug trigger event is generated if enabled by DBCNTL ONBOS0 1 0000B Trigger on single byte transfer selected 0001B Trigger on single half word transfer selected 0010B Trigger on single word transfer selected 0100B Trigger on 2 word block transfer selected 0101B Trigger on 4 word block transfer selected 0110B Trigger on 8 word block transfer sele...

Page 343: ...single write transfer or write cycle of an atomic transfer selected 1B No operation or read transaction selected RD 12 rw Write Signal for Status Debug Trigger This bit determines the state of the RD signal of an FPI Bus transaction for which a signal status debug trigger event is generated if enabled by DBCNTL ONBOS3 1 0B Trigger on a single read transfer or read cycle of an atomic transfer selec...

Page 344: ...I Bus Master Status This bit indicates whether the high priority Cerberus was SPB bus master when the break trigger event occurred 0B The high priority Cerberus was not a SPB bus master 1B The high priority Cerberus was SPB bus master PCP 3 rh PCP FPI Bus Master Status This bit indicates whether the PCP was SPB bus master when the break trigger event occurred 0B The PCP was not a SPB bus master 1B...

Page 345: ...rh Low Priority Cerberus FPI Bus Master Status This bit indicates whether the low priority Cerberus was SPB bus master when the break trigger event occurred 0B The low priority Cerberus was not a SPB bus master 1B The low priority Cerberus was SPB bus master CHNR0y y 0 7 16 y rh DMA Channel Number Status These bits indicate which DMA channel with number 0y was active when a DMA break trigger event...

Page 346: ...its Type Description 1 3 0 5 15 7 rw Reserved Read as 1 DMAH 2 rh High Priority DMA FPI Bus Master Status This bit indicates whether the high priority DMA channels were RPB bus master when the break trigger event occurred 0B The high priority DMA channels were not a RPB bus master 1B The high priority DMA channels were RPB bus master Bits CHNRxy determine the DMA channel number DMAL 4 rh Low Prior...

Page 347: ... Channel Number Status These bits indicate which DMA channel with number 1y was active when a DMA break trigger event occurred at the RPB 0B DMA channel 1y was not active at a DMA break trigger event at the RPB 1B DMA channel 1y was active at a DMA break trigger event at the RPB SBCU_DBADRT SBCU Debug Trapped Address Register 48H Reset Value 0000 0000H RBCU_DBADRT RBCU Debug Trapped Address Regist...

Page 348: ...I OPC r rh rh rh rh rh rh rh rh rh rh Field Bits Type Description FPIOPC 3 0 rh FPI Bus Opcode Status This bit field indicates the type opcode of the FPI Bus transaction captured from the FPI Bus signal lines when the BCU break trigger event occurred 0000B Single byte transfer 0001B Single half word transfer 0010B Single word transfer 0100B 2 word block transfer 0101B 4 word block transfer 0110B 8...

Page 349: ...sfer FPIWR 8 rh FPI Bus Write Indication Status This bit indicates the write signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred 0B Single write transfer or write cycle of an atomic transfer 1B No operation or read transfer FPIRST 10 9 rh FPI Bus Reset Status This bit field indicates the reset signal status captured from the FPI Bus signal lines when the ...

Page 350: ...ration FPITOUT 14 rh FPI Bus Time out Status This bit indicates the time out signal status captured from the FPI Bus signal lines when the BCU break trigger event occurred 0B Normal operation 1B A time out event was generated FPITAG 19 16 rh FPI Bus Master TAG Status This bit indicates the master TAG captured from the FPI Bus signal lines when the BCU break trigger event occurred The master TAG id...

Page 351: ...96 System Units Vol 1 of 2 User s Manual SBCU_SRC SBCU Service Request Control Register FCH Reset Value 0000 0000H RBCU_SRC RBCU Service Request Control Register FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE TOS 0 SRPN w w rh rw r r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number T...

Page 352: ...y Bus Interface Emulation Memory Interface Figure 7 1 PMU Block Diagram 7 1 Boot ROM The functionality of the 16 Kbyte Boot ROM BROM is described in Chapter 4 Reset and Boot Operation at Page 4 16 MCB05641 Program Memory Unit PMU EBU External Bus Unit PLMB Program Local Memory Bus DFLASH Data Flash Memory PFLASH Program Flash Memory BROM Boot ROM To From Program Local Memory Bus 64 PLMB Interface ...

Page 353: ...bank of the DFLASH is busy with a program or erase operation Programming one bank of the DFLASH while the other bank of the DFLASH is busy with an erase operation and simultaneously reading from PFLASH Note It is not possible to read data from DFLASH while the PFLASH is busy with a program or erase operation The embedded Flash module is divided into the following two sub modules The Flash Interfac...

Page 354: ...se Sector State transitions during execution of the commands such as termination of command execution or errors are indicated by status flags and maskable interrupts Command sequences are normally written to the PMU by the CPU but can also be issued by the PCP or the DMA controller Flash Interface PLMB MCB05642 64 Error Correction ECC Flash Command State Machine FCS Flash Interface Control Module ...

Page 355: ...s programmed into the Flash memory with one Write Page command Thus the programming width is always 256 byte Programming of single words bytes or bits is not supported The 256 byte wide PFLASH pages are numbered with PPy with y 0 to 8191 Only one complete sector can be erased Program and erase operations are initiated and supervised by the Flash Command State Machine FCS but its execution is furth...

Page 356: ...ming is no longer possible Features of Program Flash 2 Mbyte on chip program Flash memory Usable for instruction code execution or constant data storage 256 byte wide program interface 256 bytes are programmed into PFLASH page in one step command 256 bit read interface Transfer from PFLASH to CPU PMI by four 64 bit single cycle burst transfers Dynamic correction of single bit errors during read ac...

Page 357: ...PPSx x 0 1 is a physical PFLASH sector 8000 4000H 8000 7FFFH A000 4000H A000 7FFFH PS2 16 Kbyte 8000 8000H 8000 BFFFH A000 8000H A000 BFFFH PS3 16 Kbyte 8000 C000H 8000 FFFFH A000 C000H A000 FFFFH PS4 PPS1 16 Kbyte 8001 0000H 8001 3FFFH A001 0000H A001 3FFFH PS5 16 Kbyte 8001 4000H 8001 7FFFH A001 4000H A001 7FFFH PS6 16 Kbyte 8001 8000H 8001 BFFFH A001 8000H A001 BFFFH PS7 16 Kbyte 8001 C000H 800...

Page 358: ...ASH bank is suspended by a programming operation of the other DFLASH bank and automatically resumed afterwards Each DFLASH bank can be erased only completely Figure 7 4 DFLASH Structure For programming of the DFLASH the data for one page 32 words 128 bytes must be loaded into an assembly buffer using fast CPU accesses before this assembly buffer is programmed into one page of the data Flash with o...

Page 359: ...ramming of one bank possible while erasing the other bank On chip generation of programming voltage DFLASH is delivered in erased state read all zeros JEDEC standard based command sequences for DFLASH control Write state machine controls programming and erase operations Status and error reporting by status flags and interrupt Margin check for detection of problematic DFLASH bits The DFLASH contain...

Page 360: ...on Page and the Erase User Configuration Block command Figure 7 5 UCB Flash Structure More details on UCBs are described on Page 7 27 DS1 DP512 128 byte 8FE1 0000H 8FE1 007FH AFE1 0000H AFE1 007FH DPn1 128 byte 8FE1 0000H OFF 8FE1 0000H OFF 7FH with OFF n 80H AFE1 0000H OFF AFE1 0000H OFF 7FH with OFF n 80H DP1023 128 byte 8FE1 FF80H 8FE1 FFFFH AFE1 FF80H AFE1 FFFFH 1 n 0 1023 Table 7 2 DFLASH Ban...

Page 361: ...H UCP1 256 byte A000 0100H A000 01FFH UCP2 256 byte A000 0200H A000 02FFH UCP3 256 byte A000 0300H A000 03FFH UCB1 UCP4 256 byte A000 0400H A000 04FFH UCP5 256 byte A000 0500H A000 05FFH UCP6 256 byte A000 0600H A000 06FFH UCP7 256 byte A000 0700H A000 07FFH UCB2 UCP8 256 byte A000 0800H A000 08FFH UCP9 256 byte A000 0900H A000 09FFH UCP10 256 byte A000 0A00H A000 0AFFH UCP11 256 byte A000 0B00H A...

Page 362: ...ctivation of any reset After incorrect address data values or wrong command sequence After incorrect requests password failure to program or erase a locked sector After an incorrect write access to a read protected Flash memory In Read Mode command sequences are allowed The Read Mode remains active until the last cycle of a command sequence is executed In case of a write or erase command Read Mode...

Page 363: ...l the command is really finished Note that all write operations to the Flash memory space are handled by the FCS Writing incorrect addresses or data values within a command sequence or writing them in an wrong sequence generates a sequence error FSR SQER is set and terminates Command Mode If one DFLASH bank is busy with erasing a programming command sequence for the other DFLASH bank is accepted i...

Page 364: ...flash but from other internal or external memory e g from SPRAM 7 2 4 3 Page Mode With the Enter Page Mode command Page Mode is entered for one of the three Flash banks and status flag FSR PFPAGE for PFLASH or FSR DFPAGE for DFLASH is set In Page Mode the assembly buffer is ready to be filled with data in preparation for a subsequent PFLASH or DFLASH programming operation The width of the page ass...

Page 365: ...lock fCPU frequency of 1 MHz must be provided Table 7 4 Flash Command Overview Command Description Details see Reset to Read Resetting Flash State Machine to Read Mode Page 7 15 Enter Page Mode Initiate Page Mode Page 7 15 Load Page Buffer Loading page assembly buffer with 32 bit or 64 bit data Page 7 16 Write Page Programming a Flash page with assembly buffer content Page 7 18 Write User Configur...

Page 366: ... preparation for a subsequent Flash programming operation The Page Mode can only be assigned to one of the PFLASH DFLASH banks by executing the address data information shown in Table 7 6 The width of the page assembly buffer is 128 byte for DFLASH and 256 byte for PFLASH Further the Page Mode can only be entered if the related Flash bank is not busy if it does not execute program or erase operati...

Page 367: ...ction s with the corresponding data format A single Load Page Buffer command consists of a store instruction to a specific address In case of 64 bit data width the same address A000 55F0H always has to be used In case of 32 bit data width alternating addresses A000 55F0H and A000 55F4H must be used For loading of the 256 byte wide assembly buffer for PFLASH programming thirty two Load Page command...

Page 368: ... AFE0 55F4H word 3 assembly buffer byte 15 12 1 Write AFE0 55F0H word 30 assembly buffer byte 123 120 2 Write AFE0 55F4H word 31 assembly buffer byte 127 124 Sequence errors bit FSR SQER set are generated by a Load Page Buffer command in the following cases A mix of 64 bit and 32 bit write data width within one assembly buffer filling sequence has been detected An assembly buffer overrun condition...

Page 369: ...specific Flash page with the complete content of the assembly buffer It also programs invalid data of assembler buffer locations that have not been loaded by previous Load Page Buffer commands With the last cycle of the Write Page command Page Mode is terminated and the following status flags are updated FSR PFPAGE or FSR DFPAGE is cleared indicating that the related Flash is no more in Page Mode ...

Page 370: ...The address transmitted in cycle 4 of the Write User Configuration Page command is the start address of the corresponding User Configuration Page UCP 11 0 see Table 7 3 Only if protection is not installed e g for the very first installation of protection read write protection need not be disabled After writing the correct protection confirmation code in the respective user configuration page the p...

Page 371: ...r Command Cycle No PFLASH DFLASH Sec tor Address Data Bank Address Data Cycle 1 PSx1 1 x is the number of the PFLASH sector PSx that is defined in Table 7 1 x 0 12 A000 5554H XXXX XXAAH DB0 AFE0 5554H XXXX XXAAH PPS0 DB1 AFE1 5554H PPS1 Cycle 2 PSx1 A000 AAA8H XXXX XX55H DB0 AFE0 AAA8H XXXX XX55H PPS0 DB1 AFE1 AAA8H PPS1 Cycle 3 PSx1 A000 5554H XXXX XX80H DB0 AFE0 5554H XXXX XX80H PPS0 DB1 AFE1 55...

Page 372: ...r programmed A read access to a busy erasing or programming Flash bank is allowed but delayed until the corresponding Flash bank is no longer busy Note that in this case the read path PLMB is completely locked Therefore reading from a Flash bank in erase or program state should be avoided by first polling the busy flags in the FSR register If the Erase Sector operation is used to erase a physical ...

Page 373: ...sabled when the Erase User Configuration Block command is received the protection error flag FSR PROER is set the Command Mode is not entered and the erase operation is not started After a Erase User Configuration Block command a new protection configuration including keywords and protection confirmation code can be written to the pages of the user configuration block But note that the user config...

Page 374: ...or both passwords are not identical to their related keywords the sectors remain protected and the protection error flag FSR PROER is set In this case a new Disable Write Protection command is only accepted after the next reset operation After the correct execution of the Disable Write Protection command all protected sectors as defined for UCB0 or UCB1 are unlocked if no read protection is additi...

Page 375: ...ration After the correct execution of this command the PFLASH and both DFLASH banks are temporarily unlocked and flag FSR RPRODIS is set Read erase and write operations to all unlocked not separately write protected sectors are now possible until A Resume Protection command is executed or The next reset operation hardware or software reset is executed 7 2 5 10 Resume Protection Command With the on...

Page 376: ...egister FSR Error flags PFOPER DFOPER SQER PROER PFSBER DFSBER PFDBER and DFDBER Status flags PROG ERASE The one cycle Clear Status command is accepted only in Read Mode Otherwise a command sequence error occurs FSR SQER is set Read Mode is entered if Flash is not busy and after every error detection and indication change in FSR Table 7 15 Clear Status Command Cycle No Address Data Cycle 1 A000 55...

Page 377: ...ion is held as a mirror memory in an on chip RAM area After a reset operation the active EEPROM region is copied into the RAM and the related 16 Kbyte region may be marked e g with all one programming of a page to be invalid Now the next consecutive 16 Kbyte region within the DFLASH circular buffer becomes the active EEPROM region After the copy event the user program is able to read write data fr...

Page 378: ...able to install sector OTP write protection for the PFLASH sectors OTP write protected sectors are locked for ever and are never re programmable If read or write protection is installed and activated once changing the read write protection configuration parameters in the UCBs is password protected and can only be executed if the passwords are known Note If any PFLASH sector is locked for ever OTP ...

Page 379: ...confirmation code 8AFE15C3H A000 0208H 11 8 Copy of 32 bit confirmation code others Must be programmed to 00H UCP3 all This page is reserved for future purposes must be programmed to 00H UCB1 UCP4 A000 0400H 1 0 Protection configuration bits content as defined for PROCON1 A000 0408H 9 8 Copy of bytes 1 0 A000 0410H 19 16 First 32 bit keyword of user 1 A000 0414H 23 20 Second 32 bit keyword of user...

Page 380: ...CB must be programmed with 00H 2 Confirmation of the Keywords The 32 bit confirmation code word which is located in the third page of a UCB should be programmed only after a check of the correct programming of the two 32 bit keywords Reason wrong keywords in a UCB can never be retrieved because UCBs are not readable and a confirmed read or write protection cannot be disabled and changed anymore wh...

Page 381: ...tive 7 2 7 2 Write and OTP Protection for PFLASH Write protection is a feature that must be installed by the user of the TC1796 device In the delivery state of the TC1796 no write protection is installed meaning that the UCBs are in erased state If sector write protection is active for a PFLASH sector erasing and programming of this sector is only possible if the corresponding UCB keywords are kno...

Page 382: ...x or not Status flag FSR PROIN 1 this bit is set coincidently with FSR WPROINx Status flags SnL n 0 12 in the three Protection Configuration registers PROCONx x 0 2 that indicate which Flash sectors are write protected by UCBx The state of a write protection enabled or temporarily disabled is indicated by bits FSR WPRODIS0 for UCB0 and FSR WPRODIS1 for UCB1 After the execution of an Erase User Con...

Page 383: ...protection configuration as defined in UCB0 can be changed after erasing UCB0 if not coincidently sector write protection is installed by the user 0 in this case also sector write protection must be disabled A temporarily disabled read protection can be re enabled by sending the Resume Protection command or by executing a reset operation Read protection can be combined with sector specific write p...

Page 384: ...y with FCON register bits DDFDBG DDFDMA and DDFPCP of register FCON When such a bit is set the corresponding bus master Debug system DMA controller or PCP is not allowed to access PFLASH or DFLASH memory When these bits are set once they can only be cleared again when read protection is not selected at all inactive or temporarily disabled Note The debug interface is disabled after Boot ROM exit wi...

Page 385: ... programmed with a 1 In general the TC1796 Flash module supports the following error detection and correction functionality for PFLASH and DFLASH read accesses Single bit error detection within 64 bit read data with on the fly correction Status flag indication for PFLASH FSR PFSBER and DFLASH FSR DFSBER single bit errors Optional single bit error Flash interrupt generation for PFLASH and DFLASH Do...

Page 386: ...00B standard margin selected 2 Reading related Flash memory locations while observing the single bit and double bit Flash interrupts if an error occurs executing an erase and reprogramming of the corresponding sector A zero check analogous procedure as shown in steps 1 and 2 for programmed cells is normally not necessary because the energetically stabilized state of Flash cells is close to the zer...

Page 387: ...ecomes active whenever a programming or erasing operation is finished At this event one of the three FSR busy flags PBUSY D0BUSY or D1BUSY is cleared from 1 to 0 End of busy interrupts are enabled by setting the FCON EOBM bit The error flags in the Flash Status Register are controlled independently of the interrupt configuration as defined in the FCON register Thus they may be polled without inter...

Page 388: ...Conditions EOBM FCON FSR PBUSY FSR D0BUSY FSR D1BUSY Edge Detection Command Sequence Error Protection Error DFLASH Single Bit Error PFLASH Single Bit Error SQERM FCON PROERM FSR SQER PROER DFSBERM FCON PFSBERM FSR DFSBER PFSBER DFLASH Double Bit Error PFLASH Double Bit Error DFDBERM FCON PFDBERM FSR DFDBER PFDBER FLASH Interrupt Set Set Set Set Set Set 1 ...

Page 389: ...e ramped down and the Flash array oscillator is switched off Next status flag FSR SLM is set indicating an active Flash sleep mode Flash sleep mode can be initiated by software separately from the other modules in the TC1796 by setting bit FCON SLEEP Flash sleep mode can also be initiated by hardware when the sleep mode is initiated by the power management system of the TC1796 see Section 5 1 on P...

Page 390: ...ithin 900 µsec including Flash ramp up after every reset represented by the system reset When that happens any erase or programming operation that is running is aborted and the Flash might have erroneous data in the location being operated on thus the aborted operation must be repeated Such an aborted state can be detected by careful handling of the PROG and ERASE flags in FSR Note The startup tim...

Page 391: ...lash Module Identification Register 1008H Page 7 41 FLASH_FSR Flash Status Register 1010H Page 7 43 FLASH_FCON Flash Configuration Register 1014H Page 7 53 FLASH_MARP Flash Margin Control Register PFLASH 1018H Page 7 51 FLASH_MARD Flash Margin Control Register DFLASH 101CH Page 7 52 FLASH_PROCON0 Flash Protection Config Reg User 0 1020H Page 7 59 FLASH_PROCON1 Flash Protection Config Reg User 1 10...

Page 392: ... name FLASH_ 2 This register is located in the address range for the DMA controller FLASH_ID FLASH Module Identification Register 1008H Reset Value 0031 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type Thi...

Page 393: ...ter 08H Reset Value 002E C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module ident...

Page 394: ...Y P BU SY rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description PBUSY 0 rh PFLASH Busy This flag indicates the busy state of the PFLASH during program or erase operations It also indicates when the PFLASH is not in Read Mode e g in ramp up state PBUSY is cleared by any reset operation 0B PFLASH is ready and in Read Mode default after reset 1B PFLASH is busy program erase ramp...

Page 395: ... during program or erase operations It also indicates when the DFLASH bank 1 is not in Read Mode e g in ramp up state D0BUSY is cleared by any reset operation 0B DFLASH bank 1 is ready and in Read Mode default after reset 1B DFLASH bank 1 is busy program erase ramp up or sleep mode and it is not in Read Mode PROG 4 rh Programming State This flag indicates whether PFLASH or DFLASH is currently prog...

Page 396: ...and or by any reset operation 0B PFLASH is not in Page Mode default after reset 1B PFLASH is in Page Mode The page assembly buffer of the PFLASH is ready to be filled DFPAGE 7 rh DFLASH in Page Mode This flag indicates whether the DFLASH is in Page Mode or not It is set with the enter Page Mode command and cleared by a write Page Mode command or by a Reset to Read command or by any reset operation...

Page 397: ...n invalid command sequence has been detected command is not executed PROER 11 rh Protection Error This flag indicates a protection error Such an error is a command that is not allowed for example an erase sector or write page command addressing a locked sector It also indicates when wrong passwords are used in disable read or disable write protection commands PROER is cleared by a Reset to Read co...

Page 398: ...ad command or by a Clear Status command or by any reset operation 0B No error has been detected default after reset 1B A double bit error in PFLASH has been detected DFDBER 15 rh DFLASH Double Bit Error This flag indicates the occurrence of a double bit error in the DFLASH DFDBER is cleared by a Reset to Read command or by a Clear Status command or by any reset operation 0B No error has been detec...

Page 399: ...nd global write protection is temporarily disabled External Flash read as well as programming or erase on not separately write protected sectors is possible WPROIN0 21 rh UCB0 Write Protection Installed This flag indicates whether sector write protection in UCB0 is correctly installed and confirmed This bit is updated only if a modified UCB0 protection installation is detected at a reset operation...

Page 400: ...are temporarily unlocked The programming or erasing of UCB0 is possible if no read protection is installed Hierarchical protection levels Unlock state of user level zero also includes sectors that are protected by user 1 WPRODIS1 26 rh UCB1 Write Protection Disabled This flag indicates whether PFLASH sectors that are write protected by UCB1 are temporarily unlocked WPRODIS1 is cleared by any reset...

Page 401: ... operation and by the Clear Status command 0B A Flash page is correctly programmed All programmed 1 bits have a full quality 1B A Flash page programming verify error has been detected A correction of weak bits by the programming algorithm was unsuccessful during the last programming operation Note There is no interrupt generated when VER is set 0 17 20 24 27 30 29 r Reserved Read as 0 Field Bits T...

Page 402: ...Description MARGIN0 1 0 rw PFLASH Margin Selection for Low Level 00B Standard margin selected 01B High margin for 0 low level selected 10B Reserved 11B Reserved MARGIN1 3 2 rw PFLASH Margin Selection for High Level 00B Standard margin selected 01B High margin for 1 high level selected 10B Reserved 11B Reserved TRAPDIS 15 rw PFLASH Double Bit Error LMB Bus Error Disable 0B If a double bit error occ...

Page 403: ...w level selected 10B Reserved 11B Reserved MARGIN1 3 2 rw DFLASH Margin Selection for High Level 00B Standard margin selected 01B High margin for 1 high level selected 10B Reserved 11B Reserved BNKSEL 4 rw DFLASH Bank Selection 0B DFLASH bank 0 selected for margin control 1B DFLASH bank 1 selected for margin control TRAPDIS 15 rw DFLASH Double Bit Error DLMB Bus Error Disable 0B If a double bit er...

Page 404: ...egister 1014H Reset Value 000X 0636H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EOB M DF DB ERM PF DB ERM DF SB ERM PF SB ERM PRO ERM SQ ERM 0 DDF PCP DDF DMA DDF DBG DDF DCF RPA rw rw rw rw rw rw rw r rw rw rw rwh rwh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SL EEP ESL DIS 0 WS EC DF WS DFLASH 0 WS WLHIT WS EC PF WS PFLASH rw rw r rw rw r rw rw rw Field Bits Type Description WSPFLASH1 2 0 rw...

Page 405: ...y as the last PFLASH access 000B Reserved 001B Flash read hit access in one clock cycle 010B Hit access in 2 clock cycles 011B Hit access in 3 clock cycles default after reset 100B Hit access in 4 clock cycles 101B Flash access in 5 clock cycles 110B Flash access in 6 clock cycles default after Boot ROM exit see Table 4 4 on Page 4 19 111B Reserved WSDFLASH1 10 8 rw Wait States for DFLASH Read Acc...

Page 406: ...uest the Flash sleep mode The external sleep mode is controlled and requested by the Power Management System of the SCU SLEEP 15 rw Flash Sleep Mode Control This bit controls the Flash sleep mode of the Flash module 0B Normal Flash mode or wake up mode is active 1B Flash sleep mode is selected Flash sleep mode is left wake up from sleep by clearing the SLEEP bit RPA 16 rh Read Protection Activated...

Page 407: ...the data read access from the PFLASH and DFLASH memory when read protection is active Once set this bit can only be cleared when read protection is inactive RPA 0 DDF is automatically set after a reset operation It is cleared by hardware in case of internal program start out of the PFLASH 0B Data read access to PFLASH and DFLASH is allowed 1B Data read access to PFLASH and DFLASH is not allowed DD...

Page 408: ...d 1B Data read accesses from PFLASH DFLASH initiated by the PCP are disabled SQERM 25 rw Command Sequence Error Interrupt Mask This bit disables enables the command sequence error interrupt 0B Command sequence error interrupt is disabled 1B Command sequence error interrupt is enabled PROERM 26 rw Protection Error Interrupt Mask This bit disables enables the protection error interrupt 0B Protection...

Page 409: ... enables the DFLASH double bit error interrupt 0B DFLASH single bit error interrupt is disabled 1B DFLASH single bit error interrupt is enabled EOBM 31 rw End of Busy Interrupt Mask This bit enables the end of busy interrupt 0B End of busy interrupt is disabled 1B End of busy interrupt is enabled 0 7 13 12 24 22 r Reserved Read as 0 should be written with 0 1 These bits and bit fields can be chang...

Page 410: ...20H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PRO 0 S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L rh r rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description SnL n 0 12 n rh Sector Locked for Write Protection by User 0 These bits indicate whether PFLASH sector PSn is write protected by user 0 or not 0B No...

Page 411: ...17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L r rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description SnL n 0 12 n rh Sector Locked for Write Protection by User 1 These bits indicate whether sector n is write protected by user 1 or not 0B No write protection installed for sector n 1B Write protection installed for sector n 0 3...

Page 412: ...s initiated by a SPB master e g PCP or DMA additionally a SPB error is generated Write accesses to the emulation memory region by any master causes a PLMB bus error FLASH_PROCON2 Flash Protection Configuration Register User 2 1028H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 S12L S11L S10L S9L S8L S7L S6L S5L S4L S3L S2L S1L S0...

Page 413: ...at makes it possible to redirect data accesses to the PMU based memories into the DMU or emulation memory Figure 8 1 Block Diagram of the Data Memory Unit DMU Note DMU memories cannot be accessed by the PCP using burst transfers BCOPY instruction DMU MCB05648 DMU Control Overlay Address Generation Control SRAM 64 KB SBRAM 16 KB To From Data Local Memory Bus DLMB Interface Slave Master To Program L...

Page 414: ...echanism is controlled by the Stand by SRAM Control Register SBRCTR When writing a dedicated pattern into bit fields STBULK and STBSLK the SBRAM will be locked A status flag STBLOCK indicates whether the SBRAM is locked or not To unlock the SBRAM register SBRCTR must be written by three consecutive write operations for a detailed description see Page 8 12 If an access to the SBRAM is performed whi...

Page 415: ...ly initialized by a user program that writes every memory location of it once More details about the parity control for on chip memories are described in Section 5 5 on Page 5 37 8 5 Data Access Overlay Functionality The DMU overlay functionality provides the capability to redirect data read accesses from internal or external code memory to data accesses from the DMU SRAM This functionality makes ...

Page 416: ...k sizes are supported and can be individually enabled for overlay functionality The block size of each overlay memory block can be in the range of 2 bytes up to 512 bytes Attention In the TC1796ED emulation device it is possible in addition to redirect code memory data accesses to the emulation memory of the TC1796ED Code Fetch unaffected MCA05649 Data Read Write Redirect Target Address OTARx Inte...

Page 417: ...ion to control the overlay functionality The overlay target address in the Overlay Target Address Register OTARx which determines the base address of the code memory data block x to be redirected The base address of the overlay memory block in the DMU SRAM in the Redirected Address Base Register RABRx A mask in the Overlay Mask Register OMASKx defining the size of the block the address bits to che...

Page 418: ...rlay block base address bits bits OBASE in RABRx where the corresponding mask bits OMASK in registers OMASKx are set to 1 The address is completed by the original offset into the block the number of bits used are determined by the bits set to 0 in the mask OMASK Minimum Block Sizes for DLMB Transactions The overlay functionality provides the possibility to redirect data accesses with block sizes o...

Page 419: ...ing between Internal and Emulation Memory Overlay When switching a region between internal and external overlay it has to be ensured that the respective OVEN bit is cleared all region parameters are set properly and then the region is enabled again Other wise unintended access re directions may occur 8 5 4 Region Priority If concurrent matches in more than one region occur the region with the lowe...

Page 420: ... possible to cache one line of 16 bytes 128 bits of data read from specific memory areas on PMU side Read Transactions When the first read access to cachable memory areas is done the LMI initiates a 2 beat burst access on PLMB requesting 128 bit of data The start address for the burst is generated by setting the last 4 bits of the address to 0 Cachable memory regions for data accesses are Segment ...

Page 421: ...actions When a write transaction hits into the read buffer the buffer content is invalidated This feature also can be used to flush the buffer contents Read Modify Write Transactions Read modify write transaction always will be forwarded to the PLMB They will not effect the buffer content at all no caching no invalidation This implies that read modify write operations should be done to non cached ...

Page 422: ...801 0100H F801 01FFH Table 8 2 Registers Overview PMU Overlay Control Registers Register1 Short Name 1 The PMU register short names are extended and referenced in the other parts of the TC1796 User s Manual with the module name prefix PMU_ Register Long Name Offset Address Description see ID Module Identification Register 0008H Page 8 11 RABRx Redirected Address Base Register x x 0 15 0020H x CH P...

Page 423: ...Reset Value 002D C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module identificatio...

Page 424: ...ck Flag In order to unlock the SBRAM three consecutive write cycles must be written into STBULK with the following pattern 1 Write STBULK 001B 2 Write STBULK 011B 3 Write STBULK 111B During the three consecutive write operations STBSLK must be written with 0000B If any bit of STBSLK is set when writing a non zero pattern to STBULK this is treated as invalid pattern and the SBRAM will not be unlock...

Page 425: ... the offset address and which bits are part of the base address 0 31 8 r Reserved Read as 0 should be written with 0 RABRx x 0 15 Redirected Address Base Register x 20H x CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OV EN IEMS 0 RC1 RC0 0 rw r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OBASE 0 rw r Field Bits Type Description OBASE 15 1 rw Overlay Base Address This bi...

Page 426: ... bytes n 1 9 Segment address bits 31 28 are set to 1100B Note In an TC1796ED emulation device this bit can be written too When set an emulation memory is selected as overlay memory not applicable in the TC1796 OVEN 31 rw Overlay Enabled This bit controls whether or not the overlay function of overlay block x is enabled 0B Overlay function of block x is disabled 1B Overlay function of block x is en...

Page 427: ... r Field Bits Type Description TBASE 27 1 rw Target Base Holds the base address of the overlay memory block in the target memory If IEMS is set bits 9 1 will be forced to 0 and cannot be modified TSEG 31 28 rw Target Segment reserved This bit field is reserved for future use to select a segment In TC1796 implementation any access to segments 8H or AH will be checked for a valid base address return...

Page 428: ...determines which address bits will participate in the address compare for a block base address and which bits are used from the original target address and which bits are taken from RABRx OBASE OMASKx x 0 15 Overlay Mask Register x 20H x CH 8H Reset Value 0FFF FE00H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 OMASK 0 r rw r ...

Page 429: ...ponding address bits are not used in the address comparison Corresponding final address bits are derived from the original address Block size is 2n bytes n number of trailing zeros in the register 1B Corresponding address bits are used in the address comparison Corresponding final address bits are derived from RABR_OBASE Block size is 2n bytes n number of trailing zeros in the register All OMASK b...

Page 430: ...ues Corresponding address bits are not used in the address comparison Corresponding final address bits are taken from the original address 1 27 9 r Fixed Values Corresponding address bits are participating in the address comparison Corresponding final address bits are taken from RABR Field Bits Type Description ...

Page 431: ...DMI 56 Kbyte of Local Data RAM LDRAM 8 Kbyte of Dual Port RAM DPRAM PCP memory 32 Kbyte of PCP Code Memory CMEM 16 Kbyte of PCP Data Memory PRAM Furthermore the TC1796 has four on chip buses System Peripheral Bus SPB Remote Peripheral Bus RPB Program Local Memory Bus PLMB Data Local Memory Bus DLMB 9 1 How to Read the Address Maps The bus specific address maps describe how the different bus master...

Page 432: ...ET A bus access is terminated with a bus error on the PLMB and a DSE trap read access or DAE trap write access DLMBBE A bus access is terminated with a bus error on the DLMB DLMBBET A bus access is terminated with a bus error on the DLMB and a DSE trap read access or DAE trap write access EBUBET If the requested address is configured by the EBU registers and exist externally the access is executed...

Page 433: ...cesses are permitted to that register address range nE A bus access generates no bus error although the bus access points to an undefined address or address range This is valid e g for CPU accesses MTCR MFCR to undefined addresses in the CSFR range Table 9 1 Definition of Acronyms and Terms cont d Term Description ...

Page 434: ...m the SPB point of view PCP DMA and Cerberus this memory segment allows accesses to all PMU memories PFLASH DFLASH BROM and TROM and the external EBU space From the CPU point of view PMI and DMI this memory segment allows non cached accesses to all PMU memories PFLASH DFLASH BROM and TROM and the external EBU space Segment 11 This memory segment is reserved in the TC1796 comparable to segment 9 Se...

Page 435: ... DPRAM Segment 14 From the SPB point of view PCP DMA and Cerberus this memory segment allows accesses to the external peripheral space the PMU data memory SRAM the DMI memories LDRAM and DPRAM and the PMI scratch pad memory SPRAM From the CPU point of view PMI and DMI this memory segment allows non cached accesses to the external peripheral space Segment 15 From the SPB point of view PCP DMA and C...

Page 436: ...rap 0000 0008H 7FFF FFFFH 8 256 Mbyte SPBBE SPBBE 8 8000 0000H 801F FFFFH 2 Mbyte Program Flash PFLASH access access1 8020 0000H 807F FFFFH 6 Mbyte Reserved PLMBBE DLMBBE SPBBE PLMBBE 8080 0000H 8FDF FFFFH 246 Mbyte External EBU space EBU access EBU access 8FE0 0000H 8FE1 FFFFH 128 Kbyte Data Flash DFLASH access access1 8FE2 0000H 8FEF FFFFH 896 Kbyte Reserved PLMBBE DLMBBE SPBBE PLMBBE 8FF0 0000H...

Page 437: ...BBE AFF0 0000H AFF7 FFFFH 512 Kbyte Reserved for TC1796 emulation device memory AFF8 0000H AFFF BFFFH 496 Kbyte Reserved AFFF C000H AFFF DFFFH 8 Kbyte Boot ROM BROM access AFFF E000H AFFF FFFFH 8 Kbyte Test ROM TROM 11 B000 0000H BFFF FFFFH 256 Mbyte Reserved SPBBE SPBBE 12 C000 0000H C000 FFFFH 64 Kbyte DMU data memory SRAM SPBBE SPBBE C001 0000H C03F BFFFH 3 92 Mbyte Reserved SPBBE SPBBE C03F C0...

Page 438: ... BFFFH 48 Kbyte PMI Scratch Pad RAM SPRAM D400 C000H D7FF FFFFH 64 Mbyte Reserved D800 0000H DDFF FFFFH 96 Mbyte External Peripheral Space compare compare DE00 0000H DEFF FFFFH 16 Mbyte External Emulator Space DF00 0000H DFFF BFFFH 16 Mbyte Reserved SPBBE SPBBE DFFF C000H DFFF DFFFH 8 Kbyte Boot ROM BROM DFFF E000H DFFF FFFFH 8 Kbyte Test ROM TROM Table 9 2 SPB RPB Address Map of Segment 0 to 14 c...

Page 439: ... RAM LDRAM access access E840 E000H E840 FFFFH 8 Kbyte DMI Dual Port RAM DPRAM E841 0000H E84F FFFFH 1 Mbyte Reserved DLMBBE SPBBE DLMBBE E850 0000H E850 BFFFH 48 Kbyte PMI Scratch Pad SRAM SPRAM access access E850 C000H E87F FFFFH 3 Mbyte Reserved DLMBBE SPBBE PLMBBE E880 C000H EFFF FFFFH 120 Mbyte Reserved SPBBE PLMBBE 15 F000 0000H FFFF FFFFH 256 Mbyte see Table 9 3 1 Only applicable when writi...

Page 440: ... 00FFH 256 byte access access System Peripheral Bus Control Unit SBCU F000 0100H F000 01FFH 256 byte access access System Timer STM F000 0200H F000 02FFH 256 byte access access Reserved F000 0300H F000 03FFH SPBBE SPBBE On Chip Debug Support Cerberus F000 0400H F000 04FFH 256 byte access access Reserved F000 0500H F000 07FFH SPBBE SPBBE MicroSecond Bus Controller 0 MSC0 F000 0800H F000 08FFH 256 b...

Page 441: ...0 F000 1600H F000 16FFH 256 byte access access Reserved F000 1700H F000 17FFH SPBBE SPBBE General Purpose Timer Array 0 GPTA0 F000 1800H F000 1FFFH 8 256 byte access access General Purpose Timer Array 1 GPTA1 F000 2000H F000 27FFH 8 256 byte access access Local Timer Cell Array 2 LTCA2 F000 2800H F000 2FFFH 8 256 byte access access Reserved F000 3000H F000 3BFFH SPBBE SPBBE Direct Memory Access Co...

Page 442: ...BBE SPBBE Reserved F008 0000H F00F FFFFH SPBBE SPBBE Remote Peripheral Bus Control Unit RBCU F010 0000H F010 00FFH 256 byte access access Synchronous Serial Interface 0 SSC0 F010 0100H F010 01FFH 256 byte access access Synchronous Serial Interface 1 SSC1 F010 0200H F010 02FFH 256 byte access access Fast Analog to Digital Converter FADC F010 0300H F010 03FFH 256 byte access access Analog to Digital...

Page 443: ...ows F01E 8000H F01E FFFFH 4 8 Kbyte access access Reserved F01F 0000H F01F FFFFH SPBBE SPBBE MLI0 Large Transfer Windows F020 0000H F023FFFFH 4 64 Kbyte access access MLI1 Large Transfer Windows F024 0000H F027 FFFFH 4 64 Kbyte access access Reserved F028 0000H F7E0 FEFFH SPBBE SPBBE CPU CPU Slave Interface Registers CPS F7E0 FF00H F7E0 FFFFH 256 byte access access CPU Core SFRs GPRs F7E1 0000H F7...

Page 444: ...FFH DLMBBE SPBBE DLMBBE Data Local Memory Bus Control Unit DBCU F87F FA00H F87F FAFFH 256 byte access access Reserved F87F FB00H F87F FBFFH DLMBBE SPBBE DLMBBE CPU DMI Registers F87F FC00H F87F FCFFH 256 byte access access PMI Registers F87F FD00H F87F FDFFH 256 byte access access Program Local Memory Bus Control Unit PBCU F87F FE00H F87F FEFFH 256 byte access access LFI Bridge F87F FF00H F87F FFF...

Page 445: ...6 Mbyte PLMBBET PLMBBET 81 8000 0000H 801F FFFFH 2 Mbyte Program Flash PFLASH access access2 8020 0000H 807F FFFFH 6 Mbyte Reserved PLMBBET PLMBBET 8080 0000H 8FDF FFFFH 246 Mbyte External EBU Space EBU access EBU access 8FE0 0000H 8FE1 FFFFH 128 Kbyte Data Flash DFLASH PLMBBET access2 8FE2 0000H 8FEF FFFFH 896 Kbyte Reserved PLMBBET PLMBBET 8FF0 0000H 8FF7 FFFFH 512 Kbyte Reserved for TC1796 emul...

Page 446: ... PLMBBET access2 AFE2 0000H AFEF FFFFH 896 Kbyte Reserved PLMBBET PLMBBET AFF0 0000H AFF7 FFFFH 512 Kbyte Reserved for TC1796 emulation device memory access access AFF8 0000H AFFF BFFFH 496 Kbyte Reserved PLMBBET PLMBBET AFFF C000H AFFF DFFFH 8 Kbyte Boot ROM BROM access AFFF E000H AFFF FFFFH 8 Kbyte Test ROM TROM 113 B000 0000H BFFF FFFFH 256 Mbyte Reserved PLMBBET PLMBBET 121 C000 0000H CFFF FFF...

Page 447: ... 64 Mbyte Reserved PLMBBET PLMBBET D800 0000H DDFF FFFFH 96 Mbyte External Peripheral Space EBU access EBU access DE00 0000H DEFF FFFFH 16 Mbyte External Emulator Space DF00 0000H DFFF BFFFH 16 Mbyte Reserved PLMBBET PLMBBET DFFF C000H DFFF DFFFH 8 Kbyte Boot ROM BROM access PLMBBET DFFF E000H DFFF FFFFH 8 Kbyte Test ROM TROM 143 E000 0000H E7FF FFFFH 128 Mbyte External Peripheral Space EBU access...

Page 448: ...am Memory Unit PMU access access F800 0600H F800 0FFFH 2 Kbyte Reserved PLMBBET PLMBBET F800 1000H F800 23FFH 5 Kbyte Reserved Flash Registers ignore ignore F800 2400H F87F FCFFH 8 Mbyte Reserved PLMBBET PLMBBET F87F FD00H F87F FFFFH 768 byte Reserved PMI PBCU and LFI ignore ignore F880 0000H FFFF FFFFH 119 Mbyte Reserved PLMBBET PLMBBET 1 Cached area 2 Only applicable when writing Flash command s...

Page 449: ... DLMBBET SPBBET SPBBE 81 8000 0000H 801F FFFFH 2 Mbyte Program Flash PFLASH access access2 8020 0000H 807F FFFFH 6 Mbyte Reserved PLMBBET DLMBBET PLMBBE 8080 0000H 8FDF FFFFH 246 Mbyte External EBU space EBU access EBU access 8FE0 0000H 8FE1 FFFFH 128 Kbyte Data Flash DFLASH access access2 8FE2 0000H 8FEF FFFFH 896 Kbyte Reserved PLMBBET DLMBBET PLMBBE 8FF0 0000H 8FF7 FFFFH 512 Kbyte Reserved for ...

Page 450: ... 0000H AFF7 FFFFH 512 Kbyte Reserved for TC1796 emulation device memory AFF8 0000H AFFF BFFFH 496 Kbyte Reserved AFFF C000H AFFF DFFFH 8 Kbyte Boot ROM BROM access AFFF E000H AFFF FFFFH 8 Kbyte Test ROM TROM 113 B000 0000H BFFF FFFFH 256 Mbyte Reserved DLMBBET SPBBET SPBBE 121 C000 0000H C000 FFFFH 64 Kbyte DMU data memory SRAM access access C001 0000H C03F BFFFH 3 92 Mbyte Reserved DLMBBET DLMBBE...

Page 451: ...00H DEFF FFFFH 16 Mbyte External Emulator Space EBU access EBU access DF00 0000H DFFF BFFFH 16 Mbyte Reserved DLMBBET SPEBET SPEBE DFFF C000H DFFF DFFFH 8 Kbyte Boot ROM BROM DFFF E000H DFFF FFFFH 8 Kbyte Test ROM TROM 143 E000 0000H E7FF FFFFH 128 Mbyte External Peripheral Space EBU access EBU access E800 0000H EFFF FFFFH 128 Mbyte Reserved DLMBBE DLMBBE 153 F000 0000H FFFF FFFFH 256 Mbyte Addres...

Page 452: ...y Module Access Restrictions Table 9 6 describes which type of accesses are possible to the different memories in the TC1796 Table 9 6 Possible Memory Accesses Memory Bit Byte Half word Word Double word rmw r w r w r w r w PMI SPRAM DMI LDRAM DPRAM PMU ROM PFLASH DFLASH DMU SRAM SBRAM PCP CMEM PRAM ...

Page 453: ...ut output lines without GPIO functionality are provided The External Bus Interface EBU has its own set of dedicated signal lines Figure 10 1 is an overview of the I O lines with its general port to peripheral unit assignments Further details are described in the port specific sections of this chapter Figure 10 1 Peripheral GPIO Lines of the TC1796 MCA05652 Alternate Functions TC1796 Port 0 Port 1 ...

Page 454: ...eral Structure of a Port Pin MCA05653 Pull up Pull down Control ALT1 MUX Select Pin Schmitt Trigger AltDataIn System Peripheral Bus SPB Pn_OMR Output Modification Reg Pn_ESR Emergency Stop Register Pn_IOCR Input Output Control Register Pn_OUT Data Output Register ALT2 ALT3 EMSTOP MUX Control TC 1 0 Pn_IN Data Input Register Output Driver Pad Control Logic Pull Devices Only available for GPTA lines...

Page 455: ...ional advantages in an application The output multiplexer in front of the output driver selects the signal source for the GPIO line when used as output If the pin is used as general purpose output the multiplexer is switched by software Pn_IOCR register to the Output Data Register Pn_OUT Software can set or clear the bit in Pn_OUT and therefore it can directly influence the state of the port pin I...

Page 456: ...all high speed class A2 outputs at GPIO ports and all EBU output lines All GPIO lines of the TC1796 that are used by the GPTA modules GPTA0 GPTA1 LTCA2 have an emergency stop logic This logic makes it possible to individually disconnect GPTA outputs from the driving GPTA module outputs and to put them onto a well defined logic state in an emergency case In en emergency case the content of the port...

Page 457: ... the registers in the specific ports is described in Table 10 6 on Page 10 19 up to Table 10 25 on Page 10 76 Port Register Overview Figure 10 3 Port Registers Note The complete address map of the GPIO ports is described in the Chapter 18 Register Overview of this TC1796 System Units Vol 1 of 2 User s Manual Table 10 1 Registers Address Space Module Base Address End Address Note P0 F000 0C00H F000...

Page 458: ...OMR Port n Output Modification Register 04H Page 10 14 Pn_IOCR0 Port n Input Output Control Register 0 10H Page 10 7 Pn_IOCR4 Port n Input Output Control Register 4 14H Page 10 8 Pn_IOCR8 Port n Input Output Control Register 8 18H Page 10 8 Pn_IOCR12 Port n Input Output Control Register 12 1CH Page 10 9 Pn_IN Port n Input Register 24H Page 10 17 Pn_PDR Port n Pad Driver Mode Register 40H Page 10 1...

Page 459: ...ontrols the Pn 3 0 port lines Register Pn_IOCR4 controls the Pn 7 4 port lines Register Pn_IOCR8 controls the Pn 11 8 port lines Register Pn_IOCR12 controls the Pn 15 12 port lines The diagrams below show the register layouts of the port input output control registers with the PCx bit fields One PCx bit field controls exactly one port line Pn x Pn_IOCR0 Port n Input Output Control Register 0 10H R...

Page 460: ...termines the Port n line x functionality x 4 7 according to the coding table see Table 10 3 0 3 0 11 8 19 16 27 24 r Reserved Read as 0 should be written with 0 Pn_IOCR8 Port n Input Output Control Register 8 18H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC11 0 PC10 0 PC9 0 PC8 0 rw r rw r rw r rw r Field Bits Type Description PC8 PC9 PC10 PC11 7 4 15 12 23 20 31 28 rw Port...

Page 461: ...to configure the port pin functionality of a single pin with byte oriented accesses without accessing the other PCx bit fields Pn_IOCR12 Port n Input Output Control Register 12 1CH Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC15 0 PC14 0 PC13 0 PC12 0 rw r rw r rw r rw r Field Bits Type Description PC12 PC13 PC14 PC15 7 4 15 12 23 20 31 28 rw Port Control for Port n Pin 12 t...

Page 462: ...VTTL outputs Class A2 pins high speed 3 3V LVTTL outputs e g for serial outputs The assignment of each port pin to one of these pad classes is shown in the port configuration figures Figure 10 4 to Figure 10 13 Further details about pad driver classes that are available in the TC1796 are summarized in Table 1 5 on Page 1 57 Table 10 3 PCx Coding except Port 4 PCx 3 0 I O Output Characteristics Sel...

Page 463: ...ds In addition to the pad driver mode register control selections a temperature compensation logic which is a part of the system control unit SCU makes it possible to adjust the edges of the high speed class A2 GPIO output lines depending on the die temperature The temperature compensation logic affects all class A2 GPIO output lines that are used simultaneously as output The fully programmable te...

Page 464: ...es depending on the die temperature The temperature compensation logic affects all class A2 GPIO output lines that are used simultaneously as output The fully programmable temperature compensation logic provides four types of output driver levels Maximum level low temperature High level Low level Minimum level high temperature P0_PDR Port 0 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30...

Page 465: ...the port output modification register Pn_OMR Note Only Port 0 1 3 and 4 are 16 bit wide ports The Pn_OUT registers of the other ports have a reduced number of Px bits see Pn_OUT register descriptions in the corresponding port sections Pn_OUT Port n Output Register 00H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P1...

Page 466: ...lways be written using word accesses Pn_OMR Port n Output Modification Register 04H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PR 15 PR 14 PR 13 PR 12 PR 11 PR 10 PR 9 PR 8 PR 7 PR 6 PR 5 PR 4 PR 3 PR 2 PR 1 PR 0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PS 15 PS 14 PS 13 PS 12 PS 11 PS 10 PS 9 PS 8 PS 7 PS 6 PS 5 PS 4 PS 3 PS 2 PS 1 PS 0 w w...

Page 467: ... Ports and Peripheral I O Lines User s Manual 10 15 V2 0 2007 07 Ports V2 0 Table 10 5 Function of the Bits PRx and PSx PRx PSx Function 0 0 Bit Pn_OUT Px is not changed 0 1 Bit Pn_OUT Px is set 1 0 Bit Pn_OUT Px is cleared 1 1 Bit Pn_OUT Px is toggled ...

Page 468: ...ed from the GPTA module alternate function and connected to the corresponding bit of the Pn_OUT output register the content of the corresponding PCx bit fields in register Pn_IOCR is discarded Pn_ESR Port n Emergency Stop Register 50H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN 15 EN 14 EN 13 EN 12 EN 11 EN 10 EN 9 EN 8 EN 7 E...

Page 469: ... in Pn_IN independently whether the GPIO pin is selected as input or output Note Only Port 0 1 3 and 4 are 16 bit wide ports The Pn_IN registers of the other ports have a reduced number of Px bits see Pn_IN register descriptions in the corresponding port sections Pn_IN Port n Input Register 24H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4...

Page 470: ...the rising edge of HDRST and can be read by software afterwards Note that some of the P0 7 0 lines are used for configuration purposes too see Page 10 25 Figure 10 4 Port 0 Configuration Diagram Table 10 6 summarizes the I O control selection functions of each Port 0 line SCU Register SCU_SCLIR MCA05655 P0 8 P6 8 P0 9 Control P0 10 Control P0 11 Control P0 12 Control P0 13 Control P0 14 Control P0...

Page 471: ... Reserved1 1X01B 1X10B 1X11B P0 1 I General purpose input P0_IN P1 P0_IOCR0 PC1 0XXXB O General purpose output P0_OUT P1 1X00B Reserved1 1X01B 1X10B 1X11B P0 2 I General purpose input P0_IN P2 P0_IOCR0 PC2 0XXXB O General purpose output P0_OUT P2 1X00B Reserved1 1X01B 1X10B 1X11B P0 3 I General purpose input P0_IN P3 P0_IOCR0 PC3 0XXXB O General purpose output P0_OUT P3 1X00B Reserved1 1X01B 1X10B...

Page 472: ...IN P8 P0_IOCR8 PC8 0XXXB O General purpose output P0_OUT P8 1X00B Reserved1 1X01B 1X10B 1X11B P0 9 I General purpose input P0_IN P9 P0_IOCR8 PC9 0XXXB O General purpose output P0_OUT P9 1X00B Reserved1 1X01B 1X10B 1X11B P0 10 I General purpose input P0_IN P10 P0_IOCR8 PC10 0XXXB O General purpose output P0_OUT P10 1X00B Reserved1 1X01B 1X10B 1X11B P0 11 I General purpose input P0_IN P11 P0_IOCR8 P...

Page 473: ...B P0 14 I General purpose input P0_IN P14 P0_IOCR12 PC14 0XXXB O General purpose output P0_OUT P14 1X00B Reserved1 1X01B 1X10B 1X11B P0 15 I General purpose input P0_IN P15 P0_IOCR12 PC15 0XXXB O General purpose output P0_OUT P15 1X00B Reserved1 1X01B 1X10B 1X11B 1 The port I O control values P0_IOCRx Py that are assigned to this reserved alternate output control selection should not be used Other...

Page 474: ... Port 0 Output Modification Register 0004H Page 10 14 P0_IOCR0 Port 0 Input Output Control Register 0 0010H Page 10 7 P0_IOCR4 Port 0 Input Output Control Register 4 0014H Page 10 8 P0_IOCR8 Port 0 Input Output Control Register 8 0018H Page 10 8 P0_IOCR12 Port 0 Input Output Control Register 12 001CH Page 10 9 P0_IN Port 0 Input Register 0024H Page 10 17 P0_PDR Port 0 Pad Driver Mode Register 0040...

Page 475: ...w rate of Port 0 line groups The Port 0 port lines are all class A1 pads see also Figure 10 4 P0_PDR Port 0 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P0 7 0 Class A1 pads for coding see Page 10 11 PD1 6 4 rw Pad Driver Mo...

Page 476: ...xt page Note The reset value bits X of the register SCU_SCLIR is defined by the circuitry connected to Port 0 at the rising edge of HDRST Port 0 lines are set to inputs with pull up devices connected reset values of port input output control registers SCU_SCLIR SCU Software Configuration Latched Inputs Register F0000038H Reset Value 0000 XXXXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15...

Page 477: ...le 10 8 Reserved SWOPT Bits in TC1796 Devices TC1796 Device Version SWOPTx Bits x 0 15 P0 15 8 P0 7 6 P0 5 P0 4 P0 3 P0 2 0 P0 15 8 TC1796 user user user 1 user 1 1 The P0 2 0 bits are only used in alternate boot modes see Page 4 28 If alternate boot modes are not required or used in an application P0 2 0 can also be used for user program software configuration selection purposes during a hardware...

Page 478: ...re the system clock output SYSCLK is provided at Port 1 Figure 10 5 Port 1 Configuration Diagram MCA05656 P1 8 RCLK0A P6 8 P1 9 Control P1 10 Control P1 11 Control P1 12 Control P1 13 Control P1 14 Control P1 15 Control P1 9 RREADY0A P1 10 RVALID0A P1 11 RDATA0A P1 12 SYSCLK P1 13 RCLK0B P1 14 RVALID0B P1 15 RDATA0B P1 7 TDATA0 P1 7 Control P1 6 TVALID0A P1 6 Control P1 5 TREADY0A P1 5 Control P1 ...

Page 479: ...eral purpose input P1_IN P0 P1_IOCR0 PC0 0XXXB SCU input REQ0 O General purpose output P1_OUT P0 1X00B Reserved1 1X01B 1X10B 1X11B P1 1 I General purpose input P1_IN P1 P1_IOCR0 PC1 0XXXB REQ1 O General purpose output P1_OUT P1 1X00B Reserved1 1X01B 1X10B 1X11B P1 2 I General purpose input P1_IN P2 P1_IOCR0 PC2 0XXXB REQ2 O General purpose output P1_OUT P2 1X00B Reserved1 1X01B 1X10B 1X11B P1 3 I ...

Page 480: ...erved1 1X01B 1X10B 1X11B P1 6 I General purpose input P1_IN P6 P1_IOCR4 PC6 0XXXB O General purpose output P1_OUT P6 1X00B MLI0 output TVALID0A 1X01B Reserved1 1X10B 1X11B P1 7 I General purpose input P1_IN P7 P1_IOCR4 PC7 0XXXB O General purpose output P1_OUT P7 1X00B MLI0 output TDATA0 1X01B Reserved1 1X10B 1X11B P1 8 I General purpose input P1_IN P8 P1_IOCR8 PC8 0XXXB MLI0 input RCLK0A O Genera...

Page 481: ... 1X01B 1X10B 1X11B P1 11 I General purpose input P1_IN P11 P1_IOCR8 PC11 0XXXB MLI0 input RDATA0A O General purpose output P1_OUT P11 1X00B Reserved1 1X01B 1X10B 1X11B P1 12 General purpose input P1_IN P12 P1_IOCR12 PC12 0XXXB O General purpose output P1_OUT P12 1X00B System clock output SYSCLK 1X01B Reserved1 1X10B 1X11B P1 13 I General purpose input P1_IN P13 P1_IOCR12 PC13 0XXXB MLI0 input RCLK...

Page 482: ...ort line behavior may occur Table 10 10 Port 1 Registers Register Short Name Register Long Name Offset Address Description see P1_OUT Port 1 Output Register 0000H Page 10 13 P1_OMR Port 1 Output Modification Register 0004H Page 10 14 P1_IOCR0 Port 1 Input Output Control Register 0 0010H Page 10 7 P1_IOCR4 Port 1 Input Output Control Register 4 0014H Page 10 8 P1_IOCR8 Port 1 Input Output Control R...

Page 483: ... assigned to A1 and A2 pad classes see also Figure 10 5 P1_PDR Port 1 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDSYSCLK 0 PDMLI0 r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P1 3 0 and P1 15 13 Class A1 pads for coding see Page 10 11 PD1 6 4 rw Pad Driver...

Page 484: ...1 or GPTA0 GPTA1 LTCA2 I O lines Figure 10 6 Port 2 Configuration Diagram MCA05657 P2 2 Control P2 3 Control P2 4 Control P2 5 Control P2 6 Control P2 7 Control P2 8 Control P2 9 Control P2 10 Control P2 11 Control P2 12 Control P2 13 Control P2 14 Control P2 15 Control GPTA0 P2 2 SLSO2 P2 3 SLSO3 P2 4 SLSO4 P2 5 SLSO5 P2 6 SLSO6 P2 7 SLSO7 P2 8 IN0 OUT0 P2 9 IN1 OUT1 P2 10 IN2 OUT2 P2 11 IN3 OUT3...

Page 485: ...B SSC0 output SLSO02 1X01B SSC1 output SLSO12 1X10B SSC0 SSC1 output SLSO02 AND SLSO12 1X11B P2 3 I General purpose input P2_IN P3 P2_IOCR0 PC3 0XXXB O General purpose output P2_OUT P3 1X00B SSC0 output SLSO03 1X01B SSC1 output SLSO13 1X10B SSC0 SSC1 output SLSO03 AND SLSO13 1X11B P2 4 I General purpose input P2_IN P4 P2_IOCR4 PC4 0XXXB O General purpose output P2_OUT P4 1X00B SSC0 output SLSO04 1...

Page 486: ...0 output SLSO07 1X01B SSC1 output SLSO17 1X10B SSC0 SSC1 output SLSO07 AND SLSO17 1X11B P2 8 I General purpose input P2_IN P8 P2_IOCR8 PC8 0XXXB GPTA0 GPTA1 LTCA2 input IN0 O General purpose output P2_OUT P8 1X00B GPTA0 output OUT0 1X01B GPTA1 output OUT0 1X10B LTCA2 output OUT0 1X11B P2 9 I General purpose input P2_IN P9 P2_IOCR8 PC9 0XXXB GPTA0 GPTA1 LTCA2 input IN1 O General purpose output P2_O...

Page 487: ...output P2_OUT P11 1X00B GPTA0 output OUT3 1X01B GPTA1 output OUT3 1X10B LTCA2 output OUT3 1X11B P2 12 I General purpose input P2_IN P12 P2_IOCR12 PC12 0XXXB GPTA0 GPTA1 LTCA2 input IN4 O General purpose output P2_OUT P12 1X00B GPTA0 output OUT4 1X01B GPTA1 output OUT4 1X10B LTCA2 output OUT4 1X11B P2 13 I General purpose input P2_IN P13 P2_IOCR12 PC13 0XXXB GPTA0 GPTA1 LTCA2 input IN5 O General pu...

Page 488: ... output P2_OUT P14 1X00B GPTA0 output OUT6 1X01B GPTA1 output OUT6 1X10B LTCA2 output OUT6 1X11B P2 15 I General purpose input P2_IN P15 P2_IOCR12 PC15 0XXXB GPTA0 GPTA1 LTCA2 input IN7 O General purpose output P2_OUT P15 1X00B GPTA0 output OUT7 1X01B GPTA1 output OUT7 1X10B LTCA2 output OUT7 1X11B Table 10 11 Port 2 Functions cont d Port Pin I O Pin Functionality AssociatedReg I O Line Port I O C...

Page 489: ...on Page 10 14 However port lines P2 0 and P2 1 are not available Therefore the P2_OMR bits PS 1 0 and PR 1 0 have no direct effect on port lines but only on register bits P2_OUT P 1 0 Table 10 12 Port 2 Registers Register Short Name Register Long Name Offset Address Description see P2_OUT Port 2 Output Register 0000H below1 1 These registers are listed and noted here in the Port 2 section because ...

Page 490: ...r functionality is described on Page 10 16 At Port 2 only port lines P2 15 8 are connected to GPTA I O lines Therefore only these port lines of Port 2 can be controlled for the emergency stop function The P2_ESR bits EN 7 0 are not implemented They are always read as 0 and should be written with 0 P2_IOCR0 Port 2 Input Output Control Register 0 10H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15...

Page 491: ... A1 and A2 pad classes see also Figure 10 6 P2_PDR Port 2 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDSLS1 0 PDSLS0 r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 r rw r Field Bits Type Description PD1 6 4 rw Pad Driver Mode for P2 15 8 Class A1 pads for coding see Page 10 11 PDSLS0 18 16 rw Pad Driver Mode for P2 3 2 Class A2 pa...

Page 492: ...uration Diagram MCA05658 P3 0 IN8 OUT8 P3 0 Control P3 1 Control P3 2 Control P3 3 Control P3 4 Control P3 5 Control P3 6 Control P3 7 Control P3 8 Control P3 9 Control P3 10 Control P3 11 Control P3 12 Control P3 13 Control P3 14 Control P3 15 Control GPTA1 GPTA0 LTCA2 P3 1 IN9 OUT9 P3 2 IN10 OUT10 P3 3 IN11 OUT11 P3 4 IN12 OUT12 P3 5 IN13 OUT13 P3 6 IN14 OUT14 P3 7 IN15 OUT15 P3 8 IN16 OUT16 P3 ...

Page 493: ...0 1X00B GPTA0 output OUT8 1X01B GPTA1 output OUT8 1X10B LTCA2 output OUT8 1X11B P3 1 I General purpose input P3_IN P1 P3_IOCR0 PC1 0XXXB GPTA0 GPTA1 LTCA2 input IN9 O General purpose output P3_OUT P1 1X00B GPTA0 output OUT9 1X01B GPTA1 output OUT9 1X10B LTCA2 output OUT9 1X11B P3 2 I General purpose input P3_IN P2 P3_IOCR0 PC2 0XXXB GPTA0 GPTA1 LTCA2 input IN10 O General purpose output P3_OUT P2 1...

Page 494: ...utput P3_OUT P5 1X00B GPTA0 output OUT13 1X01B GPTA1 output OUT13 1X10B LTCA2 output OUT13 1X11B P3 6 I General purpose input P3_IN P6 P3_IOCR4 PC6 0XXXB GPTA0 GPTA1 LTCA2 input IN14 O General purpose output P3_OUT P6 1X00B GPTA0 output OUT14 1X01B GPTA1 output OUT14 1X10B LTCA2 output OUT14 1X11B P3 7 I General purpose input P3_IN P7 P3_IOCR4 PC7 0XXXB GPTA0 GPTA1 LTCA2 input IN15 O General purpo...

Page 495: ...t P3_OUT P9 1X00B GPTA0 output OUT17 1X01B GPTA1 output OUT17 1X10B LTCA2 output OUT17 1X11B P3 10 I General purpose input P3_IN P10 P3_IOCR8 PC10 0XXXB GPTA0 GPTA1 LTCA2 input IN18 O General purpose output P3_OUT P10 1X00B GPTA0 output OUT18 1X01B GPTA1 output OUT18 1X10B LTCA2 output OUT18 1X11B P3 11 I General purpose input P3_IN P11 P3_IOCR8 PC11 0XXXB GPTA0 GPTA1 LTCA2 input IN19 O General pu...

Page 496: ...tput P3_OUT P13 1X00B GPTA0 output OUT21 1X01B GPTA1 output OUT21 1X10B LTCA2 output OUT21 1X11B P3 14 I General purpose input P3_IN P14 P3_IOCR12 PC14 0XXXB GPTA0 GPTA1 LTCA2 input IN22 O General purpose output P3_OUT P14 1X00B GPTA0 output OUT22 1X01B GPTA1 output OUT22 1X10B LTCA2 output OUT22 1X11B P3 15 I General purpose input P3_IN P15 P3_IOCR12 PC15 0XXXB GPTA0 GPTA1 LTCA2 input IN23 O Gene...

Page 497: ... Output Register 0000H Page 10 13 P3_OMR Port 3 Output Modification Register 0004H Page 10 14 P3_IOCR0 Port 3 Input Output Control Register 0 0010H Page 10 7 P3_IOCR4 Port 3 Input Output Control Register 4 0014H Page 10 8 P3_IOCR8 Port 3 Input Output Control Register 8 0018H Page 10 8 P3_IOCR12 Port 3 Input Output Control Register 12 001CH Page 10 9 P3_IN Port 3 Input Register 0024H Page 10 17 P3_...

Page 498: ...rate of Port 3 line groups The Port 3 port lines are all of pad class A1 see also Figure 10 7 P3_PDR Port 3 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P3 7 0 Class A1 pads for coding see Page 10 11 PD1 6 4 rw Pad Driver ...

Page 499: ...ation Diagram MCA05659 P4 0 IN24 OUT24 P4 0 Control P4 1 Control P4 2 Control P4 3 Control P4 4 Control P4 5 Control P4 6 Control P4 7 Control P4 8 Control P4 9 Control P4 10 Control P4 11 Control P4 12 Control P4 13 Control P4 14 Control P4 15 Control GPTA1 GPTA0 LTCA2 P4 1 IN25 OUT25 P4 2 IN26 OUT26 P4 3 IN27 OUT27 P4 4 IN28 OUT28 P4 5 IN29 OUT29 P4 6 IN30 OUT30 P4 7 IN31 OUT31 P4 8 IN32 OUT32 P...

Page 500: ...X00B GPTA0 output OUT24 1X01B GPTA1 output OUT24 1X10B LTCA2 output OUT24 1X11B P4 1 I General purpose input P4_IN P1 P4_IOCR0 PC1 0XXXB GPTA0 GPTA1 LTCA2 input IN25 O General purpose output P4_OUT P1 1X00B GPTA0 output OUT25 1X01B GPTA1 output OUT25 1X10B LTCA2 output OUT25 1X11B P4 2 I General purpose input P4_IN P2 P4_IOCR0 PC2 0XXXB GPTA0 GPTA1 LTCA2 input IN26 O General purpose output P4_OUT ...

Page 501: ...utput P4_OUT P5 1X00B GPTA0 output OUT29 1X01B GPTA1 output OUT29 1X10B LTCA2 output OUT29 1X11B P4 6 I General purpose input P4_IN P6 P4_IOCR4 PC6 0XXXB GPTA0 GPTA1 LTCA2 input IN30 O General purpose output P4_OUT P6 1X00B GPTA0 output OUT30 1X01B GPTA1 output OUT30 1X10B LTCA2 output OUT30 1X11B P4 7 I General purpose input P4_IN P7 P4_IOCR4 PC7 0XXXB GPTA0 GPTA1 LTCA2 input IN31 O General purpo...

Page 502: ...t P4_OUT P9 1X00B GPTA0 output OUT33 1X01B GPTA1 output OUT33 1X10B LTCA2 output OUT33 1X11B P4 10 I General purpose input P4_IN P10 P4_IOCR8 PC10 0XXXB GPTA0 GPTA1 LTCA2 input IN34 O General purpose output P4_OUT P10 1X00B GPTA0 output OUT34 1X01B GPTA1 output OUT34 1X10B LTCA2 output OUT34 1X11B P4 11 I General purpose input P4_IN P11 P4_IOCR8 PC11 0XXXB GPTA0 GPTA1 LTCA2 input IN35 O General pu...

Page 503: ...TCA2 input IN37 O General purpose output P4_OUT P13 1X00B GPTA0 output OUT37 1X01B GPTA1 output OUT37 1X10B LTCA2 output OUT37 1X11B P4 14 I General purpose input P4_IN P14 P4_IOCR12 PC14 0XXXB GPTA0 GPTA1 LTCA2 input IN38 O General purpose output P4_OUT P14 1X00B GPTA0 output OUT38 1X01B GPTA1 output OUT38 1X10B LTCA2 output OUT38 1X11B P4 15 I General purpose input P4_IN P15 P4_IOCR12 PC15 0XXXB...

Page 504: ..._OMR Port 4 Output Modification Register 0004H Page 10 14 P4_IOCR0 Port 4 Input Output Control Register 0 0010H Page 10 7 P4_IOCR4 Port 4 Input Output Control Register 4 0014H Page 10 8 P4_IOCR8 Port 4 Input Output Control Register 8 0018H Page 10 8 P4_IOCR12 Port 4 Input Output Control Register 12 001CH Page 10 9 P4_IN Port 4 Input Register 0024H Page 10 17 P4_PDR Port 4 Pad Driver Mode Register ...

Page 505: ... 4 lines and line groups The Port 4 port lines are assigned to A1 and A2 pad classes see also Figure 10 8 P4_PDR Port 4 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD1 0 PD0 r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P4 7 0 Class A2 pads for coding see Page 10 11 PD1 6 4 rw...

Page 506: ... is an 8 bit bi directional general purpose I O port which can be used for the ASC0 ASC1 MSC0 MSC1 or MLI0 interface I O lines Figure 10 9 Port 5 Configuration Diagram MCA05660 P5 0 RXD0A P5 0 Control P5 1 Control P5 2 Control P5 3 Control P5 4 Control P5 5 Control P5 6 Control P5 7 Control ASC0 P5 1 TXD0A P5 2 RXD1A P5 3 TXD1A P5 4 EN00 RREADY0B P5 5 SDI0 P5 6 EN10 TVALID0B P5 7 SDI1 A2 A2 A2 A2 ...

Page 507: ...X00B ASC0 output sync mode RXD0A 1X01B Reserved1 1X10B 1X11B P5 1 I General purpose input P5_IN P1 P5_IOCR0 PC1 0XXXB O General purpose output P5_OUT P1 1X00B ASC0 output TXD0A 1X01B Reserved1 1X10B 1X11B P5 2 I General purpose input P5_IN P2 P5_IOCR0 PC2 0XXXB ASC1 input RXD1A O General purpose output P5_OUT P2 1X00B ASC1 output sync mode RXD1A 1X01B Reserved1 1X10B 1X11B P5 3 I General purpose i...

Page 508: ...utput P5_OUT P6 1X00B MSC1 output EN10 1X01B 1X11B MLI0 output TVALID0B 1X10B P5 7 I General purpose input P5_IN P7 P5_IOCR4 PC7 0XXXB MSC1 input SDI1 O General purpose output P5_OUT P7 1X00B Reserved1 1X01B 1X10B 1X11B 1 The port I O control values P5_IOCRx Py that are assigned to this reserved alternate output control selection should not be used Otherwise unpredictable output port line behavior...

Page 509: ...5 15 8 are not available Therefore the P5_OMR bits PS 15 8 and PR 15 8 are not implemented These bits should always be written with 0 10 8 3 3 Port 5 Input Register The basic P5_IN register functionality is described on Page 10 17 Port lines P5 15 8 are not available Therefore the P5_IN bits P 15 8 are always read as 0 Table 10 18 Port 5 Registers Register Short Name Register Long Name Offset Addr...

Page 510: ...d Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDMSC1 0 PDMSC0 0 PDASC1 0 PDASC0 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r Field Bits Type Description PDASC0 18 16 rw Pad Driver Mode for P5 1 0 Class A2 pads for coding see Page 10 11 PDASC1 22 20 rw Pad Driver Mode for P5 3 2 Class A2 pads for coding see Page 10 11 PDMSC0 26 ...

Page 511: ...SSC1 ASC0 ASC1 or for the MultiCAN controller I O lines Figure 10 10 Port 6 Configuration Diagram MCA05661 P6 8 RXD0B RXDCAN0 P6 8 P6 9 Control P6 10 Control P6 11 Control P6 12 Control P6 13 Control P6 14 Control P6 15 Control P6 9 TXD0B TXDCAN0 P6 10 RXD1B RXDCAN1 P6 11 TXD1B TXDCAN1 P6 12 RXDCAN2 P6 13 TXDCAN2 P6 14 RXDCAN3 P6 15 TXDCAN3 P6 7 SLSI1 P6 7 Control P6 6 SCLK1 P6 6 Control P6 5 MRST...

Page 512: ...ut slave mode MTSR1 O General purpose output P6_OUT P4 1X00B SSC1 output master mode MTSR1 1X01B Reserved1 1X10B 1X11B P6 5 I General purpose input P6_IN P5 P6_IOCR4 PC5 0XXXB SSC1 input master mode MRST1 O General purpose output P6_OUT P5 1X00B SSC1 output slave mode MRST1 1X01B Reserved1 1X10B 1X11B P6 6 I General purpose input P6_IN P6 P6_IOCR4 PC6 0XXXB SSC1 input slave mode SCLK1 O General pu...

Page 513: ...tput P6_OUT P9 1X00B CAN node 0 output TXDCAN0 1X01B ASC0 output TXD0B 1X10B Reserved1 1X11B P6 10 I General purpose input P6_IN P10 P6_IOCR8 PC10 0XXXB CAN node 1 rec input 0 CAN node 0 rec input 1 RXDCAN1 ASC1 input RXD1B O General purpose output P6_OUT P10 1X00B 1X01B ASC1 output sync mode RXD1B 1X01B Reserved1 1X11B P6 11 I General purpose input P6_IN P11 P6_IOCR8 PC11 0XXXB O General purpose ...

Page 514: ... P6 14 I General purpose input P6_IN P14 P6_IOCR12 PC14 0XXXB CAN node 3 rec input 0 CAN node 2 rec input 1 RXDCAN3 O General purpose output P6_OUT P14 1X00B Reserved1 1X01B 1X10B 1X11B P6 15 I General purpose input P6_IN P15 P6_IOCR12 PC15 0XXXB O General purpose output P6_OUT P15 1X00B CAN node 3 output TXDCAN3 1X01B Reserved1 1X10B 1X11B 1 The port I O control values P6_IOCRx Py that are assign...

Page 515: ...n Page 10 14 Port lines P6 3 0 are not available Therefore they are not implemented These bits should always be written with 0 10 9 3 3 Port 6 Input Register The basic P6_IN register functionality is described on Page 10 17 Port lines P6 3 0 are not available Therefore the P6_IN bits P 3 0 are always read as 0 Table 10 20 Port 6 Registers Register Short Name Register Long Name Offset Address Descr...

Page 516: ...6 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDCAN23 0 PDCAN01 0 PDSSC1 0 0 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r Field Bits Type Description PDSSC1 22 20 rw Pad Driver Mode for P6 7 4 Class A2 pads for coding see Page 10 11 PDCAN01 26 24 rw Pad Driver Mode for P6 11 8 Class A2 pads for coding see Page 10 11 PDCAN23...

Page 517: ...general purpose I O port that can be used for the external trigger input lines REQ 7 4 or for the ADC0 ADC1 external multiplexer control output lines Figure 10 11 Port 7 Configuration Diagram MCA05662 P7 4 REQ6 P6 8 P7 5 Control P7 6 Control P7 7 Control P7 5 REQ7 P7 6 AD1EMUX0 P7 7 AD1EMUX1 P7 3 AD0EMUX1 P7 3 Control P7 2 AD0EMUX0 P7 2 Control P7 1 REQ5 AD0EMUX2 P7 1 Control P7 0 REQ4 P7 0 Contro...

Page 518: ...ose output P7_OUT P0 1X00B Reserved1 1X01B 1X10B 1X11B P7 1 I General purpose input P7_IN P1 P7_IOCR0 PC1 0XXXB SCU input REQ5 O General purpose output P7_OUT P1 1X00B ADC0 output AD0EMUX2 1X01B Reserved1 1X10B 1X11B P7 2 I General purpose input P7_IN P2 P7_IOCR0 PC2 0XXXB O General purpose output P7_OUT P2 1X00B ADC0 output AD0EMUX0 1X01B Reserved1 1X10B 1X11B P7 3 I General purpose input P7_IN P...

Page 519: ... purpose output P7_OUT P6 1X00B ADC1 output AD1EMUX0 1X01B Reserved1 1X10B 1X11B P7 7 I General purpose input P7_IN P7 P7_IOCR4 PC7 0XXXB O General purpose output P7_OUT P7 1X00B ADC1 output AD1EMUX1 1X01B Reserved1 1X10B 1X11B 1 The port I O control values P7_IOCRx Py that are assigned to this reserved alternate output control selection should not be used Otherwise unpredictable output port line ...

Page 520: ... 8 are not available Therefore the P7_OMR bits PS 15 8 and PR 15 8 are not implemented These bits should always be written with 0 10 10 3 3 Port 7 Input Register The basic P7_IN register functionality is described on Page 10 17 Port lines P7 15 8 are not available Therefore the P7_IN bits P 15 8 are always read as 0 Table 10 22 Port 7 Registers Register Short Name Register Long Name Offset Address...

Page 521: ...pad driver mode output driver strength and slew rate of the Port 7 lines The Port 7 port lines are all class A1 pads see also Figure 10 11 P7_PDR Port 7 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD0 r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P7 7 0 Class A1 pads for coding see...

Page 522: ...I O port which can be used for the MLI1 interface lines or for the GPTA0 GPTA1 I O lines Figure 10 12 Port 8 Configuration Diagram MCA05663 P8 0 TCLK1 IN 40 OUT40 P8 0 Control P8 1 Control P8 2 Control P8 3 Control P8 4 Control P8 5 Control P8 6 Control P8 7 Control GPTA1 GPTA0 P8 1 TREADY1A IN41 OUT41 P8 2 TVALID1A IN42 OUT42 P8 3 TDATA1 IN43 OUT43 P8 4 RCLK1A IN44 OUT44 P8 5 RREADY1A IN45 OUT45 ...

Page 523: ...1X00B GPTA0 output OUT40 1X01B GPTA1 output OUT40 1X10B MLI1 output TCLK1 1X11B P8 1 I General purpose input P8_IN P1 P8_IOCR0 PC1 0XXXB GPTA0 GPTA1 input IN41 MLI1 input TREADY1A O General purpose output P8_OUT P1 1X00B GPTA0 output OUT41 1X01B GPTA1 output OUT41 1X10B Reserved1 1X11B P8 2 I General purpose input P8_IN P2 P8_IOCR0 PC2 0XXXB GPTA0 GPTA1 input IN42 O General purpose output P8_OUT P...

Page 524: ... I General purpose input P8_IN P6 P8_IOCR4 PC6 0XXXB GPTA0 GPTA1 input IN46 MLI1 input RVALID1A O General purpose output P8_OUT P6 1X00B GPTA0 output OUT46 1X01B GPTA1 output OUT46 1X10B Reserved1 1X11B P8 7 I General purpose input P8_IN P7 P8_IOCR4 PC7 0XXXB GPTA0 GPTA1 input IN47 MLI1 input RDATA1A O General purpose output P8_OUT P7 1X00B GPTA0 output OUT47 1X01B GPTA1 output OUT47 1X10B Reserve...

Page 525: ...egister The basic P8_IN register functionality is described on Page 10 17 Port lines P8 15 8 are not available Therefore the P8_IN bits P 15 8 are always read as 0 10 11 3 4 Port 8 Emergency Stop Register The basic P8_ESR register functionality is described on Page 10 16 At Port 8 only port lines P8 7 0 are implemented Therefore the P8_ESR bits EN 15 8 are not implemented They are always read as 0...

Page 526: ...oups The Port 8 port lines are assigned to A1 and A2 pad classes see also Figure 10 12 P8_PDR Port 8 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDMLI1 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD0 r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P8 1 P8 4 P8 6 and P8 7 Class A1 pads for coding see Page 10 11 PDMLI1 18 16 ...

Page 527: ...h can be used for the MSC0 MSC1 interface output lines or for the GPTA0 GPTA1 I O lines Figure 10 13 Port 9 Configuration Diagram MCA05664 P9 0 EN12 IN 48 OUT48 P9 0 Control P9 1 Control P9 2 Control P9 3 Control P9 4 Control P9 5 Control P9 6 Control P9 7 Control GPTA1 GPTA0 P9 1 EN12 IN49 OUT49 P9 2 SOP1B IN50 OUT50 P9 3 FCLP1B IN51 OUT51 P9 4 EN03 IN52 OUT52 P9 5 EN02 IN53 OUT53 P9 6 EN01 IN54 ...

Page 528: ..._OUT P0 1X00B GPTA0 output OUT48 1X01B GPTA1 output OUT48 1X10B MSC1 output EN12 1X11B P9 1 I General purpose input P9_IN P1 P9_IOCR0 PC1 0XXXB GPTA0 GPTA1 input IN49 O General purpose output P9_OUT P1 1X00B GPTA0 output OUT49 1X01B GPTA1 output OUT49 1X10B MSC1 output EN11 1X11B P9 2 I General purpose input P9_IN P2 P9_IOCR0 PC2 0XXXB GPTA0 GPTA1 input IN50 O General purpose output P9_OUT P2 1X00...

Page 529: ...1X10B MSC0 output EN02 1X11B P9 6 I General purpose input P9_IN P6 P9_IOCR4 PC6 0XXXB GPTA0 GPTA1 input IN54 O General purpose output P9_OUT P6 1X00B GPTA0 output OUT54 1X01B GPTA1 output OUT54 1X10B MSC0 output EN01 1X11B P9 7 I General purpose input P9_IN P7 P9_IOCR4 PC7 0XXXB GPTA0 GPTA1 input IN55 O General purpose output P9_OUT P7 1X00B GPTA0 output OUT55 1X01B GPTA1 output OUT55 1X10B MSC0 o...

Page 530: ...on Page 10 14 Port lines P9 15 9 are not available Therefore the P9_OMR bits PS 15 9 and PR 15 9 are not implemented These bits should always be written with 0 Table 10 26 Port 9 Registers Register Short Name Register Long Name Offset Address Description see P9_OUT Port 9 Output Register 0000H below1 1 These registers are listed and noted here in the Port 9 section because they differ from the gen...

Page 531: ...cy Stop Register The basic P9_ESR register functionality is described on Page 10 16 At Port 9 only port lines P9 8 0 are implemented Therefore the P9_ESR bits EN 15 9 are not implemented They are always read as 0 and should be written with 0 P9_IOCR8 Port 9 Input Output Control Register 8 14H Reset Value 0000 0020H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 532: ...lso Figure 10 13 P9_PDR Port 9 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDMSC1 0 PDMSC0 r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD0 r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for MSC1 GPIO P9 8 Class A2 pads for coding see Page 10 11 PDMSC0 18 16 rw Pad Driver Mode for GPTA MSC0 Outputs P9 7 4 Class A2 pads for...

Page 533: ...rising edge of HDRST and can be checked by software by reading bit field HWCFG in the reset status register RTS_SR The four input lines of Port 10 have weak pull up devices connected always active Inside the TC1796 the HWCFG 3 0 lines are used for boot configuration selection Input P10 1 HWCFG1 operates as emergency stop input for the GPTA modules The emergency stop control logic is described in d...

Page 534: ... P10_IN makes it possible to read the actual logic levels of the Port 10 inputs 10 13 2 1 Port 10 Input Register The basic P10_IN register functionality is described on Page 10 17 Port lines P10 15 4 are not available Therefore the P10_IN bits P 3 0 are always read as 0 Table 10 27 Port 10 Registers Register Short Name Register Long Name Offset Address1 1 The absolute addresses are calculated by a...

Page 535: ...SLSO0 and SLSO1 are connected to dedicated output pins When enabled SSC0_CON EN 1 SLSO0 and SLSO1 are dedicated output pins SLSO0 and SLSO1 are tri stated with SSC0_CON EN 0 default after reset When a dedicated SSC0 I O line is used as outputs its pad driver is controlled by two bits of the SCU_CON register located in the SCU SCU_CON SSC0PDR controls the output drivers of MTRS0 MRST0 and SCLK0 whi...

Page 536: ...ed SSC0_ CON EN 0 SLSI0 Input Dedicated SSC0 Slave Select Outputs SLSO0 SLSO1 Output Master SSC0_CON EN 1 SCU_CON SLSPDR2 SLSO0 SLSO1 Tri Stated SSC0_CON EN 0 1 SSC0PDR 0 strong driver sharp edge selected SSC0PDR 1 strong driver soft edge selected 2 SLSPDR 0 strong driver sharp edge selected SLSPDR 1 strong driver soft edge selected Table 10 28 SSC0 Dedicated I O Line Selection and Setup cont d De...

Page 537: ...n register SCU_CON With LDEN 0 all LVDS drivers are disabled and in power down mode With LDEN 1 all LVDS drivers are enabled for operation Table 10 29 LVDS Outputs of MSC0 MSC1 Signal Pin Short Name Description FCLP0A MSC0 differential driver clock output positive A FCLN0 MSC0 differential driver clock output negative SOP0A MSC0 differential driver serial data output positive A SON0 MSC0 different...

Page 538: ...d as the host processor s first line of defence as an interrupt handling engine The PCP can unload the CPU from having to service time critical interrupts This provides many benefits including Avoiding large interrupt driven task context switching latencies in the host processor Reducing the cost of interrupts in terms of processor register and memory overhead Improving the responsiveness of inter...

Page 539: ...y CMEM with parity protection Parameter Memory PRAM with parity protection PCP Interrupt Control Unit PICU PCP Service Request Nodes PSRN System bus interface to the Flexible Peripheral Interface FPI Bus Figure 11 1 PCP Block Diagram MCB05666 PCP Processor Core PCP Service Req Nodes PSRNs PCP Interrupt Control Unit PICU Parameter Memory PRAM Code Memory CMEM FPI Interface PCP Interrupt Arbitration...

Page 540: ...ceive the next service request The PCP Processor Core is capable of suspending execution of a channel program on receipt of a service request with a higher priority than the channel currently being executed The Core will automatically resume processing of the original channel program once the higher priority request or requests has been processed A channel that has been suspended in this way is te...

Page 541: ...r or other FPI Bus masters can use to communicate and share data While a portion of the PRAM is always implicitly used for the Context Save Areas CSAs of the channel programs the remaining area can be used for channel specific or general data storage A programmable 8 bit Data Pointer DPTR concatenated with a 6 bit offset is provided for arbitrary access to the PRAM The effective address is a 14 bi...

Page 542: ...eral the CPU external interrupts etc The PCP Interrupt Control Unit PICU determines the request with the currently highest priority and routes the request together with its priority number to the PCP Processor Core It also acknowledges the requesting source when the PCP starts the service of this interrupt The PCP itself can generate service requests to either the CPU or itself through a number of...

Page 543: ...on of the system environment outside of the scope of the PCP 11 3 1 General Purpose Register Set of the PCP The program accessible register file of the PCP is composed of eight 32 bit General Purpose Registers GPRs These registers are all accessible by PCP programs directly as part of the PCP instruction set Source and destination registers must be specified in most instructions These registers ar...

Page 544: ...is then accessible from outside the PCP 11 3 1 1 Register R0 R0 is used as an implicit operand destination for some instructions These are detailed in the individual instruction descriptions 11 3 1 2 Registers R1 R2 and R3 R1 R2 and R3 are general use registers It is recommended that by convention R2 should be used as a return address register when call and return program structures are used 11 3 ...

Page 545: ... be set to the priority level at which the channel shall run at its next invocation before the EXIT is executed The fields for R6 are shown below PCP Register R6 Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CPPN SRPN rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOS CNT1 rw rw rw rw Field Bits Type Description CNT1 11 0 rw General use Outer Loop count for COPY Instruction o...

Page 546: ...te the Z and N flags to 0 As a result the value left in R7 after the MOV is complete will be 0000FF04H i e C 1 Z 0 N 0 It is recommended that only SET and CLR instructions should be used to explicitly modify flags in R7 The Data Pointer R7 DPTR is the means of accessing PRAM variables programmatically It points to a 64 word PRAM segment that may be addressed by instructions that can use the PRAM f...

Page 547: ...rw rw rw rw rw rw Field Bits Type Description Z 0 rw Zero N 1 rw Negative C 2 rw Carry V 3 rw Overflow CNZ 4 rw Outer Loop Counter 1 Zero Flag IEN 5 rw Interrupt Enable 0B Channel is not interruptible 1B Channel can be suspended in favor of a higher priority service request CEN 6 rw Channel Enable Control Bit DPTR 15 8 rw Data Pointer Segment Address for PRAM accesses 7 rw Reserved should always b...

Page 548: ... is automatically copied to a defined area in the PRAM Context Save If the same channel program is re activated the contents of the registers are restored by copying the values from the same defined PRAM area into the appropriate registers Context Restore The defined area in the PRAM for the context save and restore operations is called the CSA Each channel program has its own individual predefine...

Page 549: ...elected Context Model is used for all channels Once a Context Model has been selected during PCP configuration and the PCP has been started the PCP must continue to use that Context Model Attempting to change the Context Model in use during PCP operation will lead to invalid context restore operations which will in turn lead to invalid PCP operation In the case of Small and Minimum Context Models ...

Page 550: ...2 0 Figure 11 2 PCP Context Models MCA05667 R0 R1 R2 R3 R4 R5 R6 R7 Stored Context in PRAM R0 R1 R2 R3 R4 R5 R6 R7 PCP Register Set Restore Save 8 Words Full Context R0 R1 R2 R3 R4 R5 R6 R7 R4 R5 R6 R7 Small Context Restore Save 4 Words R0 R1 R2 R3 R4 R5 R6 R7 R6 R7 Minimum Context Restore Save 2 Words ...

Page 551: ...uest in the TriCore Architecture the bottom region context region 0 of the CSA is never used for an actual context The total size of the CSA depends on the Context Model and the number of service request numbers used in a given system Each priority number used in a service request node which can activate interrupts to the PCP must be represented through a dedicated context region in the PRAM The h...

Page 552: ...reduced by the memory space required for this data For best utilization of PRAM it is advisable to have the CSA grow upwards as a contiguous area without any holes meaning that all SRPNs in the range 1 max are actually used to place interrupt requests on the PCP Unused regions within the CSA that is the unused region at the base of the CSA and any context regions associated with unused channels ca...

Page 553: ...user This may be advantageous for applications in which the majority of the channels do not need 4 Words not used Context 1 PRAM Memory 8 Words not used Context 1 Context 2 MCA05668 Full Context SRPN 1 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 00H 08H 10H SRPN 2 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 n1 8H SRPN n1 Context n1 31 0 SRPN 1 00H 04H 0CH CR7 CR6 CR5 CR4 CR7 CR6 CR5 CR4 08H Context 2 SRPN 2 Context 3 SRP...

Page 554: ...nt of PRAM used for general variables and globals Amount of context register content which need to be saved and restored quickly by most of the most important channels While registers R0 through R5 are always restored in a normal manner according to the context size registers R6 and R7 merit discussion regarding context restore operations The memory location CR7 in a context region is used to hold...

Page 555: ...6 and the lower half of R7 is loaded from CR7 15 0 The operating priority of the channel is taken from CR6 31 24 and all of R6 is loaded from CR6 Figure 11 4 Context Restore Channel Start in Channel Resume Mode MCA05669 31 16 0 CPPN PCP Interrupt Control Reg PCP_ICR 0 ARB CTL PIPN 0 IE 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 31 16 0 CPC CFLAGS Stored Content CR7 in PR...

Page 556: ...wer half of R7 is loaded from CR7 15 0 The upper half of CR6 is discarded The operating priority of the channel is taken from CR6 31 24 and all of R6 is loaded from CR6 Figure 11 5 Context Restore Channel Start in Channel Restart Mode MCA05670 31 16 0 CPPN PCP Interrupt Control Reg PCP_ICR 0 ARB CTL PIPN 0 IE 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 31 16 0 CPC CFLAGS ...

Page 557: ...the Service Request Node that was used to store the Suspended Interrupt Request see Page 11 70 Figure 11 6 Context Restore Suspended Channel Restart Channel Number MCA05671 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 31 16 0 CPC CFLAGS Stored Content CR7 in PRAM CDPTR 31 16 0 0 FLAGS DPTR PCP Register R7 Stored Content CR6 in PRAM 31 16 0 SRPN PCP Interrupt Req Node PCP_S...

Page 558: ... channel exit when Channel Resume Mode has been selected The value written to CR7 is created by concatenating the 16 bit PC value with the lower 16 bits of R7 CR6 is written with the value taken from R6 Figure 11 7 Context Save Channel Exit in Channel Resume Mode MCA05672 When the context save is due to execution of an EXIT instruction with EP 0 the PC is loaded with the appropriate channel entry ...

Page 559: ...en selected This is the same as for Channel Resume mode except that the PC value is discarded and the appropriate Channel Entry Table address is written to CR7 31 16 Figure 11 8 Context Save Channel Exit in Channel Restart Mode MCA05673 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS PCP Register R6 Stored Content CR6 in PRAM 31 16 0 CPC CFLAGS Stored Content CR7 in PRAM CDPTR 31 16 0 0 FLAG...

Page 560: ...annel number SRPN and the operating priority CPPN with which the channel was operating prior to being suspended This operation in conjunction with the suspended channel restore operation shown in Figure 11 6 allows the temporary suspension of a channel in favor of a higher priority channel Figure 11 9 Context Save Channel Suspend MCA05674 31 16 0 CNT1 CPPN SRPN TOS 31 16 0 CNT1 CPPN SRPN TOS Store...

Page 561: ...zed context switching strategy consisting of optimization of both context load and store During a context load in which the channel that is starting is also the last channel that the PCP was running then the PCP GPRs already contain the values appropriate to the channel In this case there is no need to reload the context i e the PCP can immediately continue operation at the appropriate point in th...

Page 562: ...t at the same address in the interrupt entry table each time the channel is requested Channel Resume Mode allows the PCP to begin execution at the PC address restored as part of the channel program context This mode allows for code to be contiguous and start at any arbitrary address It also allows for the implementation of interrupt driven state machines and even the sharing of code across multipl...

Page 563: ...en Channel Resume Mode is globally selected by configuring each EXIT instruction to determine the channel start address to be used on the next invocation of a channel see Page 11 89 When the EP 0 setting is used the PC value saved in the channel s context saved in CPC is the address of the appropriate location in the channel entry table This forces the channel to start at the appropriate location ...

Page 564: ...fset multiply each offset by two Code Memory CMEM Instruction 1 2 Half words not used Instruction 2 MCA05675 00H 02H SRPN 1 Channel 1 04H Instruction 2 Instruction 1 Channel 2 SRPN 2 SRPN 3 06H Instruction 2 Instruction 1 Channel 3 SRPN n1 n1 2H Instruction 1 Instruction 2 Channel 1 Channel 1 Main Code Channel 3 Main Code Channel n1 Main Code Channel 2 Main Code Channel Restart Mode 16 0 Channel E...

Page 565: ...ccepting interrupts and executing channel programs 11 4 2 Channel Invocation and Context Restore Operation A channel program is started when one or other of the following conditions occurs The current round of PCP interrupt arbitration results in a winning interrupt number SRPN and the PCP is currently quiescent has exited the previous channel and stored the context for that channel The current ro...

Page 566: ...ate noting that the PC value should be set to the appropriate channel entry point if PCP_CS RCB 1 11 4 3 Channel Exit and Context Save Operation The context of a channel program must be saved when it terminates Three events can cause the termination of a channel program Execution of the EXIT instruction normal termination Occurrence of an error Execution of the DEBUG instruction channel terminatio...

Page 567: ...is used Special care needs to be taken to optimize the number of clock cycles required to perform a Context Save During a Context Save the PCP Processor Core needs only to save those registers that have been written since the last Context Restore was performed Note Particular attention must be paid to the values of R6 and R7 prior to execution of the EXIT instruction When posting an interrupt requ...

Page 568: ... it must be able to restore the channel program to operation The minimum required to restart the channel program is to set the context value of CR7 CEN 1 11 4 3 3 Debug Exit If the DEBUG instruction is programmed to stop the channel program execution SDB 1 has been specified the PCP performs an exit sequence that is very similar to the error exit sequence with the exception that no interrupt reque...

Page 569: ...s an overview of the PCP interrupt scheme Figure 11 11 PCP Interrupt Block Diagram 11 5 1 Issuing Service Requests to CPU or PCP The PCP may use one of two mechanisms to raise an interrupt request to the CPU or itself The first and most inefficient method for a PCP channel program is to issue MCB05676 Winning SRPN Priority Interrupt Type PCP Core Queue full Nesting available CPPN SRPN TOS PCP_SRC2...

Page 570: ...equest to the PCP kernel If the PCP kernel is currently busy processing a channel program the new request is left pending until the current channel program has finished When the PCP kernel is ready to accept a new service request it calculates the context start address from the Pending Interrupt Priority Number PIPN stored in register ICR and begins with the context restore It notifies the PICU of...

Page 571: ... dependent Programming a PCP_SRCx register x 4 to 8 with a TOS value representing a non available interrupt bus 10B or 11B in the TC1796 will disable Service Request Node x The actual service request flag and the service request priority number of the PCP_SRCx registers are updated by the PCP when it generates an implicit service request The way this is performed is described in the following sect...

Page 572: ...he PCP suspends execution of the ongoing channel program in favor of a service request with a higher priority Such a service request is always issued to the PCP s own interrupt bus and is stored in one of the three extended Service Request Nodes PCP_SCR9 PCP_SRC10 PCPSRC11 Along with this request it passes the current channel operating priority CPPN as a SRPN and also the channel number the origin...

Page 573: ...sing them determines the stall rate Depending on the selected service provider via R6 TOS in case of an EXIT interrupt or always to the CPU in case of an error interrupt the request is routed to a free entry in the appropriate queue If no free entries are available in a queue at the time the PCP wants to post a request to that queue the PCP is forced to stall until an entry becomes clear This ensu...

Page 574: ... service requests to the PCP self interrupt the PCP will have to service these rather than outside interrupt sources Depending on the priority given to these requests this could undermine an otherwise appropriate use of the interrupt priority scheme It is recommended that the system be designed such that in most cases high priority numbers can be assigned to these self interrupts so that they can ...

Page 575: ...arding the use of PRAM this flexibility also introduces the possibility of invalid PCP operation as a result of the following issues Any channel program is allowed to write to any PRAM location including any location in the CSA This means that a channel program may be inadvertently programmed to corrupt the context save region belonging to another channel causing invalid operation of the corrupted...

Page 576: ...channels into consideration It should be noted that the instruction width of the PCP is 16 bits and that therefore execution of an instruction that is encoded into 32 bits e g LDL IL will generate two CMEM instruction reads That will therefore cause the internal watchdog counter to be incremented twice Note Enabling the Channel Watchdog function PCP_CS CWE 1 with a threshold of zero PCP_CS CWT 0 i...

Page 577: ...the instruction set and the available addressing modes of the PCP in the TC1796 11 7 1 DMA Primitives Table 11 3 DMA Transfer Instructions DMA Transfer BCOPY Move block of data value from FPI Bus source address location to FPI Bus destination address location Optionally increment or decrement source and destination pointer registers Optionally repeat instruction until counter CNT1 reaches 0 COPY M...

Page 578: ...content immediate offset LD P Load value from PRAM address location into register PRAM address DPTR register offset LD PI Load value from PRAM address location into register PRAM address DPTR immediate offset LDL IL Load 16 bit immediate value into lower bits 15 0 of register LDL IU Load 16 bit immediate value into upper bits 31 16 of register Store ST F Store register value to FPI Bus address loc...

Page 579: ...ical instructions such as PRAM PI indirect I and FPI F and IF execute unconditionally Table 11 5 Arithmetic Instructions Add ADD Add register to register conditionally ADD I Add immediate value to register ADD F Add content of FPI Bus address location to register byte half word or word ADD PI Add content of PRAM address location to register Subtract SUB Subtract register from register conditionall...

Page 580: ...ear specified bits within a PRAM location Logical Or OR Register OR register conditionally OR F Content of FPI Bus address location OR register byte half word or word OR PI Content of PRAM address location OR register MSET PI Set specified bits within a PRAM location Logical Exclusive Or XOR Register XOR register conditionally XOR F Content of FPI Bus address location XOR register byte half word o...

Page 581: ...ag into register position given by content of a register INB I Insert carry flag into register position given by immediate value Check Bit CHKB Set carry flag depending on value of specified register bit Table 11 8 Flow Control Instructions Jump JC Jump conditionally to PC short immediate offset address JC A Jump conditionally to immediate absolute address JC I Jump conditionally to PC register of...

Page 582: ...R indicated in the instruction is added to the immediate 5 bit offset value encoded in the instruction This address must be properly aligned for the type of data access byte half word or word If it is not aligned the results are undefined Effective Target Address 31 0 R a offset5 where a is the number of the register and offset5 is a 5 bit immediate offset value Instructions using this addressing ...

Page 583: ...6 3 Bit Addressing Single bits can be addressed in the PCP GPRs or in FPI Bus address locations A 5 bit value indicates the location of a bit in the register specified in the instruction This bit location is either given through an immediate value in the instruction or through the lower five bits of a second register indirect addressing Effective Bit Position 31 0 imm5 Effective Bit Position 31 0 ...

Page 584: ...L JC and JC I For absolute addressing the actual address in CMEM where program flow is to resume is either an immediate value imm16 in the CMEM location immediately following the jump instruction or it is contained in the lower 16 bits of a register If the value is greater than the PC size implemented an error condition has occurred Effective JUMP Address 15 0 imm16 Effective JUMP Address 15 0 R a...

Page 585: ...ontrol registers can be read at any time Write operations are only possible to the PCP_CS register all other register are read only Register PCP_CS can be optionally Endinit protected via bit PCP_CS EIE see Page 11 56 11 8 2 Access to the PRAM FPI Bus accesses to the PRAM must always be performed with word accesses byte or half word accesses will result in a bus error Attention needs to be paid wh...

Page 586: ...lowing formula Effective FPI Bus address 31 0 PRAM Base Address DPTR 6 11 8 3 Access to the CMEM FPI Bus accesses to the CMEM must always be performed with word accesses byte or half word accesses will result in a bus error When using a channel entry table the FPI Bus address of a specific channel s entry location is given by the following formula Effective FPI Bus address 31 0 CMEM Base Address 0...

Page 587: ...cution the action taken by the PCP depends on the value of the RTA instruction field If RTA 0 the PCP disables further invocations of the current channel through clearing bit R7 CEN and then performs a context save The execution of this channel is stopped at the point of the DEBUG instruction If the DAC instruction field 0 the PCP will continue to operate accepting service requests for other chann...

Page 588: ...reaccept service requests when PCP_CS EN is written to 1 Note The DEBUG instruction must be only used in DEBUG mode otherwise it will generate an IOP error Note If PCP_CS RCB 0 Channel Resume Mode then the channel program will begin executing at whatever PC is restored from the context location CR7 PC If PCP_CS RCB 1 Channel Restart Mode then the channel program is forced to always start at its ch...

Page 589: ...state of the PCP to the external FPI Bus master Figure 11 12 gives an overview of the PCP registers PCP Register Overview Figure 11 12 PCP Registers The complete address map of the PCP is described in Table 18 25 on Page 18 77 of this TC1796 System Units Vol 1 of 2 User s Manual Table 11 10 Registers Address Space PCP Registers Module Base Address End Address Note PCP F004 3F00H F004 3FFFH PCP_CLC...

Page 590: ...rol Register 0000H Page 11 55 PCP_ID PCP Module Identification Register 0008H Page 11 54 PCP_CS PCP Control Status Register 0010H Page 11 56 PCP_ES PCP Error Debug Status Register 0014H Page 11 59 PCP_ICR PCP Interrupt Control Register 0020H Page 11 61 PCP_ITR PCP Interrupt Threshold Control Register 0024H Page 11 63 PCP_ICON PCP Interrupt Configuration Register 0028H Page 11 64 PCP_SSR PCP Stall ...

Page 591: ...P Module Identification Register 008H Reset Value 0020 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit ...

Page 592: ...H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCG DIS 0 rw r Field Bits Type Description PCGDIS 15 rw Clock Gating Disable Bit Allows clock gating to be disabled 0B PCP Internal Clock stops when PCP is idle default after reset 1B PCP Internal Clock always runs 0 14 0 31 16 r Reserved Read as 0 should be written with 0 ...

Page 593: ...0 rw PCP Enable 0B PCP is disabled for operation default 1B PCP is enabled for operation Note This bit does not enable disable clocks for power saving It stops the PCP from accepting new service requests RST 1 rwh PCP Reset Request 0B No PCP software reset operation is requested 1B A PCP software reset is requested Halt any operating channel Reset all control registers to default values Reset PCP ...

Page 594: ...nable 0B Writes to PCP_CS are disabled if Endinit protection is enabled 1B Writes to PCP_CS are enabled if Endinit protection is enabled CS 7 6 rw Context Size Selection 00B Use Full Context for all channels 01B Use Small Context for all channels 10B Use Minimum Context for all channels 11B Reserved PPE 8 rw PRAM Partitioning Enable 0B PRAM is not partitioned 1B PRAM is partitioned Note When parti...

Page 595: ...the SRPN is greater than MCN an error condition has occurred For example setting PPS to n 3 will give a CSA containing 7 context save regions As channel 0 cannot be used and MCN 6 channels 1 to 6 are allowed CWE 16 rw Channel Watchdog Enable 0B Disable Channel Watchdog 1B Enable Channel Watchdog Note When enabled the Channel Watchdog counts the number of instructions executed since the channel sta...

Page 596: ...e last error debug event was an error generated by an FPI Bus error or an invalid address access otherwise clear Note An FPI Bus error event does not cause the PCP to post an error interrupt to the CPU An FPI Bus error interrupt is however generated by the FPI control logic IOP 1 rh Invalid Opcode Set if the last error debug event was an error generated by the PCP attempting to execute an Invalid ...

Page 597: ... was a debug event Note A debug event does not cause the posting of an interrupt to the CPU 0 5 r Reserved Read as 0 CWD 6 rh Channel Watchdog Triggered Set if the last error debug event was an error generated by a channel program attempting to execute more instructions than allowed by PCP_CS CWT PPC 7 rh PRAM Partitioning Check Set if the last error debug event was an error generated by a channel...

Page 598: ...terrupt Control Unit PICU PCP_ICR PCP Interrupt Control Register 20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 P ONE CYC PARBCYC PIPN r rw rw rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IE CPPN r rh rh Field Bits Type Description CPPN 7 0 rh Current PCP Priority Number This field indicates the current priority level of the PCP and is automatically updated by hardware ...

Page 599: ... follows the same coding scheme as described for the CPU interrupt arbitration 00B Four arbitration cycles default 01B Three arbitration cycles 10B Two arbitration cycles 11B One arbitration cycle PONECYC 26 rw Clocks per Arbitration Cycle Control This bit determines the number of clocks per arbitration cycle 0B Two clocks per arbitration cycle default 1B One clock per arbitration cycle 0 15 9 31 ...

Page 600: ...with interrupt bus 0 when the threshold condition is reached setting this value to 0 or disables the threshold detection mechanism ITL 19 16 rw Interrupt Threshold Level This bit field specifies the number of active interrupt entries at which an warning interrupt should be issued to the interrupt queue associated with interrupt bus 0 i e when the number of active port 0 interrupt requests stored i...

Page 601: ...OS when it wishes to raise an interrupt request via interrupt bus 0 P1T 3 2 r PCP Interrupt Bus 1 TOS Mapping This field reflects the TOS associated with interrupt bus 1 PCP interrupt arbitration bus The PCP should use this value in R6 TOS when it wishes to raise an interrupt request to itself the PCP is always connected to interrupt bus 1 P2T 5 4 r PCP Interrupt Bus 2 TOS Mapping This field refle...

Page 602: ...arbitration bus Interrupt bus 1 is always enabled IP2E 10 r PCP Interrupt Bus 2 Enable This bit reflects the status of interrupt bus 2 Interrupt bus 2 is always disabled not implemented in the TC1796 IP3E 11 r PCP Interrupt Bus 3 Enable This bit reflects the status of interrupt bus 3 Interrupt bus 3 is always disabled not implemented in the TC1796 0 31 12 r Reserved Read as 0 Field Bits Type Descr...

Page 603: ...on occurred This bit field can only be cleared by a reset STOS 9 8 rh PCP Stalled Type of Service This field shows the Type Of Service to which an interrupt was being posted that caused the last or present stall condition i e the service request queue that was full when the PCP attempted to post a request to it This bit field can only be cleared by a reset ST 15 rh PCP Stalled Status This bit show...

Page 604: ...OS 00 0 SRPN r rh r r r rh Field Bits Type Description SRPN 7 0 rh PCP Node x Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 0 CPU interrupt arbitration bus Default after reset is 00H TOS 11 10 r PCP Node x Type of Service State Always read as 00B This means TOS is associated with interrupt bus 0 CPU interrupt arb...

Page 605: ... 8 7 6 5 4 3 2 1 0 0 SRR SRE 1 TOS 01 0 SRPN r rh r r r rh Field Bits Type Description SRPN 7 0 rh PCP Node x Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 1 PCP interrupt arbitration bus Default after reset is 00H TOS 11 10 r PCP Node x Type of Service State Always read as 01B This means TOS is associated with i...

Page 606: ... rh PCP Node x Service Request Priority Number This number is automatically set by the PCP if it needs to place a service request on interrupt bus 0 CPU interrupt arbitration bus or 1 PCP interrupt arbitration bus Default after reset is 00H TOS 11 10 rw PCP Node x Type of Service State Control TOS value depends on the interrupt mapping that has been selected see Page 11 119 This bit field must be ...

Page 607: ...ically set by the PCP if it needs to place a service request on interrupt bus 0 CPU interrupt arbitration bus or 1 PCP interrupt arbitration bus When the PCP interrupt request contained was raised by the PCP Processor Core when executing an EXIT instruction then this bit field contains the SRPN value taken from R6 when the exit instruction was executed When the PCP interrupt request was raised by ...

Page 608: ...it instruction was executed When the PCP interrupt request was raised by the PCP Processor Core when suspending execution of a channel program in order to service a higher priority interrupt then this bit field contains the channel number of the channel that was suspended RRQ 28 rh PCP Node x Channel Restart Request Set when this service request register n contains an active service request that i...

Page 609: ...nd the state of flags Additionally many instructions including arithmetic and many flow control instructions are conditionally executed The descriptions of the PCP instructions are based on the following conventions Shift left or right respectively Indirect access based on contents of brackets de reference immNN Immediate value encoded into an instruction with width NN offsetNN Address offset imme...

Page 610: ...an equation of the Flags held in R7 See Table 11 12 Table 11 12 Condition Codes Description CONDCA B Test Flag Bits Code Mnemonic Unconditional A B 0H cc_UC Zero Equal A B Z 1 1H cc_Z Not Zero Not Equal A B Z 0 2H cc_NZ Overflow A B V 1 3H cc_V Carry Unsigned Less Than Check Bit True A B C 1 4H cc_C cc_ULT Unsigned Greater Than A B C OR Z 0 5H cc_UGT Signed Less Than A B N XOR V 1 6H cc_SLT Signed...

Page 611: ...rement CNT0 after each transfer Continue until CNT0 0 then decrement CNT1 and proceed to next instruction Post Decrement CNT0 after each transfer Continue until CNT0 0 then decrement CNT1 Reload CNT0 value and continue Continue until CNT1 0 then proceed to next instruction Reserved CNT0 CNT0 001B 111B CNT0 000B CNT0 00B CNT0 10B CNT0 11B Others Counter Reload Value COPY The COPY instruction uses a...

Page 612: ... EP 0 EP 1 Entry Point Control Set the PC to channel program Start EP 0 assumes that a Channel Entry Table exists in the base of CMEM Failure to provide such a table will cause improper operation Set the PC to the address contained in NextPC next instruction address INT INT 0 INT 1 Interrupt Control No Interrupt INT 1 AND cc_B True means Issue Interrupt RTA RTA 0 RTA 1 Action on Debug Exit Stop ch...

Page 613: ... by Size SRC Reserved S C S C 0 S C 1 Test Bit Control Check for Clear 0 Check for Set 1 SDB SDB 0 SDB 1 Stop on Debug Continue running if debug event triggered Stop PCP if debug event triggered ST ST 0 ST 1 Stop Channel Continue channel execution Leave channel program enabled Stop Channel Execution Perform actions according to RTA setting see above Table 11 13 Instruction Field Definitions cont d...

Page 614: ...nual 11 77 V2 0 2007 07 PCP V2 0 11 11 2 Counter Operation for COPY Instruction Figure 11 13 Counter Operation for COPY Instruction MCA05678 DATA Transfer COPY Instruction CNT0 0 Next Instruction CNT0 RC0 CNT0 CNT0 1 CNC CNT1 CNT1 1 CNT1 CNT1 1 CNT1 0 no yes 00 10 01 yes no ...

Page 615: ... 11 78 V2 0 2007 07 PCP V2 0 11 11 3 Counter Operation for BCOPY Instruction Figure 11 14 Counter Operation for BCOPY Instruction MCA05679_mod DATA Transfer Block size determined by CNT0 field BCOPY Instruction Next Instruction CNC CNT1 CNT1 1 CNT1 CNT1 1 CNT1 0 00 10 01 yes no ...

Page 616: ...nt divide instructions within the sequence DSTEP must use the same register for dividend and the same register for divisor as used in the preceding DINIT instruction The first instruction of any multiply sequence must be the MINIT initialization instruction Any additional instructions other than DINIT or DSTEP may also be used within the sequence as long as they do not modify any of the registers ...

Page 617: ...f CONDCA is false no operation is performed Operation if CONDCA True then R b R b R a else NOP Flags N Z V C ADD I Syntax ADD I Ra imm6 Description Add the zero extended immediate value imm6 to the contents of register Ra place the result in Ra Operation R a R a zero_ext imm6 Flags N Z V C ADD F Syntax ADD F Rb Ra Size Description Add the contents of the address location specified by the contents ...

Page 618: ...urce location is pointed to by the contents of register R4 destination location is pointed to by the contents of register R5 Options see also Table 11 13 at Page 11 74 are Source pointer SRC Increment decrement or unchanged Destination pointer SRC Increment decrement or unchanged Counter control CNC see Table 11 13 Block size value CNT0 see Table 11 13 Operation temp zero_ext FPI R 4 value loaded ...

Page 619: ...then R b R b AND R a else NOP Flags N Z AND F Syntax AND F Rb Ra Size Description Perform a bit wise logical AND of the contents of the address location specified by the contents of register Ra and the contents of register Rb place the result in Rb Operation R b R b AND zero_ext FPI R a Flags N Z AND PI Syntax AND PI Ra offset6 Description Perform a bit wise logical AND of the contents of the PRAM...

Page 620: ...specified test value S C then set the carry flag R7 C else clear the carry flag Operation if R a imm5 S C then R7_C 1 else R7_C 0 Flags C CLR Syntax CLR Ra imm5 Description Clear bit imm5 of register Ra to 0 Operation R a imm5 0 Flags None CLR F Syntax CLR F Ra imm5 Size Description Clear bit imm5 of the address location specified through the contents of register Ra to 0 This instruction is execut...

Page 621: ...egister R7 according to the result of the subtraction discard the subtraction result Operation R7_FLAGS Flags R a sign_ext imm6 Flags N Z V C COMP F Syntax COMP F Rb Ra Size Description Subtract the contents of the address location specified by the contents of register Ra from the contents of register Rb set the flags in register R7 according to the result of the subtraction discard the subtractio...

Page 622: ...y the contents of register R5 Options see also Table 11 13 at Page 11 74 are Source pointer SRC Increment decrement or unchanged Destination pointer SRC Increment decrement or unchanged Counter control CNC see Table 11 13 Counter 0 reload value CNT0 see Table 11 13 Data transfer width SIZE byte half word word pointers are incremented decremented based upon SIZE Operation temp zero_ext FPI R 4 valu...

Page 623: ...ion Error Exit DEBUG Syntax DEBUG EDA DAC RTA SDB cc_B Description Conditionally cause a debug event if condition CONDCB is true Optionally stop channel execution SDB 1 and or generate an external debug event EDA 1 Operation if CONDCB True then if EDA 1 then activate BRK_OUT pin if SDB 1 then if RTA 0 then R7_CEN 0 disable further channel invocation else PC PC 1 endif save_context idle endif if DA...

Page 624: ...is section describes the DINIT instruction of the PCP DINIT Syntax DINIT R0 Rb Ra Description Initialize Divide logic ready for divide sequence Rb Ra and Clear R0 If value of Ra is 0 then set V to flag divide by 0 error otherwise clear V If value of Rb is 0 and value of Ra is not 0 then set Z to flag a zero result otherwise clear Z Operation R0 0 Flags Z V ...

Page 625: ...b Ra Description Perform 1 step eight bits of an unsigned 32 by 32 bit divide Rb Ra Shift R0 left by 8 bits copy the most significant byte of Rb into LS byte of R0 Shift Rb left by 8 bits and add R0 divided by Ra Load R0 with the remainder of R0 divided by Ra Operation R0 R0 8 Rb 24 Rb Rb 8 R0 Ra R0 R0 Ra Flags Z INB Syntax INB Rb Ra cc_A Description If CONDCA is true then insert the carry flag R7...

Page 626: ... used to set the channel code entry point in Channel Resume Mode to either the address of the next instruction EP 1 or to the start address of the channel EP 0 The EXIT instruction is finished with a context save operation The EP option is only in effect when Channel Resume operation is globally selected through PCP_CS RCB 0 If PCP_CS RCB 1 Channel restart mode is selected for all channels and the...

Page 627: ...pecified by address16 into the PC and jump to that address If CONDCB is false no operation is performed Operation if CONDCB True then PC address16 else NOP Flags None JC I Syntax JC I Ra cc_B Description If CONDCB is true then add the value specified by Ra 15 0 to the contents of the PC and jump to that address Value Ra 15 0 is treated as a signed 16 bit number If CONDCB is false no operation is p...

Page 628: ... sign_ext offset10 Flags None LD F Syntax LD F Rb Ra Size Description Load the zero extended contents of the address location specified by the contents of register Ra into register Rb Operation R b zero_ext FPI R a Flags N Z LD I Syntax LD I Ra imm6 Description Load the zero extended value specified by imm6 into register Ra Operation R a zero_ext imm6 Flags N Z LD IF Syntax LD IF Ra offset5 Size D...

Page 629: ...ed left by six bits and the zero extended 6 bit value Ra 5 0 into register Rb If condition CONDCA is false no operation is performed Operation if CONDCA True then R b PRAM DPTR 6 zero_ext R a 5 0 else NOP Flags N Z LD PI Syntax LD PI Ra offset6 Description Load the contents of the PRAM location specified by the addition of contents of the PRAM Data Pointer shifted left by six bits and the zero ext...

Page 630: ... lower bits of register Ra bits 15 0 Bits 31 16 of register Ra are unaffected Value imm16 is treated as an unsigned 16 bit number Operation R a 15 0 imm16 Flags N Z LDL IU Syntax LDL IU Ra imm16 Description Load the immediate value imm16 into the upper bits of register Ra bits 31 16 Bits 15 0 of register Ra are unaffected Operation R a 31 16 imm16 Flags N Z MINIT Syntax MINIT R0 Rb Ra Description ...

Page 631: ... V2 0 2007 07 PCP V2 0 11 11 22 MOV Move Register to Register MOV Syntax MOV Rb Ra cc_A Description If condition CONDCA is true then move the contents of register Ra into register Rb If CONDCA is false no operation is performed Operation if CONDCA True then R b R a else NOP Flags N Z ...

Page 632: ... by 8 bits Shift R0 left by 8 bits Add Ra multiplied by the least significant 8 bits of Rb to R0 If value of R0 is zero then set Z to signal zero result else clear Z Operation Rb Rb 8 Rb 24 R0 R0 8 Rb 0xff Ra Flags Z MSTEP64 Syntax MSTEP64 R0 Rb Ra Description Perform an unsigned multiply step using eight bits of data taken from Rb keeping 40 bits of a potential 64 bit result Add Ra multiplied by ...

Page 633: ...ndition CONDCA is true then move the 2 s complement of the contents of register Ra into register Rb If CONDCA is false no operation is performed Operation if CONDCA True then R b R a else NOP Flags N Z V C NOP Syntax NOP Description No operation The NOP instruction puts the PCP in low power operation Operation no operation Flags None NOT Syntax NOT Rb Ra cc_A Description If condition CONDCA is tru...

Page 634: ...hen R b R b OR R a else NOP Flags N Z OR F Syntax OR F Rb Ra Size Description Perform a bit wise logical OR of the contents of the address location specified by the contents of register Ra and the contents of register Rb place the result in Rb Operation R b R b OR zero_ext FPI R a Flags N Z OR PI Syntax OR PI Ra offset6 Description Perform a bit wise logical OR of the contents of the PRAM location...

Page 635: ...ion CONDCA is true then find the bit position of the most significant 1 in register Ra and put the number into register Rb The bit location 31 0 is encoded as a 5 bit number stored in Rb 4 0 If the contents of Ra is zero bit Rb 5 is set while all other bits in Rb are cleared If CONDCA is false no operation is performed Operation if CONDCA False then NOP else if R a 0 then R b 0x20 else R b bit_pos...

Page 636: ...h the contents of the PRAM location specified by the addition of contents of the PRAM Data Pointer shifted left by six bits and the zero extended 6 bit value offset Write the result back to the PRAM location Operation R a R a AND PRAM DPTR 6 offset6 PRAM DPTR 6 offset6 R a Flags N Z MSET Syntax MSET PI Ra offset6 Description Perform an OR of the contents of the specified register with the contents...

Page 637: ...itions specified through the 5 bit value imm5 The values defined for imm5 are 1 2 4 and 8 The carry flag R7 C is set to the last bit shifted out of bit 31 of register Ra Operation tmp R a R a R a imm5 imm5 1 2 4 8 R7_C last bit shifted out of R a tmp tmp 32 imm5 R a tmp OR R a Flags N Z RR Syntax RR Ra imm5 Description Rotate the contents of register Ra to the right by the number of bit positions ...

Page 638: ...ription Set bit imm5 of the address location specified through the contents of register Ra to 1 This instruction is executed using a locked read modify write FPI Bus transaction Operation FPI R a imm5 1 Flags None SHL Syntax SHL Ra imm5 Description Shift the contents of register Ra to the left by the number of bit positions specified through the 5 bit value imm5 The values allowed for imm5 are 1 2...

Page 639: ...ght This section describes the SHR instruction of the PCP SHR Syntax SHR Ra imm5 Description Shift the contents of register Ra to the right by the number of bit positions specified through the 5 bit value imm5 The values allowed for imm5 are 1 2 4 and 8 Zeros are shifted in from left Operation R a R a imm5 imm5 1 2 4 8 Flags N Z ...

Page 640: ...mm5 When the Size is byte or half word the data is stored with the internal LSB bit 0 properly aligned to the correct FPI Bus byte or half word lane Operation FPI R a zero_ext imm5 R 0 Flags None ST P Syntax ST P Rb Ra cc_A Description If condition CONDCA is true then store the contents of Rb to the PRAM address location specified by the addition of the contents of the PRAM Data Pointer shifted le...

Page 641: ...e zero extended immediate value imm6 from the contents of register Ra place the result in Ra Operation R a R a zero_ext imm6 Flags N Z V C SUB F Syntax SUB F Rb Ra Size Description Subtract the zero extended contents of the address location specified by the contents of register Ra from the contents of register Rb place the result in Rb Operation R b R b zero_ext FPI R a Flags N Z V C SUB PI Syntax...

Page 642: ...nternal LSB bit 0 properly aligned to the correct FPI byte or half word lane The exchange is done via a locked FPI bus transfer Operation temp R b R b zero_ext FPI R a FPI R a temp Flags N Z XCH PI Syntax XCH PI Ra offset6 Description Exchange contents of R a and PRAM DPTR 6 offset6 Note The exchange is un interruptible and locks out external accesses it will not be interrupted by any external FPI...

Page 643: ... then R b R b XOR R a else NOP Flags N Z XOR F Syntax XOR F Rb Ra Size Description Perform a bit wise logical Exclusive OR of the contents of the address location specified by the contents of register Ra and the contents of register Rb place the result in Rb Operation R b R b XOR zero_ext FPI R a Flags N Z XOR PI Syntax XOR PI Ra offset6 Description Perform a bit wise logical Exclusive OR of the c...

Page 644: ...1 14 each instruction is shown with the flags that it updates Table 11 14 Flag Updates Instruction CN1Z V C N Z ADD yes yes yes yes AND yes yes BCOPY yes1 CHKB yes CLR COMP yes yes yes yes COPY yes1 DEBUG DINIT yes yes DSTEP yes EXIT yes1 INB JC JL LD yes2 yes LDL yes yes MCLR yes yes MSET yes yes MINIT yes MOV yes yes MSTEP32 yes MSTEP64 yes NEG yes yes yes yes NOP NOT yes yes OR yes yes PRI yes3...

Page 645: ...d clocked with fSYS as module clock fSYSmax 75 MHz resulting in a minimum clock cycle time of 13 3 ns RR yes yes RL yes yes yes SET SHR yes3 yes SHL yes yes yes ST SUB yes yes yes yes XCH yes yes XOR yes yes 1 CN1Z is only modified by the BCOPY COPY or EXIT instructions if the instruction has been configured to decrement R6 CNT1 for BCOPY COPY CNC 1 or CNC 2 for EXIT EC 1 All other instructions ha...

Page 646: ... read 3 OR F 8 min 5 int 3 min for FPI read 3 XOR F 8 min 5 int 3 min for FPI read 3 LD F 8 min 5 int 3 min for FPI read 3 ST F 5 min 2 int 3 min for FPI write 3 XCH F 8 min 4 int 4 min for FPI read and write 3 PRAM Access ADD PI 2 SUB PI 2 COMP PI 2 MCLR PI 4 AND PI 2 MSET PI 4 OR PI 2 XOR PI 2 LD PI 2 ST PI 2 XCH PI 2 Arithmetic Conditional ADD 1 SUB 1 COMP 1 NEG 1 NOT 1 AND 1 Table 11 15 Instru...

Page 647: ...I 1 SHR 1 SHL 1 RR 1 RL 1 LDL IU 1 LDL IL 1 SET 1 CLR 1 LD I 1 INB I 1 CHKB 1 FPI Immediate Access SET F 8 min 4 int 4 min for locked FPI RMW 4 CLR F 8 min 4 int 4 min for locked FPI RMW 4 LD IF 8 min 5 int 3 min for FPI read 3 ST IF 5 min 2 int 3 min for FPI write 5 Complex Maths DINIT 1 6 DSTEP 10 6 Table 11 15 Instruction Timing cont d Instruction Number of Clock Cycles Comments Notes ...

Page 648: ... modify write with 0 wait cycles 1 cycle bus arbitration 5 Cycles 2 internal 3 minimum for FPI write with 0 wait cycles 1 cycle for bus arbitration Time starts after any previous ST F instruction has completed 6 32 32 bit divide requires instruction DINIT JC 4 DSTEP 1 4 2 4 10 45 cycles 8 32 bit divide requires instruction RR DINIT JC DSTEP 1 1 4 2 10 16 cycles 7 32 8 bit multiply requires instruc...

Page 649: ...en the channel program is forced to always start at its Channel Entry Table location regardless of the PC value stored in the CSA If PCP_CS RCB 0 then the channel program will simply begin executing at whatever PC value is restored in the context R7 PC It is important to be aware of the implications of these two approaches on how CMEM should be configured and what the initial value of the PC shoul...

Page 650: ...TART nominal channel start address ST IFbase 0x8 SIZE 32 output note from R0 JC CH16 cc_UC loop back before exit Note that when the channel program is originally configured by the programmer the PC field in the R7 context of this channel program should also be set to the address of the START label Similarly an interrupt driven state machine can be created by exiting with the next PC value pointing...

Page 651: ...e not included in the context must be handled explicitly by channel programs since these are not saved and restored with the context of the interrupted channel program Channel programs may still use all registers reliably Channel programs can be so designed that they either ignore the values in unsaved registers or use those registers to store constants that no channel program changes Hence they n...

Page 652: ...ooping channel program continue operation in the background It will also always be superseded by any higher priority tasks The third approach uses a channel program to dispatch other non interrupt driven channel programs in an arbitrary order determined by the channel program dispatcher In this way multiple tasks could be continuously operated without over using the PCP service request queue This ...

Page 653: ... JL case_4 destination if R3 4 JL case_5 destination if R3 5 11 12 7 Simple DMA Operation A simple interrupt driven DMA requires at least the Small Context Model to operate properly Its operation is comprised of three stages The device interrupts the PCP to indicate it can receive or provide data The PCP moves the amount of data it is programmed to move The PCP eventually finishes and interrupts t...

Page 654: ...imilar to the COPY instruction except that it uses the FPI Burst mode to perform the transfers rather than performing individual reads writes As for the COPY instruction the FPI Bus is locked between the burst read and burst write to ensure that a valid set of data is transferred The BCOPY instruction allows support of all burst sizes supported by FPI Burst Mode except a burst size of 1 i e 2 4 or...

Page 655: ...number PCP_CS RCB and context must be consistent If RCB is configured to 0 then each channel program will start at the PC restored from its context If the wrong address is pre configured in the context the channel program will not operate properly The programmer of the PCP may lock PCP_CS by setting PCP_CS EIE 1 When the global ENDINIT bit is set the PCP_CS register will no longer be writable and ...

Page 656: ...s that is caused by an instruction e g MOV R7 R0 which updates Z and N takes precedence over any explicit bits that are moved to R7 See Page 11 9 The interrupt system assumes SRPN 0 is not a request Full Context packing leaves the least significant 8 32 bit entries where channel 0 would normally be un used That is PRAM Base PRAM Base 1 channel In addition for Small Context the least significant 4 ...

Page 657: ...truction of non interruptible code sequence 11 13 3 2 Control of Channel Priority CPPN The PCP has three extended Service Request Nodes PCP_SRC9 PCP_SRC10 and PCP_SCR11 that allow storage of suspended channel interrupt requests This allows interrupt nesting to a depth of four This limit on the nesting depth carries the danger that a high priority service request will not be serviced because the PC...

Page 658: ...in any group from 1 to 3 a group 2 channel program can only be interrupted by a new service request for a channel in group 3 Note When using this scheme each channel program must ensure prior to channel exit that the R6 CPPN field contains the appropriate value so that when the channel is next invoked it will run at the correct priority ...

Page 659: ...dhere to these conditions will lead to invalid results which are outside the scope of this document During execution of a divide sequence Rb is used both to compile the final divide result and to hold the remnants of the original dividend For example in a 32 32 bit divide sequence which consists of 4 DSTEP instructions see below Rb will have the following content After the 1st DSTEP instruction Th...

Page 660: ...on 1 8 8 bit divide After this sequence R4 holds the result R0 the remainder and R2 is unchanged Note that the above example is specified as being a 8 32 bit divide rather than an 8 8 bit divide see comments above 11 13 5 Implementing Multiply Algorithms As discussed in Section 11 11 4 a multiply algorithm must always start with a MINIT instruction followed by a number of MSTEP32 or MSTEP64 instru...

Page 661: ...2 8 Perform two 8 bit rotations RR instructions to get original least significant 16 bits into most significant 16 bits RR R2 8 MINIT R2 R3 Initialize ready for multiply MSTEP32 R2 R3 Perform two MSTEP32 instructions 16 bit multiply MSTEP32 R2 R3 After this sequence R0 holds the result R2 is left unchanged right rotated by two RR instructions then left rotated by two MSTEP32 instructions R3 is unc...

Page 662: ...nd CMEM memory blocks of the PCP are both equipped with a parity error detection logic that makes it possible to detect parity errors separately for PRAM or CMEM In case of a parity error a NMI is generated Note that before using parity protection for PRAM and CMEM the first time after a power on reset operation before setting the corresponding parity error enable bits the corresponding PCP memori...

Page 663: ...by writing a 1 to bit PCP_CS RST see also Page 11 56 A PCP soft reset differs from the PCP hard reset in that the interrupt system is not reset Specifically all PCP interrupt nodes with their service request control registers are not completely reset and the PICU is also not affected The PCP soft reset is adopted to prevent loss of synchronization between any interrupt node and the Arbitration Uni...

Page 664: ...ecommended to use the PCP soft reset capability in a PCP application program A PCP hard reset should be generated instead 11 14 4 BCOPY Instruction In the TC1796 the BCOPY instruction can be used to perform burst transfers 2 4 or 8 words with DMI memories Local data RAM and Dual port RAM and the PCP memories Other internal and external memories can be accessed using a burst size of 2 words only CN...

Page 665: ...roller and the Memory Checker Module MCHK of the TC1796 It contains the following sections Functional description of the DMA controller kernel see Page 12 2 DMA controller kernel register description see Page 12 42 TC1796 implementation specific details of the DMA controller interrupt control address decoding clock control see Page 12 91 Functional description of the MCHK module see Page 12 110 ...

Page 666: ... The third specific bus interface provides a connection to Micro Link Interface modules two MLI modules in the TC1796 and other DMA related devices Memory Checker module in the TC1796 Clock control address decoding DMA request wiring and DMA interrupt service request control are implementation specific and managed outside the DMA controller kernel Figure 12 1 DMA Block Diagram MCB05680 fDMA SR 15 ...

Page 667: ...ned number of DMA transfers Continuous Mode DMA channel remains enabled after a predefined number of DMA transfers DMA transaction can be repeated Programmable address modification Full 32 bit addressing capability of each DMA channel 4 Gbyte address range Support of circular buffer addressing mode Programmable data width of DMA transfer transaction 8 bit 16 bit or 32 bit Micro Link bus interface ...

Page 668: ...ly stored in the DMA controller The data width of read move and write move are always identical 8 bit 16 bit or 32 bit Data assembly or disassembly is not supported Figure 12 2 DMA Definition of Terms DMA Transfer A DMA transfer can be composed of 1 2 4 8 or 16 DMA moves DMA Transaction A DMA transaction is composed of several at least one DMA transfers The Transfer Count determines the number of ...

Page 669: ...e occurrence of a receive or transmit data interrupts in a peripheral module are able to generate a DMA request in parallel to an interrupt request Therefore the interrupt control unit and the DMA controller can react independently to interrupt and DMA requests that have been generated by one source Figure 12 3 DMA Principle The DMA controller mainly consists of two DMA Sub Blocks and a Bus Switch...

Page 670: ... into another memory buffer While the destination address register is updated during a running DMA transaction with the actual destination address a shadow mechanism allows programming of a new destination address without disturbing the content of the destination address register In this case the new destination address is written into a buffer registers i e the shadow address register At the star...

Page 671: ...stination address At the start of the next DMA transaction the shadow transfer takes place and the content of SHADRmn is written either into SADRmn or DADRmn ADRCRmn SHCT must be set accordingly After the shadow transfer SHADRmn is set to 0000 0000H Therefore the software can check by reading the shadow address register whether or not the shadow transfer has already taken place Only one address re...

Page 672: ...ring the DMA transaction No reload of address or counter will be done if TCOUNT is not equal to 0 The reprogramming of channel specific values except for the selected address shadow register should be avoided while a DMA channel is active MCA05683 Write new source address to address of SADRmn yes New transaction started ADRCRmn SHCT 01B no no Content of SHADRmn is transferred into SADRmn and SHADR...

Page 673: ...channel is reprogrammed with two new parameters for the next DMA transaction Transfer count tc2 and source address sa2 Source address sa2 is buffered in SADRmn and transferred to SADRmn when the new DMA transaction is started at 2 At this time transfer count tc2 is also transferred to CHSRmn TCOUNT tc2 MCT05684_mod CHSRmn TCOUNT tc1 transfer count 1 tc2 transfer count 2 sa1 source address 1 sa2 so...

Page 674: ...le Mode at the end of a DMA transaction A software request can be generated by setting bit STREQ SCH0n Status flag TRSR CHmn indicates whether or not a software or hardware generated DMA request for DMA channel mn is pending TRSR CHmn can be cleared by software or by hardware at the end of a DMA transfer RROAT 0 or at the end of a DMA transaction RROAT 1 M U X MCA05685c TRSR Transfer Request To Ch...

Page 675: ... DMA channel mn remains enabled after the last DMA transfer of its DMA transaction In hardware and software controlled mode a DMA request signal can be configured to trigger a complete DMA transaction or one single transfer Software controlled Modes In software controlled mode one software request starts one complete DMA transaction or one single DMA transfer Software controlled modes are selected...

Page 676: ...mes cleared after each DMA transfer of the DMA transaction and a new software request writing STREQ SCHmn 1 must be generated for starting the next DMA transfer Figure 12 7 Software controlled Mode Operation TR0 TR1 TRn tc 1 tc initial transfer count TR0 TR1 0 tc 1 0 tc tc 1 MCT05686 TR0 TR1 TRn tc initial transfer count 0 tc 0 CHCRmn RROAT 1 CHCRmn RROAT 0 1 tc 1 CHSRmn TCOUNT DMA Transfer mn TRS...

Page 677: ...enabled TRSR HTREmn 1 Once the hardware request CHmn_REQ becomes active the value of CHCRmn TREL is loaded into CHSRmn TCOUNT and the DMA transaction is started by executing its first DMA transfer After each DMA transfer TCOUNT becomes decremented and next source and destination addresses are calculated When TCOUNT reaches the 0 DMA channel mn becomes disabled and status flags TRSR CHmn and TRSR H...

Page 678: ...rameters actually stored in the channel register set of DMA channel mn is started each time when CHSRmn TCOUNT reaches 000H No software re enable for a hardware request at CHmn_REQ is required MCT05687 tc initial transfer count tc initial transfer count CHCRmn RROAT 1 CHCRmn RROAT 0 TR0 TR1 TRn tc 1 TR0 TR1 0 tc tc 1 0 1 tc TR0 tc 1 tc TR1 TRn 1 TRn 0 0 2 1 tc TR0 TRSR HTREmn CHmn_REQ INT triggere...

Page 679: ... 0 at the end of the DMA transaction Figure 12 9 Transaction Start by Software Continuation by Hardware 12 1 4 4 Error Conditions The source move error flag ERRSR FPI0SER indicates an FPI Bus error on bus 0 SPB that occurred during a source move read of a DMA transaction The destination move error flag ERRSR FPI0DER indicates an FPI Bus error on bus 0 SPB that occurred during a destination move wr...

Page 680: ...egister will be set to the wrap boundary SHADRmn will be cleared All automatic functions are stopped for channel mn A user program must execute the following steps for resetting a DMA channel 1 If hardware requests are enabled for the DMA channel mn disable the DMA channel mn hardware requests by setting HTREQ ECHmn 0 2 Writing a 1 to CHRST CHmn 3 Waiting polling until CHRST CHmn 0 A user program ...

Page 681: ...ce and destination addresses are calculated independently from each other The following address calculation parameters can be selected The address offset which is a multiple of the selected data width The offset direction addition subtraction or none unchanged address Control bits in address control register ADRCRmn determine how the addresses are incremented decremented Further the data width as ...

Page 682: ...estination memory with decrementing destination addresses offset of 08H In Figure 12 12 16 bit half words are transferred from a source memory with an incrementing source address offset of 02H to a destination memory with incrementing destination addresses offset of 04H MCA05690 ADRCRmn Parameters SMF 011B INCS 1 Source Memory Destination Memory 00H D1 D0 31 0 15 16 DMA Moves 04H 08H 0CH 10H 14H 1...

Page 683: ...uffer sizes of the circular buffers can be 2CBLS or 2 CBLD bytes 1 2 4 8 16 up to 32k bytes When source or destination addresses are updated incremented or decremented after a DMA move all upper bits 31 CBLS of source address and 31 CBLD of destination address are frozen and remain unchanged even if a wrap around from the lower address bits CBLS 0 or CBLD 0 occurred This address freezing mechanism...

Page 684: ...mber n is serviced first The Move Engine handles the execution of a DMA transfer that has been detected by the Channel Arbiter to be the next one The Move Engine requests the required buses and loads or stores data according to the parameters of a DMA transfer It is able to wait if a targeted bus is not available In the Move Engine a DMA transfer of a DMA transaction cannot be interrupted and alwa...

Page 685: ... DMA because all the other interfaces are master on their buses The slave interface also provides the access to the DMA and MLI registers The bridge functionality is covered independently from the DMA Move Engines An access requesting from the FPI Bus interface 0 SPB to locations on the FPI Bus interface 1 RPB has priority over DMA actions The DMA Move Engines are not involved in bridge transfers ...

Page 686: ...ne in SV mode The DMA bridge functionality from the FPI Bus 0 to FPI Bus 1 to the MLI modules or to the memory checker does not support read modify write instructions DMA Bus Bandwidth Allocation The Move Engines in the two DMA Sub Blocks use a programmable priority scheme in the switch The transfers currently requesting the master interface s of the DMA are internally arbitrated according to thei...

Page 687: ...communication of the DMA controller via its Bus Switch is blocked Hard suspend Mode can only be left by a reset operation Attention The Hard suspend Mode is mainly applicable for test purposes only It can only be exit by a reset operation and should not be used during normal operation of the DMA controller 12 1 7 2 Soft suspend Mode The TC1796 on chip debug control unit is able to generate a Soft ...

Page 688: ...t lines of the two break conditions in each DMA Sub Block are OR ed together to the BREAK output signal A transaction lost break condition occurs in DMA Sub Block m whenever at least one of its eight transaction lost interrupts becomes active and when enable bit OCDSR BRLm is set The transaction lost interrupts do not generate a break condition if OCDSR BRLm 0 Transaction interrupt control is desc...

Page 689: ...for monitoring the status flags and bit fields of register DMA_MESR Channel trace and Move Engine trace outputs are selected by bit TRCDS in the OSCU Configuration and Control Register OCNTRL The selected DMA trace is further enabled to the trace output lines TR 15 0 by bit OCNTRL TRCDEN The information that is output on the TR 15 0 trace port lines is shown in the following diagram TRSR CH01 BREA...

Page 690: ...6 bit DMA Channel Transaction Request Trace Figure 12 18 16 bit Move Engine Status Information Trace TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 0 CH 07 CH 06 CH 01 CH 00 CH 02 CH 03 CH 04 CH 05 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 0 RBT0 CH0 ME0 RS ME0 WS RBT1 ...

Page 691: ...pts Each DMA channel mn has one associated channel interrupt It can always be activated after a DMA transfer or when CHSRmn TCOUNT matches with the value of bit field CHSRmn IRDV after it has been decremented after a DMA transfer The pattern detection interrupts that are combined with the channel interrupts one common Interrupt Node Pointer CHICRmn INTP are activated when the pattern detection int...

Page 692: ...A channel mn is enabled when bit CHICRmn PATSEL is set to a value not equal to 00B The channel interrupt pointer CHICRmn INTP determines which of the interrupt outputs SR 15 0 1 will be activated on a pattern detection or channel interrupt Figure 12 19 Channel Interrupts 1 In the TC1796 only SR 7 0 are connected to interrupt nodes MCA05696_mod CHSRmn TCOUNT Decremented INTP CHICRmn INTCR CHSRmn TC...

Page 693: ...ne common transaction lost interrupt that can be directed to one of the interrupt outputs SR 15 0 1 by setting the transaction lost interrupt pointer EER TRLINP with a corresponding value A transaction request lost condition of DMA channel mn is indicated by status flag ERRSR TRLmn which can be cleared by setting bit CLRE CTLmn or CHRSTR CHmn The transaction lost interrupt for DMA channel mn is en...

Page 694: ...ER can be cleared by software when setting bit CLRE CMEmSER The source error interrupt of Move Engine m is enabled when bit EER MEmSER is set Separate clear status and enable bits are also available in each of the Move Engines for the destination error condition Each of the two Move Engine interrupts can be directed to one of the interrupt outputs SR 15 0 1 by setting the Move Engine interrupt poi...

Page 695: ... status conditions At which FPI Bus interface a Move Engine m error occurred FPI0ER and FPI1ER For which DMA channel a Move Engine m read or write move error was reported LECME0 and LECME1 These error status bits and bit fields are required by error handler software to detect in detail at which FPI Bus interface and at which DMA channel the Move Engine error was generated ERRSR FPI0ER or ERRSR FPI...

Page 696: ...nterrupt is enabled when bit CHICRmn WRPSE is set The wrap destination buffer interrupt is enabled when bit CHICRmn WRPDE is set The two interrupts for wrap source buffer and wrap destination buffer are OR ed together to one common wrap buffer interrupt of DMA channel mn that can be directed to one of the interrupt outputs SR 15 0 1 by setting the wrap buffer interrupt pointer CHICRmn WRPP with a ...

Page 697: ... outputs SR 15 0 1 by a 4 bit Interrupt Node Pointer This allows also to connect more than one interrupt source to one interrupt output SRx Each interrupt output SR 15 0 can also be activated by writing a 1 to the corresponding bit GINTR SIDMAx Figure 12 23 DMA Interrupt Request Compressor 1 In the TC1796 only SR 7 0 are connected to interrupt nodes MCA05700 INTP CHICRmn 4 DMA Channel mn Interrupt...

Page 698: ...PR its compare patterns are used for all DMA channels that are assigned to Move Engine m all DMA channels of the DMA Sub Block m The configuration and capabilities of the pattern detection logic further depends on the settings of CHCRmn CHDW CHDW determines the data width for the read and write moves individually for each DMA channel mn Another control bit CHCRmn PATSEL selects among the different...

Page 699: ...a data bit from register MEmR is compared to the corresponding pattern bit stored in register MEmPR If both bits are equal and a pattern mask bit stored in another part of register MEmPR is 0 the compare matched condition becomes active When the pattern mask bit is set to 1 the compare matched condition is always active set for the related bit When the compare matched conditions for each bit withi...

Page 700: ...it data stream coming from a serial peripheral unit with 8 bit data width e g recognition of carriage return line feed characters A mask operation of each compared bit is possible Figure 12 25 Pattern Detection for 8 bit Data Width CHCRmn CHDW 00B Table 12 2 Pattern Detection for 8 bit Data Width CHCRmn PATSEL Pattern Detection Operating Modes 00B Pattern detection disabled 01B Pattern compare RDm...

Page 701: ... current and the high byte RDm1 of the previous 16 bit read move are compared If it is not known on which byte boundary even or odd address the 16 bit pattern to be detected is located the combined mode should be used This mode is the most flexible mode that combines the pattern search capability for aligned and un aligned 16 bit data searches Table 12 3 Pattern Detection for 16 bit Data Width CHC...

Page 702: ...tern Detection for 16 bit Data Width CHCRmn CHDW 01B 0 0 MCA05703 PATm3 PATm2 PATm1 PATm0 31 2 PATSEL CHCRmn Pattern Detected 0 LXO CHSRmn MEmPR COMP RDm3 RDm2 RDm1 RDm0 31 15 16 MEmR COMP COMP 1 This signal is clocked into LXO after each read move 1 0 1 INCS ADRCRmn 15 16 7 8 24 7 8 23 24 0 1 Mask Mask Mask 1 00 01 10 11 ...

Page 703: ...d only the upper half word only or the complete 32 bit word with a pattern stored in the MEmPR register A mask operation is not possible Figure 12 27 Pattern Detection for 32 bit Data Width CHCRmn CHDW 10B Table 12 4 Pattern Detection for 32 bit Data Width CHCRmn PATSEL Pattern Detection Operating Modes 00B Pattern detection disabled 01B Unmasked pattern compare RDm 1 0 to PATm 1 0 10B Unmasked pa...

Page 704: ...ges within four of the fixed address ranges The parameters for the four sub ranges are stored in the Move Engine m access range register MEmARR The programmable address range extension is a feature that is applicable for memory access protection of memory blocks In such an application several memory sections are defined as sub ranges of a complete memory block Figure 12 28 shows the two levels of ...

Page 705: ... 0 Variable Address a 1 SIZE 111B Variable Address a 2 Variable Address a 3 0 Variable Address a 4 0 4 Variable Address a 5 0 5 Variable Address a 6 0 31 a 5 a 7 0 0 5 Variable Address a 8 0 Fixed Address Fixed Address 31 Fixed Address 31 Fixed Address 31 Fixed Address 31 Fixed Address 31 Fixed Address 31 Variable Address 1 This bit is defined by SLICE 0 2 These 2 bits are defined by SLICE 1 0 3 T...

Page 706: ... the DMA module kernel register descriptions This index is represented by n for DMA channel numbering in the functional description For example an index reference mx is equivalent to index mn Index m m 0 1 refers to the DMA Sub Blocks and indexes n and x n x 0 7 refer to the DMA channels Table 12 5 Registers Address Space DMA Kernel Registers Module Base Address End Address Note DMA F000 3C00H F00...

Page 707: ...LRE DMA Clear Error Register 028H Page 12 62 DMA_GINTR DMA Global Interrupt Set Register 02CH Page 12 50 DMA_MESR DMA Move Engine Status Register 030H Page 12 69 DMA_MEmR Move Engine m Read Register m 0 1 34H m 4 Page 12 71 DMA_MEmPR Move Engine m Pattern Register m 0 1 3CH m 4 Page 12 72 DMA_ MEmAENR Move Engine m Access Enable Register m 0 1 44H m 8 Page 12 73 DMA_ MEmARR Move Engine m Access Ra...

Page 708: ...ontrol Register m 0 1 x 0 7 m 8 x 20H 8CH Page 12 83 DMA_SADRmx DMA Channel mx Source Address Register m 0 1 x 0 7 m 8 x 20H 90H Page 12 88 DMA_DADRmx DMA Channel mx Destination Address Register m 0 1 x 0 7 m 8 x 20H 94H Page 12 89 DMA_ SHADRmx DMA Channel mx Shadow Address Register m 0 1 x 0 7 m 8 x 20H 98H Page 12 90 1 The absolute register address is calculated as follows Module Base Address Ta...

Page 709: ...tification Register 008H Reset Value 001A C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines...

Page 710: ...s bit field determines the transition type for the transaction request bit TRSR CH0x that leads to a break condition in DMA Sub Block 0 00B No break condition is generated 01B A break condition is generated when TRSR CH0x changes from 0 to 1 10B A break condition is generated when TRSR CH0x changes from 1 to 0 11B A break condition is generated when TRSR CH0x changes its state BCHS0 4 2 rw Break C...

Page 711: ...R CH1x changes from 0 to 1 10B A break condition is generated when TRSR CH1x changes from 1 to 0 11B A break condition is generated when TRSR CH1x changes its state BCHS1 12 10 rw Break Channel Select In Sub Block 1 This bit field determines the DMA channel n of DMA Sub Block 1 whose transaction request bit TRSR CH1x is observed for signal transitions as defined by BTRC1 000B DMA channel 10 select...

Page 712: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SUS EN 17 SUS EN 16 SUS EN 15 SUS EN 14 SUS EN 13 SUS EN 12 SUS EN 11 SUS EN 10 SUS EN 07 SUS EN 06 SUS EN 05 SUS EN 04 SUS EN 03 SUS EN 02 SUS EN 01 SUS EN 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description SUSEN0x x 0 7 x rw Suspend Enable for DMA Channel 0x This bit enables the soft suspend capability individually for each DMA chan...

Page 713: ...stopped after the current DMA transfer has been finished Soft suspend Mode can be terminated when SUSEN1x is written with 0 SUSAC0x x 0 7 16 x rh Suspend Active for DMA Channel 0x This status bit indicates whether DMA channel 0x is in Soft suspend Mode or not 0B DMA channel 0x is not in Soft suspend Mode or internal actions are not yet finished after the Soft suspend Mode was requested 1B DMA chan...

Page 714: ...al Interrupt Set Register 02CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI DMA 15 SI DMA 14 SI DMA 13 SI DMA 12 SI DMA 11 SI DMA 10 SI DMA 9 SI DMA 8 SI DMA 7 SI DMA 6 SI DMA 5 SI DMA 4 SI DMA 3 SI DMA 2 SI DMA 1 SI DMA 0 w w w w w w w w w w w w w w w w Field Bits Type Description SIDMAx x 0 15 x w Set DMA Interrupt Output Lin...

Page 715: ... CH0x x 0 7 x rwh Channel 0x Reset These bits force the DMA channel 0x to stop its current DMA transaction Once set by software this bit will be automatically cleared when the channel has been reset Writing a 0 to CH0x has no effect 0B No action write or the requested channel reset has been reset read 1B DMA channel 0x is stopped More details see Page 12 16 CH1x x 0 7 8 x rwh Channel 1x Reset Thes...

Page 716: ...HT RE 04 HT RE 03 HT RE 02 HT RE 01 HT RE 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH 17 CH 16 CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 07 CH 06 CH 05 CH 04 CH 03 CH 02 CH 01 CH 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description CH0x x 0 7 x rh Transaction Request State of DMA Channel 0x 0B No DMA request is pending for chan...

Page 717: ...d and CHSR0x TCOUNT 0 HTRE0x can be enabled and disabled with HTREQ ECH0x or HTREQ DCH0x HTRE0x is cleared when a pattern match is detected HTRE1x x 0 7 24 x rh Hardware Transaction Request Enable State of DMA Channel 1x 0B Hardware transaction request for DMA Channel 1x is disabled An input DMA request will not trigger the channel 1x 1B Hardware transaction request for DMA Channel 1x is enabled T...

Page 718: ...6 5 4 3 2 1 0 SCH 17 SCH 16 SCH 15 SCH 14 SCH 13 SCH 12 SCH 11 SCH 10 SCH 07 SCH 06 SCH 05 SCH 04 SCH 03 SCH 02 SCH 01 SCH 00 w w w w w w w w w w w w w w w w Field Bits Type Description SCH0x x 0 7 x w Set Transaction Request for DMA Channel 0x 0B No action 1B A transaction for DMA channel 0x is requested When setting SCH0x TRSR CH0x becomes set to indicate that a DMA request is pending for DMA ch...

Page 719: ...CH 15 ECH 14 ECH 13 ECH 12 ECH 11 ECH 10 ECH 07 ECH 06 ECH 05 ECH 04 ECH 03 ECH 02 ECH 01 ECH 00 w w w w w w w w w w w w w w w w Field Bits Type Description ECH0x x 0 7 x w Enable Hardware Transfer Request for DMA Channel 0x ECH1x x 0 7 8 x w Enable Hardware Transfer Request for DMA Channel 1x DCH0x x 0 7 16 x w Disable Hardware Transfer Request for DMA Channel 0x DCH1x x 0 7 24 x w Disable Hardwa...

Page 720: ...s Type Description ETRL0x x 0 7 x rw Enable Transaction Request Lost for DMA Channel 0x This bit enables the generation of an interrupt when the set condition for ERRSR TRL0x is detected 0B The interrupt generation for a request lost event for channel 0x is disabled 1B The interrupt generation for a request lost event for channel 0x is enabled ETRL1x x 0 7 8 x rw Enable Transaction Request Lost fo...

Page 721: ...r interrupt is enabled EME1DER 19 rw Enable Move Engine 0 Destination Error This bit enables the generation of a Move Engine 0 destination error interrupt 0B Move Engine 1 destination error interrupt is disabled 1B Move Engine 1 destination error interrupt is enabled ME0INP 23 20 rw Move Engine 0 Error Interrupt Node Pointer ME0INP determines the number n n 0 15 of the service request output SRn t...

Page 722: ...cted for Move Engine 1 interrupt 1111B SR15 selected for Move Engine 1 interrupt Note In the TC1796 only SR 7 0 are connected to interrupt nodes TRLINP 31 28 rw Transaction Lost Interrupt Node Pointer TRLINP determines the number n n 0 15 of the service request output SRn that becomes active on a transaction lost interrupt 0000B SR0 selected for transaction lost interrupt 0001B SR1 selected for tr...

Page 723: ...RL 16 TRL 15 TRL 14 TRL 13 TRL 12 TRL 11 TRL 10 TRL 07 TRL 06 TRL 05 TRL 04 TRL 03 TRL 02 TRL 01 TRL 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description TRL0x x 0 7 x rh Transaction Transfer Request Lost of DMA Channel 0x 0B No request lost event has been detected for DMA channel 0x 1B A new DMA request was detected while TRSR CH0x 1 request lost event This bit is cleare...

Page 724: ... destination error has occurred ME1SER 18 rh Move Engine 1 Source Error This bit is set whenever a Move Engine 1 error occurred during a source read move of a DMA transfer or a request could not been serviced due to the access protection 0B No Move Engine 1 source error has occurred 1B A Move Engine 1 source error has occurred ME1DER 19 rh Move Engine 1 Destination Error This bit is set whenever a...

Page 725: ...ng to an FPI Bus error that has occurred MLI0 27 rh MLI0 Error Source This bit is set whenever an FPI Bus error occurred due to an action of MLI0 0B No FPI error occurred due to MLI0 1B An FPI error occurred due to MLI0 LECME1 30 28 rh Last Error Channel Move Engine 1 This bit field indicates the channel number of the last channel of Move Engine 1 leading to an FPI Bus error that has occurred MLI1...

Page 726: ...L 02 CTL 01 CTL 00 w w w w w w w w w w w w w w w w Field Bits Type Description CTL0x x 0 7 x w Clear Transaction Request Lost for DMA Channel 0x 0B No action 1B Clear DMA channel 0x transaction request lost flag ERRSR TRL0x CTL1x x 0 7 8 x w Clear Transaction Request Lost for DMA Channel 1x 0B No action 1B Clear DMA channel 1x transaction request lost flag ERRSR TRL1x CME0SER 16 w Clear Move Engin...

Page 727: ...on 1B Clear error flag ERRSR FPI0ER CFPI1ER 21 w Clear RPB Error 0B No action 1B Clear error flag ERRSR FPI1ER CLRMLI0 27 w Clear MLI0 Error 0B No action 1B Clear error flag ERRSR MLI0 CLRMLI1 31 w Clear MLI1 Error 0B No action 1B Clear error flag ERRSR MLI1 0 26 22 30 28 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 728: ...CH 13 ICH 12 ICH 11 ICH 10 ICH 07 ICH 06 ICH 05 ICH 04 ICH 03 ICH 02 ICH 01 ICH 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description ICH0x x 0 7 x rh Interrupt from Channel 0x This bit indicates that channel 0x has raised an interrupt for TCOUNT IRDV or if TCOUNT has been decremented depending on CHICR INTCT 0 This bit and IP0x is cleared by software when writing a 1 to I...

Page 729: ...n writing a 1 to INTCR CICH0x or by a channel reset writing CHRSTR CH0x 1 0B A pattern has not been detected 1B A pattern has been detected IPM1x x 0 7 24 x rh Pattern Detection from Channel 1x This bit indicates that a pattern has been detected for channel 1x while the pattern detection has been enabled This bit and ICH1x is cleared by software when writing a 1 to INTCR CICH1x or by a channel res...

Page 730: ... rh rh rh rh rh rh rh rh rh rh Field Bits Type Description WRPS0x x 0 7 x rh Wrap Source Buffer for Channel 0x These bits indicate which channels have done a wrap around of their source buffer s 0B No wrap around occurred for channel 0x 1B A wrap around occurred for channel 0x This bit is cleared by software by writing a 1 to INTCR CWRP0x or CHRSTR CH0x WRPS1x x 0 7 8 x rh Wrap Source Buffer for C...

Page 731: ...Interrupt Clear Register 058H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C WRP 17 C WRP 16 C WRP 15 C WRP 14 C WRP 13 C WRP 12 C WRP 11 C WRP 10 C WRP 07 C WRP 06 C WRP 05 C WRP 04 C WRP 03 C WRP 02 C WRP 01 C WRP 00 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C ICH 17 C ICH 16 C ICH 15 C ICH 14 C ICH 13 C ICH 12 C ICH 11 C ICH 10 C ICH 07 C IC...

Page 732: ... 0x These bits make it possible to clear the wrap source buffer interrupt flag WRPSR WRPS0x and the wrap destination buffer interrupt flag WRPSR WRPD0x both together of DMA channel 0x by software 0B No action 1B Bits WRPSR WRPS0x and WRPSR WRPD0x are cleared CWRP1x x 0 7 24 x w Clear Wrap Buffer Interrupt for DMA Channel 1x These bits make it possible to clear the wrap source buffer interrupt flag...

Page 733: ...27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RBT1 ME1 WS CH1 ME1 RS RBT0 ME0 WS CH0 ME0 RS rh rh rh rh rh rh rh rh Field Bits Type Description ME0RS 0 rh Move Engine 0 Read Status 0B Move Engine 0 is not performing a read 1B Move Engine 0 is performing a read CH0 3 1 rh Reading Channel in Move Engine 0 This bit field indicates which channel number is currently bein...

Page 734: ... 1B Move Engine 1 is performing a read CH1 11 9 rh Reading Channel in Move Engine 1 These bit field indicates which channel number is currently being processed by the Move Engine 1 ME1WS 12 rh Move Engine 1 Write Status 0B Move Engine 1 is not performing a write 1B Move Engine 1 is performing a write RBT1 15 13 rh Read Buffer Trace for FPI Bus Interface 1 This bit field contains trace information ...

Page 735: ...x PATSEL DMA_ME0R DMA Move Engine 0 Read Register 034H Reset Value 0000 0000H DMA_ME1R DMA Move Engine 1 Read Register 038H Reset Value 0000 0000H 31 24 23 16 15 8 7 0 RDm3 RDm2 RDm1 RDm0 rh rh rh rh Field Bits Type Description RDm0 RDm1 RDm2 RDm3 7 0 15 8 23 16 31 24 rh Read Value for Move Engine m Contains the 32 bit read data four bytes RDm 3 0 that is stored in the Move Engine m after each rea...

Page 736: ...lue 0000 0000H DMA_ME1PR DMA Move Engine 1 Pattern Register 040H Reset Value 0000 0000H 31 24 23 16 15 8 7 0 PATm3 PATm2 PATm1 PATm0 rw rw rw rw Field Bits Type Description PATm0 PATm1 PATm2 PATm3 7 0 15 8 23 16 31 24 rw Pattern for Move Engine m Determines up to four 8 bit compare patterns mask patterns to be processed by the pattern detection logic in Move Engine m Depending on the pattern detec...

Page 737: ... 30 AEN 29 AEN 28 AEN 27 AEN 26 AEN 25 AEN 24 AEN 23 AEN 22 AEN 21 AEN 20 AEN 19 AEN 18 AEN 17 AEN 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AEN 15 AEN 14 AEN 13 AEN 12 AEN 11 AEN 10 AEN 9 AEN 8 AEN 7 AEN 6 AEN 5 AEN 4 AEN 3 AEN 2 AEN 1 AEN 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description AENn n 0 31 n rw Address Range x E...

Page 738: ...24 23 22 21 20 19 18 17 16 SIZE3 SLICE3 SIZE2 SLICE2 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE1 SLICE1 SIZE0 SLICE0 rw rw rw rw Field Bits Type Description SLICE0 4 0 rw Address Slice 0 SLICE0 selects a specific sub range within address range extension 0 SIZE0 7 5 rw Address Size 0 SIZE0 determines the sub range size within address range extension 0 SLICE1 12 8 rw Address Slice 1 SLIC...

Page 739: ...s range and address range extension definitions SIZE2 23 21 rw Address Size 2 SIZE2 determines the sub range size within address range extension 2 SLICE3 28 24 rw Address Slice 3 SLICE3 selects a specific sub range within address range extension 3 SIZE3 31 29 rw Address Size 3 SIZE3 determines the sub range size within address range extension 3 Field Bits Type Description ...

Page 740: ...0 PATSEL 0 CHDW CH MO DE RRO AT BLKM r rw r rw r rw r rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRSEL 0 TREL rw r rw Field Bits Type Description TREL 8 0 rw Transfer Reload Value This bit field contains the number of DMA transfers for s DMA transaction of DMA channel mx This 9 bit transfer count value is loaded into CHSRmx TCOUNT at the start of a DMA transaction when TRSR CHmx becomes set...

Page 741: ...ode BLKM determines the number of DMA moves executed during one DMA transfer 000B One DMA transfer has 1 DMA moves 001B One DMA transfer has 2 DMA moves 010B One DMA transfer has 4 DMA moves 011B One DMA transfer has 8 DMA moves 100B One DMA transfer has 16 DMA moves others Reserved do not use these combinations See also Figure 12 10 on Page 12 17 RROAT 19 rw Reset Request Only After Transaction R...

Page 742: ...th for moves selected 10B 32 bit word data width for moves selected 11B Reserved PATSEL 25 24 rw Pattern Select This bit field selects the mode of the pattern detection logic Depending on the channel data width PATSEL selects different pattern detection configurations If pattern detection is enabled PATSEL not equal 00B the pattern detection interrupt line will be activated an the selected pattern...

Page 743: ...ration related to channel mx is requesting FPI Bus 0 The value of DMAPRIO is also used for the DMA internal arbitration between the Move Engines of the DMA This bit has no effect in the channel prioritization and in the prioritization between the Move Engines 0B Low priority selected 1B High priority selected 0 12 9 23 27 26 29 31 r Reserved Read as 0 should be written with 0 Field Bits Type Descr...

Page 744: ... Transfer Count Status TCOUNT holds the actual value of the DMA transfer count for DMA channel mx TCOUNT is loaded with the value of CHCRmx TREL when TRSR CHmx becomes set and TCOUNT 0 After each DMA transfer TCOUNT is decremented by 1 LXO 15 rh Old Value of Pattern Detection This bit contains the compare result of a pattern compare operation when 8 bit or 16 bit data width is selected 8 bit data ...

Page 745: ...w rw Field Bits Type Description WRPSE 0 rw Wrap Source Enable 0B Wrap source buffer interrupt disabled 1B Wrap source buffer interrupt enabled WRPDE 1 rw Wrap Destination Enable 0B Wrap destination buffer interrupt disabled 1B Wrap destination buffer interrupt enabled INTCT 3 2 rw Interrupt Control 00B No interrupt will be generated on changing the TCOUNT value The bit INTSR ICHmx is set when TCO...

Page 746: ...selected for channel mx wrap buffer interrupt 0001B SR1 selected for channel mx wrap buffer interrupt B 1111B SR15 selected for channel mx wrap buffer interrupt Note In the TC1796 only SR 7 0 are connected to interrupt nodes INTP 11 8 rw Interrupt Pointer INTP determines the number n n 0 15 of the service request output SRn that becomes active on a channel interrupt 0000B SR0 selected for channel ...

Page 747: ... 18CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SHCT r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBLD CBLS INCD DMF INCS SMF rw rw rw rw rw rw Field Bits Type Description SMF 2 0 rw Source Address Modification Factor This bit field and the data width as defined in CHCRmx CHDW determine an address offset value by which the source address is modified after each DMA move...

Page 748: ...offset value by which the destination address is modified after each DMA move The destination address is not modified if CBLD 0000B See also Table 12 8 000B Address offset is 1 CHDW 001B Address offset is 2 CHDW 010B Address offset is 4 CHDW 011B Address offset is 8 CHDW 100B Address offset is 16 CHDW 101B Address offset is 32 CHDW 110B Address offset is 64 CHDW 111B Address offset is 128 CHDW INC...

Page 749: ... 31 3 is not updated B 1110B Source address SADR 31 14 is not updated 1111B Source address SADR 31 15 is not updated CBLD 15 12 rw Circular Buffer Length Destination This bit field determines which part of the 32 bit destination address register remains unchanged and is not updated after a DMA move operation see also Page 12 19 Therefore CBLD also determines the size of the circular destination bu...

Page 750: ...y 01B Shadow address register used for source address buffering When writing to SADRmx the address is buffered in SHADRmx and transferred to SADRmx with the start of the next DMA transaction 10B Shadow address register used for destination address buffering When writing to DADRmx the address is buffered in SHADRmx and transferred to DADRmx with the start of the next DMA transaction 11B Reserved In...

Page 751: ...ved and should not be used Table 12 8 Address Offset Calculation Table CHCRmx CHDW 00B 8 bit Data Width CHCRmx CHDW 01B 16 bit Data Width CHCRmx CHDW 10B 32 bit Data Width SMF DMF INCS INCD Address Offset SMF DMF INCS INCD Address Offset SMF DMF INCS INCD Address Offset 000B 0 1 000B 0 2 000B 0 4 1 1 1 2 1 4 001B 0 2 001B 0 4 001B 0 8 1 2 1 4 1 8 010B 0 4 010B 0 8 010B 0 16 1 4 1 8 1 16 011B 0 8 0...

Page 752: ...RSR CHmx 0 If DMA channel mx is active when writing to SADRmx the source address will not be written into SADRmx directly but will be buffered in the shadow register SHADRmx until the start of the next DMA transaction During this shadowed address register operation bit field ADRCRmx SHCT must be set to 01B DMA_SADR0x x 0 7 DMA Channel 0x Source Address Register x 20H 90H Reset Value 0000 0000H DMA...

Page 753: ... channel mx is active when writing to DADRmx the source address will not be written into DADRmx directly but will be buffered in the shadow register SHADRmx until the start of the next DMA transaction During this shadowed address register operation bit field ADRCRmx SHCT must be set to 10B DMA_DADR0x x 0 7 DMA Channel 0x Destination Address Register x 20H 94H Reset Value 0000 0000H DMA_DADR1x x 0 ...

Page 754: ...tored in the SHADR is automatically set to 0000 0000H when the shadow transfer takes place The user can read the shadow register in order to detect if the shadow transfer has already taken place If the value in SHADR is 0000 0000H no shadow transfer can take place and the corresponding address register is modified according to the circular buffer rules DMA_SHADR0x x 0 7 DMA Channel 0x Shadow Addre...

Page 755: ...e Pointers and individual interrupt enable bits As a result each of the internal requests of a module can be routed independently to any of the interrupt output lines INT_Ox of the module The modules ASC0 1 and SSC0 1 have interrupt output lines that are directly connected to a specific request source MCA05707 fDMA SR 7 0 DMA Controller DMA Channels 00 07 DMA Sub Block 0 Request Selection Arbitrat...

Page 756: ... CHCR00 PRSEL 001B TIR SSC0 CHCR00 PRSEL 010B RIR SSC0 CHCR00 PRSEL 011B TIR SSC1 CHCR00 PRSEL 100B SR4 MLI0 CHCR00 PRSEL 101B SR4 MLI1 CHCR00 PRSEL 110B not connected 0 CHCR00 PRSEL 111B 01 CH00_OUT DMA channel 00 CHCR01 PRSEL 000B SCU_REQ1 Ext Request Unit1 CHCR01 PRSEL 001B TIR SSC1 CHCR01 PRSEL 010B RIR SSC1 CHCR01 PRSEL 011B TIR SSC0 CHCR01 PRSEL 100B SR5 MLI0 CHCR01 PRSEL 101B SR5 MLI1 CHCR0...

Page 757: ... SCU_REQ0 Ext Request Unit1 CHCR04 PRSEL 001B TIR ASC0 CHCR04 PRSEL 010B RIR ASC0 CHCR04 PRSEL 011B TIR ASC1 CHCR04 PRSEL 100B INT_O0 MultiCAN CHCR04 PRSEL 101B TIR SSC0 CHCR04 PRSEL 110B not connected 0 CHCR04 PRSEL 111B 05 CH04_OUT DMA channel 04 CHCR05 PRSEL 000B SCU_REQ1 Ext Request Unit1 CHCR05 PRSEL 001B TIR ASC1 CHCR05 PRSEL 010B RIR ASC1 CHCR05 PRSEL 011B TIR ASC0 CHCR05 PRSEL 100B INT_O0 ...

Page 758: ...t connected 0 CHCR06 PRSEL 111B 07 CH06_OUT DMA channel 06 CHCR07 PRSEL 000B SCU_REQ3 Ext Request Unit1 CHCR07 PRSEL 001B SR3 MSC0 CHCR07 PRSEL 010B SR3 MSC1 CHCR07 PRSEL 011B SR7 MLI0 CHCR07 PRSEL 100B SR7 MLI1 CHCR07 PRSEL 101B INT_O2 MultiCAN CHCR07 PRSEL 110B not connected 0 CHCR07 PRSEL 111B 1 The external request unit located in the System Control Unit handles DMA requests coming from GPTA a...

Page 759: ...I0 CHCR10 PRSEL 101B SR4 MLI1 CHCR10 PRSEL 110B not connected 0 CHCR10 PRSEL 111B 11 CH10_OUT DMA channel 10 CHCR11 PRSEL 000B SCU_REQ1 Ext Request Unit1 CHCR11 PRSEL 001B SR1 FADC CHCR11 PRSEL 010B SR7 ADC0 CHCR11 PRSEL 011B SR7 ADC1 CHCR11 PRSEL 100B SR5 MLI0 CHCR11 PRSEL 101B SR5 MLI1 CHCR11 PRSEL 110B not connected 0 CHCR11 PRSEL 111B 12 CH11_OUT DMA channel 11 CHCR12 PRSEL 000B SCU_REQ2 Ext R...

Page 760: ...000B SCU_REQ0 Ext Request Unit1 CHCR14 PRSEL 001B SR0 FADC CHCR14 PRSEL 010B SR6 ADC0 CHCR14 PRSEL 011B SR6 ADC1 CHCR14 PRSEL 100B SR3 MSC0 CHCR14 PRSEL 101B SR3 MSC1 CHCR14 PRSEL 110B not connected 0 CHCR14 PRSEL 111B 15 CH14_OUT DMA channel 14 CHCR15 PRSEL 000B SCU_REQ1 Ext Request Unit1 CHCR15 PRSEL 001B SR1 FADC CHCR15 PRSEL 010B SR7 ADC0 CHCR15 PRSEL 011B SR7 ADC1 CHCR15 PRSEL 100B INT_O3 Mul...

Page 761: ...t connected 0 CHCR16 PRSEL 111B 17 CH16_OUT DMA channel 16 CHCR17 PRSEL 000B SCU_REQ3 Ext Request Unit1 CHCR17 PRSEL 001B SR3 FADC CHCR17 PRSEL 010B SR7 MLI0 CHCR17 PRSEL 011B SR7 MLI1 CHCR17 PRSEL 100B INT_O1 MultiCAN CHCR17 PRSEL 101B SR3 MSC1 CHCR17 PRSEL 110B not connected 0 CHCR17 PRSEL 111B 1 The external request unit located in the System Control Unit handles DMA requests coming from GPTA a...

Page 762: ...0 02FFH STM 3 AEN3 F000 0400H F000 04FFH OCDS 4 AEN4 F000 0800H to F000 08FFH F000 0900H to F000 09FFH MSC0 MSC1 5 AEN5 F000 0A00H to F000 0AFFH ASC0 6 AEN6 F000 0B00H to F000 0BFFH ASC1 7 AEN7 F000 0C00H F000 0FFFH P0 P1 P2 P3 8 AEN8 F000 1000H F000 17FFH P4 P5 P6 P7 P8 P9 P10 9 AEN9 F000 1800H F000 2FFFH GPTA0 GPTA1 LTCA2 10 AEN10 F000 3C00H F000 3EFFH DMA 11 AEN11 F000 4000H F000 5FFFH MultiCAN...

Page 763: ...A080 0000H AFDF FFFFH External EBU Space 25 AEN25 8FE0 0000H 8FEF FFFFH AFE0 0000H AFEF FFFFH Data Flash Space 26 AEN26 8FF0 0000H 8FFF BFFFH AFF0 0000H AFFF BFFFH Emulation Device Memory Space 27 AEN27 8FFF C000H 8FFF FFFFH AFFF C000H AFFF FFFFH Boot ROM 28 AEN28 D800 0000H DEFF FFFFH E000 0000H E7FF FFFFH External Peripherals External Emulator 29 AEN29 E800 0000H E83F FFFFH LMU Image E80x transl...

Page 764: ...anges SLICE0 Selected Address Range 000B 32 sub ranges of 64 byte 00000B 00001B 11111B F010 A000H F010 A03FH F010 A040H F010 A07FH F010 A7C0H F010 A7FFH F010 A800H F010 BFFFH is not selectable 001B 32 sub ranges of 128 byte 00000B 00001B 11111B F010 A000H F010 A07FH F010 A080H F010 A0FFH F010 AF80H F010 AFFFH F010 B000H F010 BFFFH is not selectable 010B 32 sub ranges of 256 byte 00000B 00001B 1111...

Page 765: ...E800 4000H E800 FFFFH is not selectable 001B 32 sub ranges of 1 Kbyte 00000B 00001B 11111B E800 0000H E800 03FFH E800 0400H E800 07FFH E800 7C00H E800 7FFFH E800 8000H E800 FFFFH is not selectable 010B 32 sub ranges of 2 Kbyte 00000B 00001B 11111B E800 0000H E800 07FFH E800 0800H E800 0FFFH E800 F800H E800 FFFFH 011B 16 sub ranges of 4 Kbyte X0000B X0001B X1111B E800 0000H E800 0FFFH E800 1000H E8...

Page 766: ...d Note The 16 Kbyte stand by RAM SBRAM located at addresses C03FC000H to C03FFFFFH cannot be accessed by the DMA controller even if the corresponding enable bit MEmAENR AEN29 is set 110B 2 sub ranges of 32 Kbyte XXXX0B XXXX1B E800 0000H E800 7FFFH E800 8000H E800 FFFFH 111B 64 Kbyte XXXXXB E800 0000H E800 FFFFH Table 12 13 SRAM Address Protection Sub Range Definitions cont d SIZE1 Sub Ranges SLICE...

Page 767: ...LI1 are supplied from a common module clock fDMA that has the frequency of the system clock fSYS and is controlled via the DMA_CLC clock control register The MLI modules do not have their own clock control registers Their input clock is derived from the DMA clock divided by separate fractional divider registers The control of the suspend and break features is done independently inside each module ...

Page 768: ...requests of the MLI0 module INT_O 7 4 are not connected Two interrupt requests SR 1 0 INT_O 1 0 from the MLI1 module upper six interrupt requests of the MLI0 module INT_O 7 2 are not connected Four system interrupts SR 3 0 from the SCU Figure 12 32 Implementation of the DMA Module and the MLI Modules DMA Module Kernel Interrupt Control in DMA Module Clock Control Address Decoder SR 7 0 MCA05709 IN...

Page 769: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE 0 SP EN DISS DISR r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable the suspen...

Page 770: ... used and not connected DMA_SRCx x 0 7 DMA Service Request Control Register x 2FCH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Request Enable SRR 13 ...

Page 771: ...service request registers Note The bit coding of the MLI0 MLI1 service request registers is identical to that of the DMA Service Request Control Registers shown on the previous page DMA_MLI0SRCx x 0 3 DMA MLI0 Service Request Control Register x 2ACH x 4H Reset Value 0000 0000H DMA_MLI1SRCx x 0 1 DMA MLI1 Service Request Control Register x 2BCH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23...

Page 772: ...oint Unit FPU interrupt see also Page 5 35 DMA_SYSSCR1 Flash module interrupt see also Page 7 36 DMA_SYSSCR2 External Interrupt 0 see also Page 5 36 DMA_SYSSCR3 External Interrupt 1 see also Page 5 36 DMA_SYSSCR4 None can be used as software interrupt DMA_SYSSRCx x 0 4 DMA System Interrupt Service Request Control Register x 29CH x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 773: ...r blocks are arranged and adds some absolute address information Figure 12 33 DMA Controller Register Block Address Map 0 9 8 11 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description MCA05710 General Module Control DMA Control Status Registers F000 3C00H F000 3C10H F000 3C80H F000 3D80H F000 3C30H DMA Channel 00 07 Registers F000 3E78H Move Engine Registers DMA Control St...

Page 774: ...cker result register must be initialized e g written with FFFFH or with a desired start value and a DMA transaction has to be set up start address length etc When programming the DMA channel for the memory checker with CHCRmn RROAT 1 one DMA transfer request software or hardware triggered starts the DMA transaction At the read move operations of the DMA transaction data is always read from the mem...

Page 775: ...s Space Memory Checker Module Base Address End Address Note MCHK F010 C200H F010 C2FFH Table 12 16 Registers Overview Memory Checker egisters Register Short Name Register Long Name Offset Address1 1 The absolute register address is calculated as follows Module Base Address Table 12 5 Offset Address shown in this column Description see MCHK_ID Memory Checker Module Identification Reg 0008H Page 12 ...

Page 776: ...er Module Identification Register 008H Reset Value 001B C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit...

Page 777: ...liver 0000 0000H The Memory Checker Result Register contains the result of the memory check operation Before starting a checksum calculation operation it should be written with an initial checksum calculation value MCHK_IR Memory Checker Input Register 10H Reset Value 0000 0000H 31 0 MCHKIN w Field Bits Type Description MCHKIN 31 0 w Memory Checker Input The value written to MCHKIN is used for the...

Page 778: ...r MLI controller Move Engines when the pattern detection feature of the DMA controller is used Accessing MCHK_WR with the Move Engines of the MLI or DMA controller via the Bus Switch of the DMA controller see Figure 12 14 does not request the two FPI buses of the TC1796 SPB and RPB because it is near the MLI modules address ranges MCHK_WR Memory Checker Write Register 20H Reset Value 0000 0000H 31...

Page 779: ...Burst Flash memory devices The following features are supported by the EBU 64 bit internal PLMB interface 32 bit external demultiplexed bus interface Support for Intel style and Motorola style interface signals Support for Burst Flash memory devices Flexibly programmable access parameters Programmable chip select lines Arbitration support for external EBU bus master devices Little endian and Big e...

Page 780: ... either asynchronous external accesses or Burst Mode external accesses The EBU further contains blocks that control the external bus arbitration the region selection as well as the data and address paths MCB05713 Address Bus Control Lines Program Local Memory Bus Data Path Control External Bus Arbitration Asynchronous Access State Machine Burst Access State Machine PLMB Address Region Selection PL...

Page 781: ...on the data bus to the width of the external device according to the programmed parameters in its control registers The byte control signals BC 3 0 specify which parts of the data bus carry valid data Table 13 1 EBU Interface Signals Signal Pin Type Function D 31 0 O Data bus lines 0 31 A 23 0 O Address bus lines 0 23 CS 3 0 O Chip select 0 3 CSCOMB O Combined chip select for global select emulato...

Page 782: ...bal select signal or for emulator memory selection purposes More details are described on Page 13 28 13 2 4 Burst Flash Clock Output Input BFCLKO BFCLKI The clock output signal of the EBU is provided at pin BFCLKO It is used for timing purposes timing reference during Burst Mode accesses BFCLKO can be generated at Burst Mode accesses continuously or only during active accesses The clock input BFCL...

Page 783: ...e not activated during Burst Mode cycles Signals BCx can be programmed for different timing The available modes cover a wide range of external devices such as RAM with separate byte write enable signals and RAM with separate byte chip select signals This allows external devices to connect without any external glue logic Table 13 2 Byte Control Pin Usage Width of External Device BC3 BC2 BC1 BC0 32 ...

Page 784: ...ation Signals HOLD HLDA and BREQ The HOLD input signal is the external bus arbitration signal that indicates to the EBU when an external bus master requests to obtain ownership of the external bus The HLDA output signal is the external bus arbitration signal that indicates to a external bus master that it has obtained ownership of the external bus from the EBU The BREQ output signal is the externa...

Page 785: ...external bus Owner Mode Hold Mode When in Owner Mode the EBU operates as the master of the external bus In other words the EBU drives the external bus as required in order to access devices located on the external bus While the EBU is in Owner Mode it is not possible for any other master to perform any accesses on the external bus During Hold Mode the EBU tri states the appropriate signal on the e...

Page 786: ...l bus arbitration Table 13 4 EBU External Bus Arbitration Signals Signal Direction Function HOLD In HOLD is asserted low by an external bus master when the external bus master requests to obtain ownership of the external bus from the EBU HLDA In Out1 HLDA is asserted low by the Arbiter to signal that the external bus is available for use by the Participant i e the bus is not being used by the Arbi...

Page 787: ...13 5 External Bus Arbitration Programmable Parameters Parameter Function Description see EBU_CON ARBMODE Arbitration mode selection Page 13 83 EBU_CON ARBSYNC Arbitration input signal sampling control EBU_CON EXTLOCK External bus ownership locking control EBU_CON TIMEOUTC External bus time out control ...

Page 788: ... to the external bus at any time The EBU operates in Owner Mode all the time The HOLD arbitration input is ignored and the HLDA and BREQ arbitration outputs remain at high inactive level Sole Master Mode is selected by EBU_CON ARBMODE 11B 13 3 3 3 Arbiter Mode Arbitration Mode The EBU is the default owner of the external bus e g applicable when operating from external memory Arbitration is perform...

Page 789: ...hed bus ownership which causes the EBU to exit Hold Mode HLDA Out While HLDA is high the EBU is operating in Owner Mode A high to low transition indicates that the EBU has entered Hold Mode and that the external bus is available to the external master While HLDA is low the EBU is operating in Hold Mode A low to high transition indicates that the EBU has exited Hold Mode and has retaken ownership o...

Page 790: ...can perform at least one complete external bus access 4 When the external master has completed its access it tri states its bus interface and sets HOLD to inactive high level to signal that it has released the bus back to the EBU 5 When the EBU detects that the bus has been released it returns HLDA to high level and returns to Owner Mode by actively driving the bus interface lines There is always ...

Page 791: ...re completed When the external master requests the external bus HOLD 0 and conditions are appropriate the EBU releases ownership of the bus by HLDA 0 Start PLMB access to external bus is starting EBU_CON EXTLOCK 1 HOLD 0 EBU in Hold Mode i e not owner of the external bus Perform Appropriate External Bus Access for read access return result to PLMB yes no yes no no yes HOLD 0 yes no The EBU remains...

Page 792: ...ill return ownership of the bus to the external master once any ongoing transaction is complete Note Regardless of the state of the HOLD input the EBU will always perform at least one external bus access assumed that there is not a time out before returning ownership of the bus to the external master The use of the arbitration signals in Participant Mode is Participant Mode arbitration mode is sel...

Page 793: ...ts to regain ownership of the external bus 5 When the criterias are met for the EBU to release the bus ownership the EBU enters Hold Mode and drives BREQ 1 output high to signal that it has released the bus 6 When the external master detects that the EBU has released the bus BREQ 1 it returns HLDA to high level and takes ownership of the external bus 7 The EBU will not request ownership of the ext...

Page 794: ... is in Hold Mode yes no EBU is in Owner Mode EBU access to ext bus is underway New EBU access to ext bus is waiting EBU_CON EXTLOCK 1 EBU access to ext bus is pending yes no yes no yes no yes no The EBU remains in Hold Mode until the bus is released by the Arbiter signalled by the HLDA 0 Once the EBU has gained the external bus ownership it holds ownership While EXTLOCK 1 or Until all queued exter...

Page 795: ...ership 13 3 5 Locking the External Bus The external bus can be locked to allow the EBU to perform uninterrupted sequences of external bus accesses The EBU allows two methods of locking the external bus Locked PLMB accesses Lock bit EXTLOCK When the EBU has ownership of the external bus and is performing external bus accesses in response to a locked PLMB access sequence the ownership of the externa...

Page 796: ...t has access to the external bus at all times and as a result it is possible for the EBU to immediately perform the required external bus access If the EBU is operating in Arbiter or Participant Modes and receives a request for an external access from an PLMB or FPI bus master when it is not the owner of the external bus or is not able to retain ownership of the bus the request is rejected with a ...

Page 797: ...rship is started the external bus ownership is given once to the EBU Now the EBU waits until the next external bus access occurs on the PLMB If the requesting PLMB master or any other PLMB master subsequently performs no external bus accesses e g fails to re submit the original access request the EBU has ownership of the bus for an indefinite time and it would become impossible for an external mas...

Page 798: ...setting that will provide reasonable code execution performance while not placing too great a restriction on the access time of the memory device connected to the emulator region i e to the CSEMU chip select output see Page 13 29 In Emulation Mode the EBU can be configured for either Arbiter or Participant arbitration modes When configured as Participant the EBU must be granted the bus by an exter...

Page 799: ...oot memory i e instruction fetches In External Boot Mode the EBU can be configured for either Arbiter or Participant Arbitration modes When configured as Participant the EBU must be granted the bus by an external master before the Boot Configuration Value access can be made When configured as Arbiter the EBU owns the bus immediately after reset and can therefore perform the Boot Configuration Valu...

Page 800: ...ot memory is 32 bit wide and therefore always reads a 32 bit configuration word at the Data in point shown above The encoding of this 32 bit configuration word subsequently signals whether the memory is actually 32 bit or 16 bit wide In the case of 16 bit wide memory the EBU will discard the most significant 16 bits of the configuration word Note If FFFFH is returned as configuration word during t...

Page 801: ...DDRC WAITRDC RES AALI GN Field Bits Description AALIGN 0 Address Alignment Loaded into EBU_BUSCON0 AALIGN RES 1 Reserved Reserved for future use For TC1796 this bit must be set to 0 WAITRDC 4 2 Number of Wait States for Read Accesses Loaded into EBU_BUSAP0 WAITRDC ADDRC 6 5 Number of Cycles in the Address Phase Loaded into EBU_BUSAP0 ADDRC WAITINV 7 WAIT Input Polarity Control Loaded into EBU_BUSC...

Page 802: ... connected to CS0 is 32 bit wide Bit field RES32 bits 31 16 of the configuration word are potentially available for use as configuration information Note In the TC1796 the EBU does not actually use bits 31 to 16 of the configuration word when CONF32BIT is 1 However to allow future expansion this bit should be programmed to 0 RES32 31 16 Reserved This bit field is reserved for future use In the TC1...

Page 803: ...al memory regions is translated by the EBU to the appropriate external access es In the TC1796 the EBU responds to the address ranges as defined in Table 13 9 The compare action means that the EBU compares the supplied PLMB address to all its external regions If a match is found the EBU performs the appropriate external bus access Otherwise the EBU generates a PLMB Error Acknowledge The access reg...

Page 804: ...mmodate different types of external devices The emulator region is programmable in the same way as the user programmable regions through registers EBU_EMUAS EBU_EMUBC and EBU_EMUBAP Each of the regions can be defined for either asynchronous demultiplexed or synchronous Burst Flash access Table 13 11 lists the programmable parameters that are available for the five external regions region 0 to 3 an...

Page 805: ...termines whether or not parameter ALTSEG is always compared to PLMB address REGENAB Enable bit for each region A disabled region will always generate a miss during address comparison EBU_BUSCONx EBU_EMUBC AGEN Region access type Demultiplexed asynch or Burst Flash sync access ENDIAN Region endian mode Little or big endian access mode PORTW External region data bus width 16 bit or 32 bit WRITE Regi...

Page 806: ...omes active CSCOMB which is a combination of CSEMU CSGLB and CSOVL Details about the chip select control logic as implemented in the TC1796 are shown in Figure 13 10 The four chip select lines CSx are all available at dedicated chip select outputs The internal CSGLB signal is controlled by bit field EBU_CON GLOBALCS The bits in this bit field make it possible to individually enable disable each of...

Page 807: ...05721 EBU Control 1 1 1 1 CSCOMB CS1 CS2 CS3 CS0 CS1 CS0 CSGLB Bit Field GLOBALCS SCU_CON CSG EN CSO EN CSE EN EBU_CON Bit 19 Bit 18 Bit 17 Bit 16 1 1 CSOVL CSEMU 1 1 1 1 1 Bit Field OVERLAY EBU_EMUOVL Bit 3 Bit 2 Bit 1 Bit 0 1 1 Bit CSEEN is set after reset Bits CSOEN and CSGEN are cleared after reset 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...

Page 808: ...on x where A 31 28 must only point to segments 8 10 13 and 14 see Table 13 9 on Page 13 25 Bit field MASK determines the length of a region It specifies how many bits of a PLMB address must match the contents of the BASE x bit field to a maximum of 15 starting with A 26 Note that address bits A 31 27 must always match Bit field ALTSEG determines the number of an alternate segment that can be used ...

Page 809: ...G bit field alternate segment address The result of the comparison 1 if equal otherwise 0 is fed to an AND gate 2 If ALTENAB 0 the alternate segment function is disabled and the output of the AND gate is 0 With ALTENAB 1 the alternate segment function is enabled and the result of the comparison between ALTSEG and the segment part of the PLMB address is fed to an OR gate MCA05722 31 LMB Address 28 ...

Page 810: ...rst Flash access of Type 0 AGEN 010B or of Type 1 AGEN 101B The output of the comparator is fed to an OR gate 8 The OR gate produces a 1 if the region is a read only region for example a Burst Flash access that is write protected via the write bit The output of the OR gate is fed to a NAND gate 9 The NAND gate delivers a 0 if a write is performed to a read only region and prevents the region from ...

Page 811: ...disabled region s or no address match The EBU returns a PLMB Error Acknowledge Table 13 12 EBU Address Regions Size and Start Address Relations MASK No of Address Bits compared to BASE 26 12 Range of Address Bits compared to BASE 26 12 Region Size and Start Address Granularity Range of Offset Address Bits within Region 1111B 15 A 26 12 4 Kbyte A 11 0 1110B 14 A 26 13 8 Kbyte A 12 0 1101B 13 A 26 1...

Page 812: ... loaded automatically by the boot read access see Page 13 21 Note When performing a boot sequence from the device connected to CS0 software must be written carefully to ensure that external code access is never unintentionally disabled This can be achieved when the regions are configured as required with CS0FAM 1 after reset and afterwards CS0FAM is set to 0 to activate the new address map Emulato...

Page 813: ...he index number of the lowest matching region to the parameter selection logic During the third phase Cycle n 2 the parameter selection logic selects the appropriate access cycle parameters At the end of this cycle the access parameters associated with the highest priority region are checked for an invalid access e g a write access that does not lie within a defined writable region If the access i...

Page 814: ...e of TriCore Additionally the EBU provides limited support for big endian access modes Big endian accesses are supported by modifying the least significant two address bits This feature is programmable separately for each chip select region by bits ENDIAN in registers EBU_BUSCONx and EBU_EMUBC Big endian access mode is available only for single accesses 8 bit 16 bit or 32 bit to regions programmed...

Page 815: ...ration of the access sequence The external accesses are performed in ascending PLMB address order To allow proper bus width translation the EBU has the capability to re align data between the external bus and the PLMB as shown in Figure 13 13 Figure 13 13 PLMB to External Bus Data Re Alignment During an access to a 32 bit wide external region either Buffer 1 or Buffer 2 is enabled according to bit...

Page 816: ...ess the external bus address sequence will be XX10B XX00B 13 5 7 Address Alignment During Bus Accesses During an external bus access the EBU will optionally align the internal byte address to generate the appropriate external word or half word address aligned to the external address pins A 23 0 This address alignment is enabled separately for each region by the AALIGN bit in the EBU_BUSCONx or EBU...

Page 817: ... the PLMB from the appropriate number of 16 bit or 32 bit data fetched from the external bus The EBU provides a bypass feature for the case where a PLMB read access is received which matches a pending write in the Data Write Buffer In this case the required data is returned directly from the Data Write Buffer In all other cases the request is translated in to the appropriate number of external rea...

Page 818: ...umber of cycles to fetch the next four 64 bit words For asynchronous memories the prefetch is performed by generating the appropriate number of device read accesses The result of the prefetch will be that the Code Prefetch Buffer will be ready with the instructions when the next request for sequential instructions arrives The allows the cancellation of a pending prefetch if a new data access start...

Page 819: ... applies to burst read cycles Throughout the remainder of this document a short hand notation is adopted to represent any clock cycle in any phase This notation consists of two or three letters followed by a number The letters identify the access phase within which the clock cycle is located e g AP for Address Phase The number denotes the number of LMBCLK clock cycles within the phase i e 1 first ...

Page 820: ...BUSCONx MULTMAP 0 is set ADDRC multiplier function enabled The calculation of the number of LMBCLK cycles in the Address Phase is described in the following table The equivalent control capability is available for bit field EBU_EMUBAP ADDRC that can be multiplied by EBU_EMUBCx CMULT if bit EBU_EMUBC MULTMAP 0 is set When an access is performed at a burst read cycle the start of the Address Phase i...

Page 821: ...following table The equivalent control capability is available for bit field EBU_EMUBAP CMDDELAY which can be multiplied by EBU_EMUBC CMULT if bit EBU_EMUBC MULTMAP 2 is set 13 7 3 Command Phase CP The Command Phase is mandatory It always consists of at least one or more LMBCLK cycles The phase can optionally be extended to accommodate slower devices The length number of LMBCLK cycles of the Comma...

Page 822: ...ata to be written on the data bus D 31 0 in the case of a write cycle Asserts the appropriate BCx low in the case where BCx is programmed to be asserted with the RD or RD WR signals At the end of the Command Phase during an asynchronous access the EBU Returns the appropriate control signal RD or RD WR high according to the type of access type read or write Latches the data from the data bus D 31 0...

Page 823: ...BCLK cycles of the Data Hold phase is programmed via the EBU_BUSAPx DATAC bit field The total number of Data Hold phase clock cycles is calculated by multiplying the DATAC parameter independently of bit field EBU_BUSCONx MULTMAP with EBU_BUSCONx CMULT The calculation of the number of LMBCLK cycles in the Data Hold phase is described in the following table The equivalent control capability is avail...

Page 824: ...Phase during a burst read access the EBU Returns the BAA signal high Returns the CSx signal high Returns the RD signal high The total number of Burst Phase cycles is calculated by multiplying the EBU_BUSAPx BURSTC parameter with EBU_BUSCONx CMULT but only if bit EBU_BUSCONx MULTMAP 3 is set BURSTC multiplier function enabled The calculation of the number of Burst Phase cycles is defined by the fol...

Page 825: ... is followed by a read access or after a read access that is followed by a write access Bit fields EBU_BUSAPx DTACS and EBU_EMUBAPx DTACS determine the length basic number of LMBCLK clock cycles of the Recovery Phase after a read write access of one region that is followed by a read write access of another region The calculation of the total numbers of Recovery Phase clock cycles for each of the f...

Page 826: ...e Case Parameter s used to calculate Highest Wins Recovery Phase Region Current Access Next Access Same CSn Read Read RDRECOVC Write Write WRRECOVC Read Write RDRECOVC DTARDWR Write Read WRRECOVC DTARDWR Different CSn Read Read DTACS RDRECOVC Write Write DTACS WRRECOVC Read Write DTACS RDRECOVC DTARDWR Write Read DTACS WRRECOVC DTARDWR ...

Page 827: ...fields providing multiplication factors of 1 4 8 16 and 32 As some types of device timing requirements for a number of the access phases tend to be larger than others these phase length settings are always multiplied by the appropriate multiplier value These phases length settings are Number of Command Phase cycles during read accesses WAITRDC Number of Command Phase cycles during write accesses W...

Page 828: ...cycles when Switching between different memory regions CS Switching between read and write operations After each read cycle After each write cycle Software driver routines are required in order to support Nand Flash devices using asynchronous device accesses A single Nand Flash access sequence is performed by generating the appropriate sequence of discrete asynchronous device accesses in software ...

Page 829: ... The 16 bit data is driven to read from the D 15 0 pins during the data phase D 31 16 are not used Figure 13 15 Connection of a 16 bit Demultiplexed Device The 32 bit demultiplexed mode is selected by EBU_BUSCONx PORTW 10B EBU_BUSCONx AGEN 000B For 32 bit demultiplexed devices the complete 24 bit address is driven at the EBU pins for the duration of the complete external bus cycle The 32 bit data ...

Page 830: ...ection for the current transfer and can be used to control the data direction through the buffer for the D 31 0 bus as well as controlling whether an access to a Motorola Style device is read or write Figure 13 17 Typical Connection of Asynchronous Devices A 23 0 D 31 0 32 Bit Intel style Device MCA05728 A 23 0 D 31 0 CE OE WE CSx CSy RD RD WR TC1796 EBU MR W A 23 0 D 31 0 32 Bit Motorola style De...

Page 831: ... parameters only apply to asynchronous devices when EBU_BUSCONx AGEN 000B Note that emulation registers EBU_EMU include parameters that control the emulator chip select region CSEMU output while EBU_BUS x registers include parameters that control the four CS 3 0 chip select regions x The equivalent registers contain identical bits and bit fields Table 13 17 Asynchronous Access Programmable Paramet...

Page 832: ...ess always multiplied by CMULT DTACS Number of minimum recovery cycles when the next access going to a different memory region always multiplied by CMULT EBU_BUSCONx EBU_EMUBC WAIT External Wait State control OFF asynchronous synchronous WAITINV Reversed polarity at WAIT active low or active high CMULT Common cycle multiplier control 1 4 8 16 32 MULTMAP Multiplier map each bit enables multiplier f...

Page 833: ...ur phases as follows Address Phase compulsory Command Delay Phase optional Command Phase compulsory Recovery Phase optional The example shows an access cycle with all four phases programmed for a duration of one LMBCLK cycle Address LMBCLK1 A 23 0 MCT05729 Sample ADV AP 1 to n CD2 0 to n CP 1 to n RP2 0 to n next AP Next A CSx RD RD WR MR W Data in D 31 0 BCx 3 3 1 All phases programmed to one LMB...

Page 834: ...ompulsory Command Delay Phase optional Command Phase compulsory Data Hold Phase optional Recovery Phase optional The example shows an access cycle with all five phases programmed for a duration of one LMBCLK cycle 1 All phases programmed to one LMBCLK period length 2 These phases are optional and can be skipped 3 BCx signals can be asserted either with CSx or RD WR LMBCLK1 A 23 0 Address ADV AP 1 ...

Page 835: ...ion to be ignored or sampled either synchronously or asynchronously selected via the EBU_BUSCONx WAIT or EBU_EMUBC WAIT bit field Additionally the polarity of WAIT can be programmed for active low default after reset or active high function via bit EBU_BUSCONx WAITINV or EBU_EMUBC WAITINV The signal will only take effect after the programmed number of Command Phase cycles has passed This means tha...

Page 836: ...ase CPi1 internally programmed At LMBCLK edge 2 the EBU samples the WAIT input as low and starts an additional Command Phase cycle CPe2 externally generated as a result of the WAIT input sampled as low at LMBCLK edge 1 At LMBCLK edge 3 the EBU samples the WAIT input as high and starts an additional Command Phase cycle CPe3 externally generated as a result of the WAIT input sampled as low at LMBCLK...

Page 837: ...internally programmed At LMBCLK edge 3 the EBU samples the WAIT input as high and starts an additional Command Phase cycle CPe3 externally generated as a result of the WAIT input sampled as low at LMBCLK edge 1 At LMBCLK edge 4 the EBU starts an additional Command Phase cycle CPe4 externally generated as a result of the WAIT input sampled as low at LMBCLK edge 2 LMBCLK A 23 0 Address MCT05731 AP C...

Page 838: ...starts the Recovery Phase Figure 13 21 External Wait Insertion Asynchronous Mode LMBCLK A 23 0 Address MCT05732 AP CPi1 CPi2 CPe3 CPe4 CSx RD D 31 0 RP1 Read Access with Asynchronous WAIT 1 2 3 4 5 Data in In the example above the Command Delay phase is internally programmed to zero LMBCLK cycles no Command Delay phase The Command Phase is internally programmed to two LMBCLK cycles All other phase...

Page 839: ...mmand Delay Phase is followed by a three cycle Command Phase At the end of the Command Phase the data is read latched by the EBU A one cycle Recovery Phase is inserted at the end of the cycle At the start of this Recovery Phase all control signals return to their non active levels For the write access the Command Delay Phase is followed by a two cycle Command Phase During a write access it is poss...

Page 840: ...13 22 Example of an INTEL style Demultiplexed Device Access LMBCLK A 23 0 Address MCT05733 AP1 Next A CSx RD Data in D 31 0 AP2 CDi1 CDi2 CPi1 CPi2 CPi3 RP1 RP2 New AP1 Sample Read Access LMBCLK A 23 0 Address AP1 Next A CSx RD WR Data out D 31 0 AP2 CDi1 CDi2 CPi1 CPi2 DH1 DH2 RP1 New AP1 Write Access ...

Page 841: ...gnal that the data is available on the data bus During a write access the falling edge of DTACK indicates that the Motorola style device has completed the write access and the data can be removed from the data bus This can be accomplished by use of the WAIT signal with inverse polarity selected by EBU_BUSCONx WAITINV 1 with the following limitations 1 During read accesses a minimum command phase o...

Page 842: ...4 AP1 Next A CSx M RW Data in D 31 0 AP2 CPi1 CPi2 CPe3 CPe4 CPe5 RP1 RP2 New AP1 Sample Read Access LMBCLK A 23 0 Address AP1 Next A CSx MR W Data out D 31 0 AP2 CPi1 CPi2 CPe3 CPe4 RP1 RP2 RP3 New AP1 Write Access WAIT used as DTACK used as AS used as AS WAIT used as DTACK 1 1 1 1 1 At Motorola devices CS is connected with AS while WAIT with inverse polarity is connected to the DTACK output ...

Page 843: ...k clock to maximize the frequency of operation When it is necessary to perform non burst accesses to Burst Flash devices it is necessary to reprogram the characteristics of the corresponding chip select region for the appropriate asynchronous access 13 9 1 Signal List The following signals of the EBU are used for the burst read accesses Table 13 18 Burst Flash Mode Signal List Signal Type Function...

Page 844: ...the address phase s The 16 bit data is read from the D 15 0 pins during the burst phases D 31 16 are not used connected Figure 13 24 Connection of a 16 bit Burst Flash Memory The 32 bit Burst Flash mode is selected by EBU_BUSCONx PORTW 10B EBU_BUSCONx AGEN 010B Burst Flash Type 0 or 101B Burst Flash Type 1 For 32 bit Burst Flash devices the complete 24 bit address is driven at the EBU pins during ...

Page 845: ...de the user s software must first perform the appropriate actions to initialize the Burst Flash memory devices for burst operation using asynchronous access mode and then reconfigure the EBU to use the devices in Burst Mode DQ 15 0 D 31 16 1M x 16 Burst FLASH Memory D 15 0 A 19 0 CE OE WE CSx RD RD WR TC1796 EBU ADV WAIT CLK DQ 15 0 1M x 16 Burst FLASH Memory A 19 0 CE OE WE ADV WAIT CLK A 21 2 AD...

Page 846: ...andard access phases for Burst Flash devices are AP Address Phase compulsory see Page 13 41 CD Command Delay Phase optional see Page 13 43 CP Command Phase compulsory see Page 13 43 BP Burst Phase compulsory see Page 13 46 RP Recovery Phase optional see Page 13 47 Note During a burst access the Burst Phase BP is repeated the required number of times to complete the burst length 13 9 4 Programmable...

Page 847: ...s for read accesses always multiplied by CMULT BURSTC Number of data cycles can be multiplied by CMULT RDRECOVC Number of minimum recovery cycles after a read access can be multiplied by CMULT DTACS Number of minimum recovery cycles when the next access points to a different memory region always multiplied by CMULT EBU_BUSCONx EBU_EMUBC WAIT External Wait State control OFF asynchronous synchronous...

Page 848: ...r burst length defined in FETBLEN FETBLEN0 Number of burst data cycles for Type 0 devices 1 2 4 or 8 FETBLEN1 Number of burst data cycles for Type 1 devices 1 2 4 or 8 EXTCLOCK BFCLKO frequency in relation to LMBCLK Equal 2 3 or 4 of LMBCLK FDBKEN Burst clock feedback control DBA0 Address Alignment Wrapping control for Type 0 device DBA1 Address Alignment Wrapping control for Type 1 device EBSE0 E...

Page 849: ... burst clock mode bit FDBKEN burst clock feedback control and bit field DTALTNCY latency cycle control are valid for both Burst Flash access types independently of bit AGEN 13 9 6 BFCLKO Output The EBU provides a clock signal BFCLKO Burst Flash Clock Output suitable for clocking Burst Flash devices during burst read accesses The BFCLKO signal can be programmed to operate in one of two modes Ungate...

Page 850: ...is clocked by BFCLKI instead of by BFCLKO The data is then re synchronized to BFCLKO internally before being passed to the normal logic When the clock feedback mode is used BFCLKI can therefore be skewed by almost an entire BFCLKO cycle relative to the internal LMBCLK clock without losing data integrity A side effect of using clock feedback mode is an increase in data latency of 2 cycles of BFCLKO...

Page 851: ...e Burst Flash access cycle is defined by bit field FETBLENn In this mode one two four or eight Burst Phases can be selected for one Burst Flash access cycle Bit field FETBLENn determines the maximum number of Burst Phases If more data is requested than can be delivered by one Burst Flash access cycle as defined by FETBLENn the EBU will automatically generate the appropriate number of continuous Bu...

Page 852: ...elay Phase length 3 LMBCLK cycles CMDDELAY 011B Command Phase length 2 LMBCLK cycles WAITRDC 010B Burst Phase length 2 LMBCLK cycles BURSTC 010B Recovery Phase length 2 LMBCLK cycles RDRECOVC 010B Burst Length 4 FETBLENn 010B Bus Width 16 bit PORTW 01B or 32 bit PORTW 10B Note that the cycle multiplier control capability is disabled in the example MULTMAP 00H AP1 AP2 AP3 CPi1 CPi2 BP1 BP2 new AP1 ...

Page 853: ...ng of data by the EBU guarantees valid sampling of the data from the Burst Flash device 13 9 11 External Cycle Control via the WAIT Input The EBU controls the Burst Flash device via the WAIT input This allows the EBU to support operation of Burst Flash while crossing Burst Flash page boundaries During a Burst Flash access the WAIT input operates in one of the five modes shown in Table 13 20 AP 1 A...

Page 854: ...y Wait Generation Mode EBU_BUSCON WAIT 01B and standard wait generation EBU_BUSCON WAIT 10B In operation the Burst Flash controller loads a counter with the required number of samples at the start of each burst At the end of each Burst Phase the Burst Flash controller samples the WAIT input and the data bus If WAIT is inactive the sample is valid the sample counter is decremented and the sampled d...

Page 855: ... access cycle i e Address Phase Command Delay Phase Command Phase Burst Phase etc Furthermore the EBU calculates the address to be issued during the new Address Phase to ensure correct sequential reading of the Burst Flash device s This mode allows for example an AMD Burst Flash device to cause the EBU to terminate the current access when a page boundary is crossed and to issue a complete new burs...

Page 856: ... by de asserting the CSx signal followed by the appropriate length Recovery Phase Figure 13 30 shows termination of a burst access following the read of two locations i e two Burst Phases from the Burst Flash device s Figure 13 30 Terminating a Burst by De asserting CS LMBCLK A 23 0 MCT05740 AP2 CSx RD Data 1 D 31 0 CPi1 CPi2 BP1 BP2 BP1 BP2 RP1 RP2 BFCLKO ADV BAA Data 2 Address ...

Page 857: ...this TC1796 System Units Vol 1 of 2 User s Manual Table 13 21 Registers Address Space Flash Registers Module Base Address End Address Note EBU F800 0000H F800 03FFH Table 13 22 Registers OverviewPMU Overlay Control Registers Register Short Name Register Long Name Offset Address Description see EBU_CLC EBU Clock Control Register 000H Page 13 82 EBU_ID EBU Module Identification Register 008H Page 13...

Page 858: ... Bus Configuration Register 2 0D0H EBU_BUSCON3 EBU Bus Configuration Register 3 0D8H EBU_BUSAP0 EBU Bus Access Parameter Register 0 100H Page 13 97 EBU_BUSAP1 EBU Bus Access Parameter Register 1 108H EBU_BUSAP2 EBU Bus Access Parameter Register 2 110H EBU_BUSAP3 EBU Bus Access Parameter Register 3 118H EBU_EMUAS EBU Emulator Address Select Register 160H Page 13 101 EBU_EMUBC EBU Emulator Bus Confi...

Page 859: ...tification Register 008H Reset Value 0014 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines...

Page 860: ...EBU_CLC EBU Clock Control Register 000H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DISS DISR r r rw Field Bits Type Description DISR 0 rw EBU Disable Request Bit This bit is used for enable disable control of the EBU 0B EBU disable is not requested 1B EBU disable is requested DISS 1 r EBU Disable Status Bit 0B EBU is enabled d...

Page 861: ...11 10 9 8 7 6 5 4 3 2 1 0 TIMEOUTC ARB MODE ARB SYN C EXT LOC K 1 0 0 rw rw rw rw rw rw r Field Bits Type Description EXTLOCK 4 rw External Bus Lock Control 0B External bus is not locked after the EBU gains ownership 1B External bus is locked after the EBU gains ownership ARBSYNC 5 rw Arbitration Signal Synchronization Control 0B Arbitration inputs are synchronous 1B Arbitration inputs are asynchr...

Page 862: ...0B Normal region chip select logic is in operation 1B Normal region chip select logic is disabled The Chip Select 0 Address Override Mode is selected All external bus accesses are directed to Region 0 CS0 This bit is set following reset in external boot mode see Page 13 21 which ensures that the CPU to which the EBU is connected can boot from external memory regardless of the CPU specific boot add...

Page 863: ...reduces the number of synchronization stages used in the pad logic of EBU pads 0B Two stages of synchronization used 1B Single stage of synchronization used 1 3 rw Reserved Read as 1 after reset must be written with 0 0 2 1 26 20 rw Reserved Read as 0 must be written with 0 0 0 31 30 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 864: ...ption FETBLEN0 3 0 rw Fetch Burst Length for Burst Flash Type 0 This bit field determines the maximum number of burst data cycles which are executed by the EBU during a burst access to Burst Flash Type 0 000B 1 data access default after reset 001B 2 data accesses 010B 4 data accesses 011B 8 data accesses 1XXB Reserved FBBMSEL0 4 rw Flash Burst Buffer Mode Select for Burst Flash Type 0 0B Continuou...

Page 865: ...state EBSE0 9 rw Early Burst Signal Enable for Burst Flash Type 0 0B Outputs ADV and BAA are delayed by 1 2 LMBCLK clock period 1B Output lines ADV and BAA are not delayed see Page 13 73 DBA0 10 rw Disable Burst Address Wrapping 0B The EBU automatically re aligns any non aligned burst access to a Type 0 device so that data can be fetched from the device in a single burst transaction 1B The EBU alw...

Page 866: ...ber of burst data cycles which are executed by the EBU during a Burst Flash Type 1 burst access 000B 1 data access default after reset 001B 2 data accesses 010B 4 data accesses 011B 8 data accesses 1XXB Reserved FBBMSEL1 20 rw Flash Burst Buffer Mode Select for Burst Flash Type 1 0B Continuous mode 1B Flash burst buffer length is defined by the value of FETBLEN1 default after reset WAITFUNC1 21 rw...

Page 867: ...s to a Type 1 device at the address specified by the LMB request Any required address wrapping must be automatically provided by the Burst Flash device Note Care must be taken with the use of this feature The address at which wrapping should take place varies with the LMB burst access size while Burst Flash devices wrap at fixed address boundaries Therefore it is not possible to guarantee correct ...

Page 868: ...EGENAB 0 rw Memory Region Enable 0B Memory region is disabled default after reset except for ADDRSEL0 see below 1B Memory region is enabled When the EBU is in external boot mode REGENAB in register ADDRSEL0 is 1 after reset ALTENAB 1 rw Alternate Segment Comparison Enable 0B ALTSEG is never compared to LMB address default after reset 1B ALTSEG is always compared to LMB address MASK 7 4 rw Memory R...

Page 869: ...t is set to ensure that region 0 i e CS0 is activated for all external bus accesses This allows external boot to be performed from region 0 regardless of the actual boot address of the CPU to which EBU is connected BASE 31 12 rw Memory Region Base Address Base address to be compared to PLMB address in conjunction with the mask control 0 3 2 r Reserved Read as 0 should be written with 0 Field Bits ...

Page 870: ...EBU Bus Configuration Register 0C0H x 8H Reset Value internal boot 8092 8000H Reset Value external boot 8092 807FH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRI TE AGEN 0 WAIT PORTW BCGEN WAI TINV PRE FET CH DLO AD ENDI AN rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMULT 0 CTYPE AALI GN WEA KPR EF 0 MULTMAP rw r rw rw rw r rw ...

Page 871: ... XX1XXXXBDATAC is not multiplied X0XXXXXBRDRECOVC is not multiplied X1XXXXXBRDRECOVC is multiplied by CMULT 0XXXXXXBWRRECOVC is not multiplied 1XXXXXXBWRRECOVC is multiplied by CMULT Note that the bus access parameters WAITRDC WAITWRC DTARDWR and DTACS in register BUSAPx are not programmable and always use the CMULT multiplier WEAKPREF 8 rw Weak Prefetch 0B Code prefetch cannot be aborted by an in...

Page 872: ...default after reset 1B Big endian access mode selected DLOAD 17 rw Enforce Data Upload from External Bus 0B Data access is fed from data write buffer if it is available default after reset 1B Data access is always fed from the external bus access PREFETCH 18 rw Prefetch Mechanism for Each Code Access 0B Code access never uses prefetch buffer mechanism default after reset 1B Code access always uses...

Page 873: ... State Control This bit determines the function of the WAIT input This is specific to the device type i e the AGEN field For Asynchronous devices AGEN 000B 00B OFF default after reset 01B Asynchronous input at WAIT 10B Synchronous input at WAIT 11B Nand Flash mode For Burst Flash devices AGEN 010B or 101B 00B OFF default after reset 01B Early synchronous input at WAIT 10B Synchronous input at WAIT...

Page 874: ... BUSCON0 is overwritten automatically subsequent to the release of reset as a result of the external Boot Configuration Value fetch WRITE 31 rw Memory Region Write Protection 0B Writes to the memory region are enabled 1B Writes to the memory region are disabled default after reset 0 12 7 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 875: ...0 DATAC RDRECOVC WRRECOVC DTARDWR DTACS rw rw rw rw rw Field Bits Type Description DTACS 3 0 rw Recovery Cycles between Different Regions This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions The total number of this type of Recovery Phase clock cycles is defined by DTACS multiplied by the factor selected by EBU_BUSCON...

Page 876: ...termines the basic number of clock cycles of the Recovery Phase at the end of write accesses The total number of this type of Recovery Phase clock cycles further depends on bit fields EBU_BUSCONx CMULT and EBU_BUSCONx MULTMAP 6 see also Page 13 47 000B No Recovery Phase clock cycles available 001B 1 clock cycle selected B 110B 6 clock cycles selected 111B 7 clock cycles selected RDRECOVC 13 11 rw ...

Page 877: ... bit field determines the basic number of data cycles during burst accesses The total number of burst data cycles further depends on bit fields EBU_BUSCONx CMULT and EBU_BUSCONx MULTMAP 3 see also Page 13 46 000B No burst data cycle selected 001B 1 clock cycle selected B 110B 6 clock cycles selected 111B 7 clock cycles selected WAITWRC 21 19 rw Write Command Phase Cycles This bit field determines ...

Page 878: ...sic number of Command Delay phase clock cycles The total number of Command Delay phase clock cycles further depends on bit fields EBU_BUSCONx CMULT and EBU_BUSCONx MULTMAP 2 see also Page 13 43 000B 0 clock cycle selected 001B 1 clock cycle selected B 110B 6 clock cycles selected 111B 7 clock cycles selected 1 29 28 rw Reserved Rading these bits will return the value last written read as 1 after r...

Page 879: ...rw rw r rw rw Field Bits Type Description REGENAB 0 rw Memory Region Enable 0B Memory region is disabled 1B Memory region is enabled default after reset ALTENAB 1 rw Alternate Segment Comparison Enable 0B ALTSEG is never compared to LMB address default after reset 1B ALTSEG is always compared to LMB address MASK 7 4 rw Memory Region Address Mask Specifies the number of right most bits in the base ...

Page 880: ...should be written with 0 EBU_EMUBC EBU Emulator Bus Configuration Register 168H Reset Value 0190 2077H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRI TE AGEN 0 WAIT PORTW BCGEN WAI TINV PRE FET CH DLO AD ENDI AN rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMULT 0 CTYPE AALI GN WEA KPR EF 0 MULTMAP rw r rw rw rw r rw Field Bits Type Description ...

Page 881: ...XX1XXXXBDATAC is not multiplied X0XXXXXBRDRECOVC is not multiplied X1XXXXXBRDRECOVC is multiplied by CMULT 0XXXXXXBWRRECOVC is not multiplied 1XXXXXXBWRRECOVC is multiplied by CMULT Note that the bus access parameters WAITRDC WAITWRC DTARDWR and DTACS in register BUSAPx are not programmable and always use the CMULT multiplier WEAKPREF 8 rw Weak Prefetch 0B Code prefetch cannot be aborted by an int...

Page 882: ...default after reset 1B Big endian access mode selected DLOAD 17 rw Enforce Data Upload from External Bus 0B Data access is fed from data write buffer if it is available default after reset 1B Data access is always fed from the external bus access PREFETCH 18 rw Prefetch Mechanism for Each Code Access 0B Code access never uses prefetch buffer mechanism default after reset 1B Code access always uses...

Page 883: ...mines the function of the WAIT input This is specific to the device type i e the AGEN field 00B OFF default after reset 01B Asynchronous input at WAIT default after reset 10B Synchronous input at WAIT 11B Data Handshake input at WAIT Burst Flash devices only 0 27 26 rw Reserved Read as 0 after reset must be always written with 0 AGEN 30 28 rw Address Generation Control This bit field selects the a...

Page 884: ...9 8 7 6 5 4 3 2 1 0 DATAC RDRECOVC WRRECOVC DTARDWR DTACS rw rw rw rw rw Field Bits Type Description DTACS 3 0 rw Recovery Cycles between Different Regions This bit field determines the basic number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions The total number of this type of Recovery Phase clock cycles is defined by DTACS multiplied by the facto...

Page 885: ...etermines the basic number of clock cycles of the Recovery Phase at the end of write accesses The total number of this type of Recovery Phase clock cycles further depends on bit fields EBU_EMUBC CMULT and EBU_EMUBC MULTMAP 6 see also Page 13 47 000B No Recovery Phase clock cycles available 001B 1 clock cycle selected B 110B 6 clock cycles selected 111B 7 clock cycles selected RDRECOVC 13 11 rw Rec...

Page 886: ...is bit field determines the basic number of data cycles during burst accesses The total number of burst data cycles further depends on bit fields EBU_EMUBC CMULT and EBU_EMUBC MULTMAP 3 see also Page 13 46 000B No burst data cycle selected 001B 1 clock cycle selected B 110B 6 clock cycles selected 111B 7 clock cycles selected WAITWRC 21 19 rw Write Command Phase Cycles This bit field determines th...

Page 887: ... The total number of Command Delay phase clock cycles further depends on bit fields EBU_EMUBC CMULT and EBU_EMUBC MULTMAP 2 see also Page 13 43 000B 0 clock cycle selected 001B 1 clock cycle selected B 110B 6 clock cycles selected 111B 7 clock cycles selected 1 28 r Reserved Reading these bits will return the value last written read as 1 after reset 0 29 r Reserved Reading these bits will return t...

Page 888: ...3 2 1 0 0 0 OVERLAY r rw rw Field Bits Type Description OVERLAY 3 0 rw Overlay Chip Select Signal The bits of this bit field are used to enable the CS 3 0 chip select lines for the CSOVL overlay chip select generation With x 0 3 the OVERLAY bits are defined as follows see also Page 13 29 0B CSOVL is not activated by an active CSx 1B CSOVL is activated when CSx becomes active Bits 3 0 are assigned ...

Page 889: ...Register 190H Reset Value 0000 0000H 31 1 0 0 D I P r rw Field Bits Type Description DIP 0 rw Disable Internal Pipelining 0B The EBU can accept a new LMB transaction before the previous LMB transaction has been completed 1B The EBU will issue an LMB re try if an LMB access is received while a previous LMB transaction is still not completed 0 31 1 r Reserved Read as 0 should be written with 0 ...

Page 890: ...ice requests Additionally the Bus Control Units the Debug Unit the PCP and even the CPU itself can generate service requests to either of the two service providers As shown in Figure 14 1 each TC1796 unit that can generate service requests is connected to one or more Service Request Nodes SRN Each SRN contains a Service Request Control Register mod_SRCx where mod is the identifier of the service r...

Page 891: ... 4 SRNs 4 ADC1 4 SRNs 4 FADC 38 4 5 3 4 16 38 38 PCP Interrupt Arbitration Bus CPU Interrupt Arbitration Bus 5 SRNs 2 SRNs 2 PCP2 Int Ack CCPN 5 2 5 5 5 SRNs 5 Int Req PIPN CPU CCPN Int Ack Software Break point Interrupts ICU 38 38 38 5 5 5 SRNs 5 2 SRNs 2 MSC0 2 SRNs 2 MSC1 2 2 SRNs 2 MLI1 2 FPU 8 SRNs 1 SRN 1 SRN 1 SRN 1 SRN STM Flash GPTA0 GPTA1 LTCA2 Service Requestors DMA DBCU PBCU RBCU SBCU ...

Page 892: ...ters in the TC1796 have the same format In general these registers contain Enable disable information Priority information Service provider destination Service request status bit Software initiated service request set and clear bits Besides being activated by the associated triggering unit through hardware each SRN can also be set or cleared by software via two software initiated service request c...

Page 893: ... rw Service Request Priority Number 00H Service request is never serviced 01H Service request is on lowest priority H FFH Service request is on highest priority TOS 10 rw Type of Service Control 0B CPU service is initiated 1B PCP request is initiated SRE 12 rw Service Request Enable 0B Service request is disabled 1B Service request is enabled SRR 13 rh Service Request Flag 0B No service request is...

Page 894: ...independent of the state of the SRE bit This allows service requests to be handled automatically by hardware or through software polling If SRE 1 pending service requests are passed on to the designated service provider for interrupt arbitration The SRR bit is automatically set to 0 by hardware when the service request is acknowledged and serviced It is recommended that in this case software shoul...

Page 895: ...owledged and serviced Software can poll SRR to check for a pending service request SRR must be cleared by software in this case by writing a 1 to CLRR It is advised not to clear a pending service request flag SRR writing CLRR 1 and to enable the corresponding service request node SRN writing SRE 1 simultaneously at the same write access to the Service Request Control Register When doing this an un...

Page 896: ... number This is unlike traditional interrupt architectures in which their interrupt vector tables are ordered by the source of the interrupt The TC1796 Interrupt Vector Table allows a single peripheral can have multiple priorities for different purposes The range of values for SRPNs used in a system depends on the number of possible active service requests and the user definable organization of th...

Page 897: ... ICU Interrupt Control Register ICR The ICU Interrupt Control Register ICR holds the current CPU priority number CCPN the global interrupt enable disable bit IE the pending interrupt priority number PIPN and bit fields which control the interrupt arbitration process ICR ICU Interrupt Control Register F7E1FE2CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 C ONE CYC CARBC...

Page 898: ...upt Priority Number PIPN is a read only bit field that is updated by the ICU at the end of each interrupt arbitration process It indicates the priority number of the pending service request PIPN is set to 0 when no request is pending and at the beginning of each new arbitration process 00H No valid pending request YYH A request with priority YYH is pending CARBCYC 25 24 rw Number of Arbitration Cy...

Page 899: ...ify write operation The full list of conditions which could block the CPU from immediately responding to an interrupt request generated by the ICU is Current CPU priority ICR CCPN is equal to or higher than the pending interrupt priority ICR PIPN Interrupt system is globally disabled ICR IE 0 CPU is in the process of entering an interrupt or trap service routine CPU is executing non interruptible ...

Page 900: ...as acknowledged the current pending interrupt request any new service request generated by an SRN must wait at least until the end of the next service request arbitration process to be serviced Essentially arbitration in the ICU is performed whenever a new service request is detected regardless of whether or not the CPU is servicing interrupts Because of this the ICR PIPN bit field always reflects...

Page 901: ...arge range of service priorities If not all priorities are needed in a system arbitration can be speeded up by not examining all the bits used to identify all 255 unique priorities For instance if a 6 bit number is enough to identify all priority numbers used in a system meaning that bits 7 6 of all SRPNs are always 0 it is not necessary to perform arbitration on these two bits Three arbitration c...

Page 902: ... ICR CCPN and the state of the global interrupt enable bit ICR IE are automatically saved with the PCXI register bit field PCPN and bit PIE 2 Interrupt system is globally disabled ICR IE is set to 0 3 Current CPU priority number ICR CCPN is set to the value of ICR PIPN 4 PSW is set to a default value a All permissions are enabled that is PSW IO 10B b Memory protection is switched to PRS0 that is P...

Page 903: ...se an MTCR instruction to modify ICR IE and ICR CCPN However this should be performed together with an ISYNC instruction which synchronizes the instruction stream to ensure completion of this operation before the execution of following instructions Note The lower context can also be saved through execution of a SVLCX Save Lower Context instruction 14 6 Exiting an Interrupt Service Routine When an ...

Page 904: ...ster BIV stores the base address of the Interrupt Vector Table It can be assigned to any available code memory Its default on power up is fixed at 0000 0000H However the BIV register can be modified using the MTCR instruction during the initialization phase of the system before interrupts are enabled With this arrangement it is possible to have multiple Interrupt Vector Tables and switch between t...

Page 905: ...table is organized according to the interrupt priorities the TC1796 offers an additional option by allowing spanning several Interrupt Vector Table entries so long as those entries are otherwise unused Figure 14 3 illustrates this The required size of the Interrupt Vector Table depends only on the range of priority numbers actually used in a system Of the 256 vector entries 255 may be used Vector ...

Page 906: ...2007 07 Interrupt V2 0 Figure 14 3 Interrupt Vector Table 8 Words 8 Words MCA05744 Interrupt Vector Table 8 Words 8 Words BIV PN 0 never used PN 1 PN 2 PN 3 PN 4 PN 5 PN 255 Priority Number may not be used if spanned by ISR with PN 2 Service Routine may span several entries ...

Page 907: ...quest PCP service There is a performance trade off that may arise when using this technique because the range of priority numbers used increases This may have an impact on the number of arbitration cycles required to perform arbitration Consider the case in which a system uses only three active interrupt sources that is where there are only three SRNs enabled to request service If these three acti...

Page 908: ...to the values of the interrupted program 14 8 3 Interrupt Priority Groups It is sometimes useful to create groups of interrupts at the same or different interrupt priorities that cannot interrupt each other s ISRs For instance devices that can generate multiple interrupts may need to have interrupts at different priorities interlocked in this way The TC1796 interrupt architecture can be used to cr...

Page 909: ...riority groups demonstrate the power of the TC1796 priority based interrupt ordering system Thus the flexibility of interrupt priority levels ranges from all interrupts in one group to each interrupt request building its own group and to all possible combinations in between Figure 14 4 Interrupt Priority Groups 14 8 4 Splitting Interrupt Service Across Different Priority Levels Interrupt service c...

Page 910: ...e ISR could raise the value of ICR CCPN to a priority that would exclude some or all other interrupts or simply leave interrupts disabled 14 8 5 Using different Priorities for the same Interrupt Source For some applications the urgency of a service request may vary depending on the current state of the system To handle this different priority numbers SRPNs can be assigned at different times to a s...

Page 911: ...vice Request Control Register Thus software can initiate interrupts that are handled by the same mechanism as hardware interrupts After the SRR bit is set in an active SRN there is no way to distinguish between a software initiated interrupt request and a hardware interrupt request For this reason software should only use SRNs and interrupt priority numbers that are not being used for hardware int...

Page 912: ...de SBCU_SRC RBCU 1 RBCU Request Node RBCU_SRC1 DMA 8 DMA Service Request Nodes 7 0 DMA_SRC 7 0 1 FPU Service Request Node DMA_SYSSRC0 1 FLASH Service Request Node DMA_SYSSRC1 2 External Interrupt Nodes 1 0 DMA_SYSSRC2 DMA_SYSSRC3 1 Software Interrupt Request Node DMA_SYSSRC4 4 MLI0 Service Request Nodes 3 0 DMA_MLI0SRC 3 0 2 MLI1 Service Request Nodes 1 0 DMA_MLI1SRC 1 0 PCP 12 PCP Service Request...

Page 913: ...e SSC1_RSRC1 SSC1 Error Interrupt Service Request Node SSC1_ESRC1 MSC0 2 MSC0 Service Request Nodes 1 0 MSC0_SRC 1 0 MSC1 2 MSC1 Service Request Nodes 1 0 MSC1_SRC 1 0 CAN 16 CAN Service Request Nodes 15 0 CAN_SRC 15 0 1 GPTA 38 GPTA0 Service Request Nodes 37 00 GPTA0_SRC 37 00 38 GPTA1 Service Request Nodes 37 00 GPTA1_SRC 37 00 16 LTCA2 Service Request Nodes 15 00 LTCA2_SRC 15 00 ADC0 4 ADC0 Ser...

Page 914: ...trigger any action NMI is equipped with a noise suppression filter which suppresses glitches below 10 ns pulse width NMI pulses with a width above 100 ns are safely recognized as a valid signal The noise suppression filter is switched off when pin BYPASS 1 14 10 2 Phase Locked Loop NMI The PLL clock generation unit sets the NMIPLL flag when it detects a loss in the synchronization with the externa...

Page 915: ... error flag mechanism has some effects on na NMI trap handling routine Figure 14 5 shows a trap handler flow diagram that especially handles a typical SRAM parity error NMI trap recognition Additional details about SRAM parity error control are described in section SRAM Parity Control on Page 5 37 Figure 14 5 NMI Trap Handler Routine for Parity Error Handling MCA06449a V1 SCU_PETSR V2 NMIPER 1 no ...

Page 916: ... Watchdog Timer times out it sets NMISR NMIWDT If the PLL loses its clock signal it sets NMISR PLL The bits in NMISR are OR ed together to generate an NMI trap request to the CPU If one of the NMISR bits is newly asserted while another bit is set no new NMI trap request is generated All flags are cleared automatically after a read of NMISR Therefore after reading NMISR the NMI TSR must check all b...

Page 917: ...ag This flag indicates whether or not a Watchdog Timer NMI request has occurred 0B No watchdog NMI occurred 1B The Watchdog Timer has entered the pre warning phase due to a watchdog error NMIPER 3 rh Parity Error NMI Flag This flag indicates whether or not SRAM parity error NMI request has occurred 0B No SRAM parity error NMI occurred 1B An SRAM parity error NMI has been detected The SRAM module w...

Page 918: ...fSTM At fSTM 75 MHz for example the STM counts 30 47 years before overflowing Thus it is capable of continuously timing the entire expected product life time of a system without overflowing 15 2 Operation The STM is an upward counter running either at the system clock frequency fSYS or at a fraction of it The STM clock frequency is fSTM fSYS RMC with RMC 0 7 default after reset is fSTM fSYS 2 sele...

Page 919: ...ue of the timer at exactly the same time when the lower part is read The second read operation would then read the content of the STM_CAP to get the complete timer value The STM can also be read in sections from seven registers STM_TIM0 through STM_TIM6 that select increasingly higher order 32 bit ranges of the STM These can be viewed as individual 32 bit timers each with a different resolution an...

Page 920: ...TM Module Registers STM Module 00H STM_CAP STM_TIM6 STM_TIM5 00H 55 47 39 31 23 15 7 56 Bit System Timer Address Decoder Clock Control Enable Disable fSTM MCB05746 31 23 15 7 Compare Register 0 Interrupt Control Compare Register1 STMIR1 STMIR0 PORST 0 0 31 23 15 7 0 STM_TIM4 STM_TIM3 STM_TIM2 STM_TIM1 STM_TIM0 STM_CMP1 STM_CMP0 ...

Page 921: ...M 236 fSTM 213 ns 916 2 s STM_TIM2 39 8 256 fSTM 240 fSTM 3 41 µs 244 3 min STM_TIM3 43 12 4096 fSTM 244 fSTM 54 6 µs 65 1 h STM_TIM4 47 16 65536 fSTM 248 fSTM 0 874 ms 43 44 days STM_TIM5 51 20 220 fSTM 252 fSTM 13 98 ms 1 90 yr STM_TIM6 55 32 232 fSTM 256 fSTM 57 3 s 30 47 yr STM_CAP 55 32 232 fSTM 256 fSTM 57 3 s 30 47 yr STM_TIM0 31 0 fSTM 232 fSTM 26 7 ns 114 5 s 37 5 STM_TIM1 35 4 16 fSTM 23...

Page 922: ...ation in the 56 bit STM that is taken for the compare operation can be programmed from 0 to 24 These programming capabilities make compare functions very flexible It even makes it possible to detect bit transitions of a single bit n n 0 to 24 within the 56 bit STM by setting MSIZE 0 and MSTART n Figure 15 2 Compare Mode Operation Figure 15 2 shows an example of the compare operation In this exampl...

Page 923: ...ware on a compare match event The interrupt request flags can be set STM_ISSR CMPxIRS or cleared STM_ISSR CMPxIRR by software Note that setting STM_ICR CMPxIR by writing a 1 into STM_ISSR CMPxIRS does not generate an interrupt at STMIRx The compare match interrupts from CMP0 and CMP1 can be further directed by STM_ICR CMPxOS to either output signal STMIR0 or STMIR1 The STMIR0 and STMIR1 outputs ar...

Page 924: ...xIRR set Otherwise undesired compare match interrupt events are triggered accidentally 15 3 Kernel Registers This section describes the kernel registers of the STM The STM registers can be divided into four types as shown in Figure 15 4 Note In the TC1796 all kernel registers are readable in suspend mode STM Registers Overview Figure 15 4 STM Registers The complete and detailed address map of the ...

Page 925: ...2 STM_TIM3 STM Timer Register 3 1CH Page 15 12 STM_TIM4 STM Timer Register 4 20H Page 15 12 STM_TIM5 STM Timer Register 5 24H Page 15 13 STM_TIM6 STM Timer Register 6 28H Page 15 13 STM_CAP STM Timer Capture Register 2CH Page 15 14 STM_CMP0 STM Compare Register 0 Low Part 30H Page 15 15 STM_CMP1 STM Compare Register 0 High Part 34H STM_CMCON STM Compare Match Control Register 38H Page 15 16 STM_IC...

Page 926: ...S OE SB WE E DIS SP EN DIS S DIS R r rw r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the STM module 0B No disable requested 1B Disable requested DISS 1 r Module Disable Status Bit Bit indicates the current status of the STM module 0B STM module is enabled 1B STM module is disabled SPEN 2 rw Module Suspend Enable for OCDS Used...

Page 927: ... This bit field is not affected by a hardware reset operation HDRST 0 0 7 6 31 11 r Reserved Read as 0 should be written with 0 STM_ID STM Module Identification Register 08H Reset Value 0000 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first r...

Page 928: ...erlying STM counter STM_TIM0 STM Timer Register 0 10H Reset Value 0000 0000H 31 0 STM 31 0 r Field Bits Type Description STM 31 0 31 0 r System Timer Bits 31 0 This bit bield contains bits 31 0 of the 56 bit STM STM_TIM1 STM Timer Register 1 14H Reset Value 0000 0000H 31 0 STM 35 4 r Field Bits Type Description STM 35 4 31 0 r System Timer Bits 35 4 This bit bield contains bits 35 4 of the 56 bit ...

Page 929: ... bield contains bits 39 8 of the 56 bit STM STM_TIM3 STM Timer Register 3 1CH Reset Value 0000 0000H 31 0 STM 43 12 r Field Bits Type Description STM 43 12 31 0 r System Timer Bits 43 12 This bit bield contains bits 43 12 of the 56 bit STM STM_TIM4 STM Timer Register 4 20H Reset Value 0000 0000H 31 0 STM 47 16 r Field Bits Type Description STM 47 16 31 0 r System Timer Bits 47 16 This bit bield co...

Page 930: ... r Field Bits Type Description STM 51 20 31 0 r System Timer Bits 51 20 This bit bield contains bits 51 20 of the 56 bit STM STM_TIM6 STM Timer Register 6 28H Reset Value 0000 0000H 31 24 23 0 0 STM 55 32 r r Field Bits Type Description STM 55 32 23 0 r System Timer Bits 55 32 This bit bield contains bits 55 32 of the 56 bit STM 0 31 24 r Reserved Read as 0 ...

Page 931: ...TM_CAP 55 32 r r Field Bits Type Description STM 55 32 23 0 r Captured System Timer Bits 55 32 The capture register STM_CAP always captures the STM bits 55 32 when one of the registers STM_TIM0 to STM_TIM5 is read This capture operation is performed in order to enable software to operate with a coherent value of all the 56 STM bits at one time stamp This bit bield contains bits 55 32 of the 56 bit...

Page 932: ...M Compare Register holds up to 32 bits its value is compared to the value of the STM STM_CMPx x 0 1 STM Compare Register x 30H x 4H Reset Value 0000 0000H 31 0 CMPVAL rw Field Bits Type Description CMPVAL 31 0 rw Compare Value of Compare Register x This bit field holds up to 32 bits of the compare value right adjusted ...

Page 933: ...ster CMP0 starting from bit 0 that are used for the compare operation with the STM 00000B CMP0 0 used for compare operation 00001B CMP0 1 0 used for compare operation B 11110B CMP0 30 0 used for compare operation 11111B CMP0 31 0 used for compare operation MSTART0 12 8 rw Start Bit Location for CMP0 This bit field determines the lowest bit number of the 56 bit STM that is compared with the content...

Page 934: ... 11111B CMP1 31 0 used for compare operation MSTART1 28 24 rw Start Bit Location for CMP1 This bit field determines the lowest bit number of the 56 bit STM that is compared with the content of register CMP1 bit 0 The number of bits to be compared is defined by bit field MSIZE1 00000B STM 0 is the lowest bit number 00001B STM 1 is the lowest bit number B 10111B STM 23 is the lowest bit number 11000...

Page 935: ...bit enables the compare match interrupt with compare register CMP0 0B Interrupt on compare match with CMP0 disabled 1B Interrupt on compare match with CMP0 enabled CMP0IR 1 rh Compare Register CMP0 Interrupt Request Flag This bit indicates whether or not a compare match interrupt request of compare register CMP0 is pending CMP0IR must be cleared by software 0B A compare match interrupt has not bee...

Page 936: ...tes whether or not a compare match interrupt request of compare register CMP1 is pending CMP1IR must be cleared by software 0B A compare match interrupt has not been detected since the bit has been cleared for the last time 1B A compare match interrupt has been detected CMPIR1 must be cleared by software and can be set by software too see CMPISRR register After an STM reset CMP1IR is immediately s...

Page 937: ...CMP 0 IRS CMP 0 IRR r w w w w Field Bits Type Description CMP0IRR 0 w Reset Compare Register CMP0 Interrupt Flag 0B Bit ICR CMP0IR is not changed 1B Bit ICR CMP0IR is cleared CMP0IRS 1 w Set Compare Register CMP0 Interrupt Flag 0B Bit ICR CMP0IR is not changed 1B Bit ICR CMP0IR is set The state of bit CMP0IRR is don t care in this case CMP1IRR 2 w Reset Compare Register CMP1 Interrupt Flag 0B Bit ...

Page 938: ...s Manual STM_SRC0 STM Service Request Control Register 0 FCH Reset Value 0000 0000H STM_SRC1 STM Service Request Control Register 1 F8H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service ...

Page 939: ... Supervisor Mode is active and bit ENDINIT 0 Because servicing the Watchdog and modifications of the ENDINIT bit are critical functions that must not be allowed in case of a system malfunction a sophisticated scheme is implemented that requires a password and guard bits during accesses to the WDT control register Any write access that does not deliver the correct password or the correct value for ...

Page 940: ... first access or invalid guard bits during second access trigger the Watchdog reset generation Overflow Error Detection An overflow of the counter triggers the Watchdog reset generation Watchdog function can be disabled access protection and ENDINIT monitor function remain enabled Double Reset Detection If a Watchdog induced reset occurs twice a severe system malfunction is assumed and the TC1796 ...

Page 941: ...s will not be modified in this case In this case an interrupt in the corresponding bus control units of the TC1796 is generated instead of a bus error trap There is an exception If read modify write instructions are used for the write access a bus error trap is generated instead of an interrupt An additional line controlled through a separate bit makes it possible to protect against unintentional ...

Page 942: ...ap and interrupt vector table pointer as well as the interrupt stack pointer are Endinit protected WDT_CON1 The WDT Control Register 1 which controls the disabling and the input frequency of the WDT is Endinit protected In addition its bits will only have an effect on the WDT when ENDINIT is properly set to 1 again RST_REQ OSC_CON PLL_CLC SCU_SCLKFDR SCU_EMSR SCU_TCCON SCU_CON SCU_TCLR0 SCU_TCLR1 ...

Page 943: ...o WDT_CON0 The reload value was set to REL_1 4 Time Out Mode is terminated and Normal Mode entered again by setting ENDINIT to 1 The reload value WDTREL has been changed to REL_2 and the timer input clock was set to the fast clock Events 3 and 4 constitute a WDT service sequence 5 The WDT was not serviced and continued to count until overflow Reset Prewarning Mode is entered Timer counts with sele...

Page 944: ...cess error WDTAE While WDT_SR is a read only register the control registers can be read and written Reading these registers is always possible a write access however must follow certain protocols Register WDT_CON1 is Supervisor Mode and Endinit protected thus Supervisor Mode must be active and bit ENDINIT must be 0 for a successful write to this register If one or both conditions are not met a bus...

Page 945: ...from one mode to the other As well as these major operating modes the WDT has special behavior during power saving and OCDS suspend modes Detailed discussions of each of the modes can be found on Page 16 13 Figure 16 3 is a state diagram of the different modes of the WDT and the transition possibilities Please refer to the description for the conditions for changing from one state to the other Fig...

Page 946: ...uence to the WDT control register WDT_CON0 This reloads the timer with the start value and normal operation continues If the WDT is not serviced before the timer overflows or if an invalid access to the WDT is performed a system malfunction is assumed Normal Mode is terminated a WDT NMI request WDT_NMI is requested and Prewarning Mode is entered A reset of the TC1796 is imminent and can no longer ...

Page 947: ... If the part would be immediately reset on the detection of a Watchdog error this debugging information would never be available and investigating the cause of the malfunction would be a very difficult task In Prewarning Mode after having generated the NMI request the WDT counts for a specified period of time and then generates a Watchdog reset for the device This reset generation cannot be avoide...

Page 948: ..._CON0 as an unlocking password If the password matches the requirements WDT_CON0 will be unlocked as soon as the Password Access has finished The unlocked condition will be indicated by WDT_CON0 WDTLCK 0 If WDT_CON0 is successfully unlocked a subsequent write access can modify it as described on Page 16 11 If an improper password value is written to WDT_CON0 during the Password Access a Watchdog A...

Page 949: ...E is set and the Prewarning Mode is entered After the Modify Access has completed WDT_CON0 WDTLCK is set to 1 again by hardware automatically re locking WDT_CON0 Before the register can be modified again a Valid Password Access must be executed again Table 16 3 Modify Access Bit Pattern Requirements Bit Position Value 0 User definable desired value for the ENDINIT bit WDT_CON0 ENDINIT 1 Fixed must...

Page 950: ...to WDT_CON0 in order to successfully open WDT_CON0 Valid Password Access A Password Access with the correct password value A Valid Password Access opens register WDT_CON0 for one and only one Modify Access Bit WDTLCK is set to 0 after this access The WDT is placed into the Time Out Mode after a Valid Password Access in Normal Mode or Disabled Mode Modify Access The second access of an Watchdog Acc...

Page 951: ...s value Bits WDTAE and WDTOE depend on their state before the reset if the reset was caused by the Watchdog For any other reset PORST HDRST SRST PWDRST they are 0 WDTIS retains its previous value After reset ENDINIT is 0 Thus access to Endinit protected registers is enabled If Time Out Mode was entered through other reasons ENDINIT might or might not be 0 Operation Timer starts counting up from FF...

Page 952: ...ble Mode 2 Bit WDTOE is set to 1 and the WDT enters the Prewarning Mode 3 Bit WDTAE is set to 1 and the WDT enters the Prewarning Mode Table 16 5 WDT Normal Mode State Action Description Entry Only from Time Out Mode by writing ENDINIT to 1 with a Valid Modify Access a Valid Password Access must have been executed first while bit WDTDR 0 Actions on Entry WDTTIM is loaded with the value of WDTREL B...

Page 953: ... the detection of access errors and the entry of Prewarning Mode nor the entry of Time Out Mode on a Valid Password Access Table 16 6 WDT Disable Mode State Action Description Entry Only from Time Out Mode by writing ENDINIT to 1 with a Valid Modify Access a Valid Password Access must have been executed first while bit WDTDR 1 Actions on Entry Bits WDTAE WDTOE WDTPR and WDTTO are cleared Bit WDTDS...

Page 954: ...quest to the CPU WDTTIM is set to FFFCH WDTPR is set to 1 WDTDS is set to 0 WDTIS retains its value WDTTO retains its previous value If entry into Prewarning Mode was from Time Out Mode WDTTO is 1 In all other cases WDTTO is 0 Bits WDTAE and WDTOE indicate whether Prewarning Mode was entered due to an access or an overflow error They have been set accordingly on exit of the previous mode Operation...

Page 955: ...its state from 0 to 1 the CPU is awakened and continues to execute the instruction that follows the instruction that was last executed before entering the Idle or Sleep Mode Note Before switching into a non running power management mode software should perform a Watchdog service sequence At the Modify Access the Watchdog reload value WDT_CON0 WDTREL should be programmed such that the wake up occur...

Page 956: ... calculate a Watchdog period is 16 1 The parameter startvalue represents the fixed value FFFCH for the calculation of the Time out Period and the user programmable reload value WDTREL for the calculation of the Normal Period Note that the exponent 1 WDTIS 6 results to 0 if WDTIS is 1 and to 6 if WDTIS is 0 This results in the value 256 being multiplied by either 1 20 1 or by 64 26 giving the two d...

Page 957: ...er reset the WDT counter is initially set to FFFCH when Time Out Mode is entered and Time Out Mode expires when the counter overflows However there are two differences to the Time out Period after reset First the input frequency can be either fSYS 256 or fSYS 16384 depending on the programmed state of bit WDT_SR WDTIS before the Time out Period was entered Second because there is no synchronizatio...

Page 958: ...ded with the 16 bit reload value WDT_CON0 WDTREL The WDT Period can be varied over a wide range with these two parameters Again since there is no synchronization of the clock divider to the mode transitions of the Watchdog the next clock pulse incrementing the counter may come after one clock divider period or immediately after the counter was reloaded Thus it is recommended that the reload value ...

Page 959: ... the WDT reload value before going to Idle or Sleep Mode As described on Page 16 17 the state of bit 15 of the Watchdog counter is used to wake up from these modes Thus the reload value should be chosen such that it is less then 7FFEH bit 15 0 otherwise an immediate wake up could occur Only half of the maximum periods shown in Table 16 9 can be used for the wake up period ...

Page 960: ...lid Modify Access WDT_CON0 ENDINIT must be set to 1 which will exit Time Out Mode The WDT is switched to the operation determined by the new values of WDTIS and WDTDS Note The action described above must absolutely be performed during initialization of the device to properly terminate this mode Even if the Watchdog function will not be used in an application and the WDT will be disabled a valid ac...

Page 961: ...e is the only occasion when WDT_CON0 must be accessed again after the system is initialized If there are no further changes to critical system registers needed no further accesses to WDT_CON0 WDT_CON1 or WDT_SR are necessary However it is always recommended that the WDT be used in an application for safety reasons 16 5 3 Servicing the Watchdog Timer If the WDT is used in an application and is enab...

Page 962: ...are can modify this bit field each time it executes a Watchdog service sequence The next service sequence needs to take this new value into account for its Password Access and it again changes the value during its Modify Access Up to 256 different password values can be used In this way each service sequence is unique If a malfunction occurs that for instance would result in the omission of one or...

Page 963: ...ther again To determine the correct password software uses a value returned from the path that was executed This value must match the value in WDTPW otherwise the wrong path was executed Figure 16 5 shows an example It is also possible to have the different paths of a program compute the full or partial password to unlock register WDT_CON0 The password will only match at the next MCA05753 Password...

Page 964: ...echanism will detect this and issue a reset of the device after the prewarning phase Figure 16 5 Monitoring Program Sequences MCA05754 Determine branch condition PW A or B or C Password access write xyH to WDTPW Modify access set WDTPW to PW Perform Branch Path B PW B Return PW Path A PW A Return PW Path C PW C Return PW WDTPW PW Next expected Service Sequence n Password access write PW to WDTPW M...

Page 965: ... only a time limited window for the second access Although computing the required values from the current contents of the Watchdog registers is one option using predetermined values that are set at compile time of the program may be the better approach in many cases Usually handling the WDT is performed by one and only one task Thus the problem will not occur that another task might have changed s...

Page 966: ...and detailed address map of the SCU which includes the WDT registers is shown in Table 18 3 on Page 18 7 Table 16 11 Registers Address Space WDT Registers Module Base Address End Address Note WDT F000 0000H F000 00FFH Table 16 12 Registers Overview WDT Kernel Registers Register Short Name Register Long Name Offset Address Description see WDT_CON0 Watchdog Timer Control Register 0 20H Page 16 29 WD...

Page 967: ... Reset Value FFFC 0002H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTREL rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTPW WDTHPW 1 WDTHPW 0 WDT LCK END INIT rw w w rw rw Field Bits Type Description ENDINIT 0 rw End of Initialization Control Bit 0B Access to Endinit protected registers is permitted default after reset 1B Access to Endinit protected registers is not permitted ENDINIT controls th...

Page 968: ...word 0 This bit field must be written with the value of the bits WDT_CON1 WDTDR and WDT_CON1 WDTIR during a Password Access This bit field must be written with 0 s during a Modify Access to WDT_CON0 When read these bits always return 0 WDTHPW1 7 4 w Hardware Password 1 This bit field must be written to 1111B during both a Password Access and a Modify Access to WDT_CON0 When read these bits always ...

Page 969: ...nput frequency to fSYS 256 This bit can only be modified if WDT_CON0 ENDINIT is set to 0 WDT_SR WDTIS is updated by this bit only when ENDINIT is set to 1 again As long as ENDINIT is left at 0 WDT_SR WDTIS controls the current input frequency of the WDT When ENDINIT is set to 1 again WDT_SR WDTIS is updated with the state of WDTIR WDTDR 3 rw Watchdog Timer Disable Request Control Bit 0B Request to...

Page 970: ...DTDS and WDTIS are always 0 after any reset 0 1 0 31 4 r Reserved Read as 0 should be written with 0 WDT_SR Watchdog Timer Status Register 28H Reset Value FFFC 0010H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTTIM rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 WDT PR WDT TO WDT DS WDT IS WDT OE WDT AE r rh rh rh rh rh rh Field Bits Type Description WDTAE 0 rh Watchdog Access Error Status Flag 0...

Page 971: ...the state of bit WDT_CON1 WDTIR after WDT_CON0 ENDINIT is written with 1 during a Valid Modify Access to register WDT_CON0 WDTDS 3 rh Watchdog Enable Disable Status Flag 0B WDT is enabled default after reset 1B WDT is disabled This bit is updated with the state of bit WDT_CON1 WDTDR after WDT_CON0 ENDINIT is written with 1 during a Valid Modify Access to register WDT_CON0 WDTTO 4 rh Watchdog Time ...

Page 972: ...er reset 1B The Watchdog is operating in Prewarning Mode This bit is set to 1 when a Watchdog error is detected The WDT has issued an NMI trap and is in Prewarning Mode A reset of the chip occurs after the prewarning period has expired WDTTIM 31 16 rh WDT Value Reflects the current content of the WDT 0 15 6 r Reserved Read as 0 Field Bits Type Description ...

Page 973: ...bug hardware may become master of the internal buses and read or write the on chip register memory resources The Cerberus also makes it possible to set breakpoint and trigger conditions as well as to control user program execution run stop break single step OCDS Level 2 The OCDS Level 2 makes it possible to implement program tracing capabilities for enhanced debuggers by extending the OCDS Level 1...

Page 974: ...onents The OCDS of the TC1796 consists of the following building blocks OCDS Level 1 module of TriCore OCDS Level 2 interface of TriCore SBCU M U X MCB05756_mod TCK TMS TDI TDO Remote Peripheral Bus Multi Core Break Switch MCBS JTAG Debug Interface JDI OCDS System Control Unit OSCU TRST BRKIN BRKOUT TR 15 0 TRCLK JTAG Controller Cerberus SPB Peripheral Unit 1 RPB Peripheral Unit 1 RPB Peripheral U...

Page 975: ...ng also possible Concurrent access to memory and SFRs via Cerberus possible PCP Level 1 OCDS Break by DEBUG instruction or Break signal from break switch Concurrent access to memory and SFRs via Cerberus possible DMA Level 1 OCDS Break request on error Event generation on specified channel activity Suspending pre selected channels BCU Level 1 OCDS Event generation on specified transactions 16 pin ...

Page 976: ...ol via a PC port 2 The debugger hardware interface adapter connecting the TC1796 JTAG interface in the target system with the PC port parallel serial or USB This configuration makes it possible to realize a cheap debugging environment that permits comprehensive real time debugging tasks to be performed Figure 17 2 Typical OCDS Level 1 Hardware Connections 17 2 1 TriCore CPU Level 1 OCDS The TriCor...

Page 977: ...riority requests can still be serviced when the core is in emulation mode by interrupting the monitor program 17 2 1 1 Basic Concept The TriCore CPU in the TC1796 provides OCDS with the following two basic parts Debug Event Trigger Generation Debug Event Trigger Processing The first part controls the generation of debug events and the second part controls what actions are taken when a debug event ...

Page 978: ...event generation unit and to rely on help from the external debug system or debug monitor to implement more complex breakpoints Activation of the External Break Input Pin BRKIN When activating the TC1796 device pin BRKIN 0 the MCBS unit induces a break event as specified in a External Break Input Event Specifier Register EXEVT Execution of a DEBUG Instruction The TriCore architecture supports a me...

Page 979: ... CREVT or SWEVT or EXEVT or TR0EVT or TR1EVT The action that is performed when a MTCR or MFCR instruction is executed on user core SFRs defined by the content of the Emulator Resource Protection Event Specifier Register CREVT 17 2 1 3 Debug Actions Four types of debug actions are available Assert BRKOUT signals by the MCBS unit Halt the CPU core Cause a breakpoint trap Generate an interrupt reques...

Page 980: ...tionally the Break Switch can send an external break request to the PCP with the same consequence Debug Exit or Error Exit Table 17 1 TriCore OCDS Registers Register Short Name Register Long Name Address DBGSR Debug Status Register F7E1 FD00H EXEVT External Break Input Event Specifier Register F7E1 FD08H CREVT Core SFR Access Break Event Specifier Register F7E1 FD0CH SWEVT Software Break Event Spe...

Page 981: ...al which is sent to the Break Switch The OCDS registers of SBCU and RBCU are described in Chapter 6 starting in section SBCU and RBCU Registers on Page 6 34 17 2 4 DMA OCDS Level 1 The DMA controller in the TC1796 provides the following debugging capabilities Hard suspend mode of the DMA controller for test purposes only Soft suspend mode of DMA channels Break signal generation In suspend modes th...

Page 982: ...t state of the CPU PCP cores The trace output lines are grouped into three parts 5 bits of pipeline status information 8 bit indirect PC bus information 3 bits of breakpoint qualification information With this information an external emulator can reconstruct a cycle by cycle image of the instruction flow through the CPU or PCP The trace information can be captured by the external debugger hardware...

Page 983: ... Controller the break in and break out features of the CPU can be used at the same time Selecting DMA trace and enabling the break out lines of both units makes it possible to distinguish between DMA trace events and CPU break out activation during DMA trace the BRKOUT output becomes activated only together with one of the trace port pins being active 1 as well if BRKOUT output becomes activated w...

Page 984: ...Generation of external break condition via pins BRKIN BRKOUT Full access to the complete SPB RPB FPI Bus address space via JTAG No user resources hardware software are required Minimum run time impact Generic memory read write functionality Write word half word and byte Block read and write Full support for communication between an on chip monitor program and the external debugger Pending reads wr...

Page 985: ...e request is not actively executed by the Cerberus but it sets request bits in the CPU accessible IOSR register to signal the monitor that the debugger wants to send IO_WRITE_WORD or receive IO_READ_WORD a value The software monitor has to poll register IOSR The IOADDR register is not used 17 4 3 Triggered Transfers Triggered Transfers are an OCDS specific feature of the Cerberus They can be used ...

Page 986: ...e PCP2 Seven break in sources TriCore PCP DMA SBCU RBCU MLI0 MLI1 Two port pins BRKIN and BRKOUT Two independent break buses Suspend generation supports delayed suspend Break to suspend converter Create interrupt request with a break coming from a source Synchronous restart of the system BRKOUT MCA05760_mod Multi Core Break Switch MCBS BRKIN BRKOUT TriCore CPU PCP2 DMA SBCU RBCU MLI0 MLI1 BRKOUT S...

Page 987: ...ramming Interface It allows several debugger applications to share the same JTAG interface For example it is possible to run a PCP debugger concurrently with a TriCore debugger on the same TC1796 device In addition the tool specific PC interfaces such as Ethernet printer port or even USB can be hidden from the debugger software by the JTAG API layer The JTAG API enables the debugger vendor to forg...

Page 988: ...Register 1 bit 1 ID JTAG Module Identification Register 32 bit 1 INSTRUCTION JTAG Instruction Register 8 bit 1 IOPATH IO Client Selection Register 2 bit 1 Cerberus Registers OJCONF OSCU Configuration by JTAG Register 1 CBS_OEC Cerberus OCDS Enable Control Register F000 0478H CBS_OCNTRL Cerberus OSCU Configuration and Control Register F000 047CH MCA05761 CLIENT_ID1 JDI Registers OJCONF1 OSCU Regist...

Page 989: ...R Cerberus Status Register F000 046CH CBS_INTMOD Cerberus Internal Mode Status and Control Register F000 0484H CBS_ICTSA Cerberus Internal Controlled Trace Source Address Register F000 0488H CBS_ICTTA Cerberus Internal Controlled Trace Target Address Register F000 048CH CBS_MCDBBS Cerberus Break Bus Switch Configuration Register F000 0470H CBS_MCDBBSS Cerberus Break Bus Switch Status Register F000...

Page 990: ...ed by a reset operation SV Access permitted in Supervisor Mode R Read only register 32 Only 32 bit word accesses are permitted to this register address range E Endinit protected register address PW Password protected register address NC No change indicated register is not changed BE Indicates that an access to this address range generates a Bus Error nBE Indicates that no Bus Error is generated wh...

Page 991: ... F000 0300H F000 03FFH BE BE On Chip Debug Support Cerberus F000 0400H F000 04FFH see Page 18 14 256 byte Reserved F000 0500H F000 07FFH BE BE MicroSecond Channel 0 MSC0 F000 0800H F000 08FFH see Page 18 16 256 byte MicroSecond Channel 1 MSC1 F000 0900H F000 09FFH see Page 18 17 256 byte Async Sync Serial Interface 0 ASC0 F000 0A00H F000 0AFFH see Page 18 20 256 byte Async Sync Serial Interface 1 ...

Page 992: ...General Purpose Timer Array 0 GPTA0 F000 1800H F000 1FFFH see Page 18 33 8 256 byte General Purpose Timer Array 1 GPTA1 F000 2000H F000 27FFH see Page 18 42 8 256 byte Local Timer Cell Array 2 LTCA2 F000 2800H F000 2FFFH see Page 18 50 8 256 byte Reserved F000 3000H F000 3BFFH BE BE Direct Memory Access Controller DMA F000 3C00H F000 3EFFH see Page 18 53 3 256 byte Reserved F000 3F00H F000 3FFFH B...

Page 993: ...see Page 18 79 256 byte Synchronous Serial Interface 0 SSC0 F010 0100H F010 01FFH see Page 18 81 256 byte Synchronous Serial Interface 1 SSC1 F010 0200H F010 02FFH see Page 18 82 256 byte Fast Analog to Digital Converter FADC F010 0300H F010 03FFH see Page 18 84 256 byte Analog to Digital Converter 0 ADC0 F010 0400H F010 05FFH see Page 18 87 2 256 byte Analog to Digital Converter 1 ADC1 F010 0600H...

Page 994: ...Windows F020 0000H F023FFFFH nE nE 4 64 Kbyte MLI1 Large Transfer Windows F024 0000H F027 FFFFH nE nE 4 64 Kbyte Reserved F028 0000H F7E0 FEFFH BE BE CPU CPU Slave Interface Registers CPS F7E0 FF00H F7E0 FFFFH see Page 18 104 256 byte CPU Core SFRs GPRs F7E1 0000H F7E1 FFFFH see Page 18 105 64 Kbyte Reserved F7E2 0000H F7FF FFFFH BE BE External Bus Interface Unit EBU F800 0000H F800 03FFH see Page...

Page 995: ...rol Unit DBCU F87F FA00H F87F FAFFH see Page 18 122 256 byte Reserved F87F FB00H F87F FBFFH BE BE CPU DMI Registers F87F FC00H F87F FCFFH see Page 18 123 256 byte PMI Registers F87F FD00H F87F FDFFH see Page 18 124 256 byte Program Local Memory Bus Control Unit PBCU F87F FE00H F87F FEFFH see Page 18 125 256 byte DLMB to SPB Bus Bridge LFI F87F FF00H F87F FFFFH see Page 18 126 256 byte Reserved F88...

Page 996: ... 002C C0XXH SCU_ SCLKFDR SCU System Clock Fractional Divider Register F000 000CH U SV SV E 0000 0000H RST_REQ Reset Request Register F000 0010H U SV U SV E 0000 0000H RST_SR Reset Status Register F000 0014H U SV BE see Page 4 4 OSC_CON Oscillator Control Register F000 0018H U SV SV E see Page 3 9 Reserved F000 001CH BE BE WDT_CON0 Watchdog Timer Control Register 0 F000 0020H U SV U SV PW FFFC 0002...

Page 997: ...STAT SCU Status Register F000 0054H U SV BE 0000 E000H SCU_ TCLR0 SCU Temperature Compensation 0 Level Register F000 0058H U SV U SV E 02FF FFFFH SCU_ TCLR1 SCU Temperature Compensation 1 Level Register F000 005CH U SV U SV E 02FF FFFFH Reserved these locations must not be read and written F000 0060H F000 0068H Reserved F000 006CH BE BE MANID Manufacturer Identification Register F000 0070H U SV BE...

Page 998: ...0H TGADC1 Trigger Gating ADC1 Register F000 00A0H U SV U SV 0000 0000H Reserved F000 00A4H BE BE Reserved these locations should not be written F000 00A8H F000 00ACH SCU_ PTCON SCU Pad Test Control Register F000 00B0H U SV SV E 0000 0000H SCU_ PTDAT0 SCU Pad Test Data Register 0 F000 00B4H U SV U SV XXXX XXXXH SCU_ PTDAT1 SCU Pad Test Data Register 1 F000 00B8H U SV U SV XXXX XXXXH SCU_ PTDAT2 SCU...

Page 999: ...0 SCU_ PETSR SCU Parity Error Trap Status Register F000 00D4H U SV BE 0000 0000H Reserved F00000D8H F000 00F8H BE BE Reserved this location should not be written F000 00FCH nBE nBE Table 18 3 Address Map of SCU and WDT cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1000: ...SV SV 0000 0000H SBCU_ EADD SBCU Error Address Capture Register F000 0124H U SV SV 0000 0000H SBCU_ EDAT SBCU Error Data Capture Register F000 0128H U SV SV 0000 0000H Reserved F000 012CH BE BE SBCU_ DBCNTL SBCU Debug Control Register F000 0130H U SV SV 0000 7003H SBCU_ DBGRNT SBCU Debug Grant Mask Register F000 0134H U SV SV 0000 FFFFH SBCU_ DBADR1 SBCU Debug Address 1 Register F000 0138H U SV SV...

Page 1001: ...BOST SBCU Debug Trapped Bus Operation Signals Register F000 014CH U SV BE 0000 3180H Reserved F000 0150H F000 01F8H BE BE SBCU_SRC SBCU Service Request Control Register F000 01FCH U SV SV 0000 0000H Table 18 4 Address Map of SBCU cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1002: ...21CH U SV nBE 0000 0000H STM_TIM4 STM Timer Register 4 F000 0220H U SV nBE 0000 0000H STM_TIM5 STM Timer Register 5 F000 0224H U SV nBE 0000 0000H STM_TIM6 STM Timer Register 6 F000 0228H U SV nBE 0000 0000H STM_CAP STM Timer Capture Reg F000 022CH U SV nBE 0000 0000H STM_CMP0 STM Compare Register 0 F000 0230H U SV U SV 0000 0000H STM_CMP1 STM Compare Register 1 F000 0234H U SV U SV 0000 0000H STM...

Page 1003: ...figuration Register F000 0470H U SV SV 0000 0000H CBS_ MCDSSG Cerberus Suspend Signal Generation Status and Control Register F000 0474H U SV SV 0000 0000H CBS_OEC Cerberus OCDS Enable Control Register F000 0478H U SV SV 0000 0000H CBS_ OCNTRL Cerberus OSCU Configuration and Control Register F000 047CH U SV SV 0000 0000H CBS_ OSTATE Cerberus OSCU Status Register F000 0480H U SV SV 0000 0000H CBS_ I...

Page 1004: ...erus Suspend Signal Generation Configuration Register F000 0494H U SV SV 0000 0000H Reserved F000 0498H F000 04F8H BE BE CBS_SRC Cerberus Service Request Control Register F000 04FCH U SV U SV 0000 0000H Table 18 6 Address Map of Cerberus cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1005: ...MSC0 Downstream Control Register F000 0814H U SV U SV 0000 0000H MSC0_DSS MSC0 Downstream Status Register F000 0818H U SV U SV 0000 0000H MSC0_DD MSC0 Downstream Data Register F000 081CH U SV U SV 0000 0000H MSC0_DC MSC0 Downstream Command Register F000 0820H U SV U SV 0000 0000H MSC0_ DSDSL MSC0 Downstream Select Data Source Low Register F000 0824H U SV U SV 0000 0000H MSC0_ DSDSH MSC0 Downstream...

Page 1006: ...ervice Request Control Register 1 F000 08F8H U SV U SV 0000 0000H MSC0_ SRC0 MSC0 Service Request Control Register 0 F000 08FCH U SV U SV 0000 0000H Micro Second Channel 1 MSC1 MSC1_CLC MSC1 Clock Control Register F000 0900H U SV SV E 0000 0003H Reserved F000 0904H BE BE MSC1_ID MSC1 Module Identification Register F000 0908H U SV nBE 0028 C0XXH MSC1_FDR MSC1 Fractional Divider Register F000 090CH ...

Page 1007: ...ter 0 F000 0930H U SV U SV 0000 0000H MSC1_UD1 MSC1 Upstream Data Register 1 F000 0934H U SV U SV 0000 0000H MSC1_UD2 MSC1 Upstream Data Register 2 F000 0938H U SV U SV 0000 0000H MSC1_UD3 MSC1 Upstream Data Register 3 F000 093CH U SV U SV 0000 0000H MSC1_ICR MSC1 Interrupt Control Register F000 0940H U SV U SV 0000 0000H MSC1_ISR MSC1 Interrupt Status Register F000 0944H U SV U SV 0000 0000H MSC1...

Page 1008: ...Regs V2 0 MSC1_ SRC1 MSC1 Service Request Control Register 1 F000 09F8H U SV U SV 0000 0000H MSC1_ SRC0 MSC1 Service Request Control Register 0 F000 09FCH U SV U SV 0000 0000H Table 18 7 Address Map of MSC0 MSC1 cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1009: ... 0A14H U SV U SV 0000 0000H ASC0_FDV ASC0 Fractional Divider Register F000 0A18H U SV U SV 0000 0000H Reserved F000 0A1CH BE BE ASC0_ TBUF ASC0 Transmit Buffer Register F000 0A20H U SV U SV 0000 0000H ASC0_ RBUF ASC0 Receive Buffer Register F000 0A24H U SV U SV 0000 0000H Reserved F0000A28H F000 0A4CH BE BE ASC0_ WHBCON ASC0 Write Hardware Bits Control Register F000 0A50H U SV U SV 0000 0000H Rese...

Page 1010: ... ASC1_ TBUF ASC1 Transmit Buffer Register F000 0B20H U SV U SV 0000 0000H ASC1_ RBUF ASC1 Receive Buffer Register F000 0B24H U SV U SV 0000 0000H Reserved F0000B28H F000 0B4CH BE BE ASC1_ WHBCON ASC1 Write Hardware Bits Control Register F000 0B50H U SV U SV 0000 0000H Reserved F0000B54H F000 0BECH BE BE ASC1_ TSRC ASC1 Transmit Interrupt Service Req Control Reg F000 0BF0H U SV U SV 0000 0000H ASC1...

Page 1011: ... SV U SV P0_IOCR0 Port 0 Input Output Control Register 0 F000 0C10H U SV U SV 2020 2020H P0_IOCR4 Port 0 Input Output Control Register 4 F000 0C14H U SV U SV 2020 2020H P0_IOCR8 Port 0 Input Output Control Register 8 F000 0C18H U SV U SV 2020 2020H P0_IOCR12 Port 0 Input Output Control Register 12 F000 0C1CH U SV U SV 2020 2020H Reserved F000 0C20H U SV U SV P0_IN Port 0 Input Register F000 0C24H ...

Page 1012: ... SV U SV P1_IOCR0 Port 1 Input Output Control Register 0 F000 0D10H U SV U SV 2020 2020H P1_IOCR4 Port 1 Input Output Control Register 4 F000 0D14H U SV U SV 2020 2020H P1_IOCR8 Port 1 Input Output Control Register 8 F000 0D18H U SV U SV 2020 2020H P1_IOCR12 Port 1 Input Output Control Register 12 F000 0D1CH U SV U SV 2020 2020H Reserved F000 0D20H U SV U SV P1_IN Port 1 Input Register F000 0D24H ...

Page 1013: ... F000 0E10H U SV U SV 2020 2020H P2_IOCR4 Port 2 Input Output Control Register 4 F000 0E14H U SV U SV 2020 2020H P2_IOCR8 Port 2 Input Output Control Register 8 F000 0E18H U SV U SV 2020 2020H P2_IOCR12 Port 2 Input Output Control Register 12 F000 0E1CH U SV U SV 2020 2020H Reserved F000 0E20H U SV U SV P2_IN Port 2 Input Register F000 0E24H U SV U SV 0000 XXXXH Reserved F000 0E28H F000 0E3CH U SV...

Page 1014: ... F000 0F10H U SV U SV 2020 2020H P3_IOCR4 Port 3 Input Output Control Register 4 F000 0F14H U SV U SV 2020 2020H P3_IOCR8 Port 3 Input Output Control Register 8 F000 0F18H U SV U SV 2020 2020H P3_IOCR12 Port 3 Input Output Control Register 12 F000 0F1CH U SV U SV 2020 2020H Reserved F000 0F20H U SV U SV P3_IN Port 3 Input Register F000 0F24H U SV U SV 0000 XXXXH Reserved F000 0F28H F000 0F3CH U SV...

Page 1015: ... F000 1010H U SV U SV 2020 2020H P4_IOCR4 Port 4 Input Output Control Register 4 F000 1014H U SV U SV 2020 2020H P4_IOCR8 Port 4 Input Output Control Register 8 F000 1018H U SV U SV 2020 2020H P4_IOCR12 Port 4 Input Output Control Register 12 F000 101CH U SV U SV 2020 2020H Reserved F000 1020H U SV U SV P4_IN Port 4 Input Register F000 1024H U SV U SV 0000 XXXXH Reserved F000 1028H F000 103CH U SV...

Page 1016: ...egister F000 1104H U SV U SV 32 0000 00XXH Reserved F000 1108H F000 110CH U SV U SV P5_IOCR0 Port 5 Input Output Control Register 0 F000 1110H U SV U SV 2020 2020H P5_IOCR4 Port 5 Input Output Control Register 4 F000 1114H U SV U SV 2020 2020H Reserved F000 1118H F000 1120H U SV U SV P5_IN Port 5 Input Register F000 1124H U SV U SV 0000 00XXH Reserved F000 1128H F000 113CH U SV U SV P5_PDR Port 5 ...

Page 1017: ...0 XXXXH Reserved F000 1208H F000 1210H U SV U SV P6_IOCR4 Port 6 Input Output Control Register 4 F000 1214H U SV U SV 2020 2020H P6_IOCR8 Port 6 Input Output Control Register 8 F000 1218H U SV U SV 2020 2020H P6_IOCR12 Port 6 Input Output Control Register 12 F000 121CH U SV U SV 2020 2020H Reserved F000 1220H U SV U SV P6_IN Port 6 Input Register F000 1224H U SV U SV 0000 XXXXH Reserved F000 1228H...

Page 1018: ...egister F000 1304H U SV U SV 32 0000 00XXH Reserved F000 1308H F000 130CH U SV U SV P7_IOCR0 Port 7 Input Output Control Register 0 F000 1310H U SV U SV 2020 2020H P7_IOCR4 Port 7 Input Output Control Register 4 F000 1314H U SV U SV 2020 2020H Reserved F000 1318H F000 1320H U SV U SV P7_IN Port 7 Input Register F000 1324H U SV U SV 0000 00XXH Reserved F000 1328H F000 133CH U SV U SV P7_PDR Port 7 ...

Page 1019: ...00 1408H F000 140CH U SV U SV P8_IOCR0 Port 8 Input Output Control Register 0 F000 1410H U SV U SV 2020 2020H P8_IOCR4 Port 8 Input Output Control Register 4 F000 1414H U SV U SV 2020 2020H Reserved F0001418H F000 1420H U SV U SV P8_IN Port 8 Input Register F000 1424H U SV U SV 0000 00XXH Reserved F0001428H F000 143CH U SV U SV P8_PDR Port 8 Pad Driver Mode Register F000 1440H U SV SV E 0000 0000H...

Page 1020: ...rt 9 Input Output Control Register 0 F000 1510H U SV U SV 2020 2020H P9_IOCR4 Port 9 Input Output Control Register 4 F000 1514H U SV U SV 2020 2020H P9_IOCR8 Port 9 Input Output Control Register 8 F000 1518H U SV U SV 0000 0020H Reserved F000 151CH F000 1520H U SV U SV P9_IN Port 9 Input Register F000 1524H U SV U SV 0000 0XXXH Reserved F000 1528H F000 153CH U SV U SV P9_PDR Port 9 Pad Driver Mode...

Page 1021: ... 0 2007 07 Regs V2 0 Table 18 19 Address Map of Port 10 Short Name Description Address Access Mode Reset Value Read Write Port 10 Reserved F000 1600H F000 1620H U SV U SV P10_IN Port 10 Input Register F000 1624H U SV U SV 0000 000XH Reserved F000 1628H F000 16FCH U SV U SV ...

Page 1022: ...GPTA0 Service Request State Set Register 0 F000 1814H U SV U SV 0000 0000H GPTA0_ SRSC1 GPTA0 Service Request State Clear Register 1 F000 1818H U SV U SV 0000 0000H GPTA0_ SRSS1 GPTA0 Service Request State Set Register 1 F000 181CH U SV U SV 0000 0000H GPTA0_ SRSC2 GPTA0 Service Request State Clear Register 2 F000 1820H U SV U SV 0000 0000H GPTA0_ SRSS2 GPTA0 Service Request State Set Register 2 F...

Page 1023: ...l Timer Register 0 F000 184CH U SV U SV 0000 0000H GPTA0_ FPCCTR1 GPTA0 Filter and Prescaler Cell Control Register 1 F000 1850H U SV U SV 0000 0000H GPTA0_ FPCTIM1 GPTA0 Filter and Prescaler Cell Timer Register 1 F000 1854H U SV U SV 0000 0000H GPTA0_ FPCCTR2 GPTA0 Filter and Prescaler Cell Control Register 2 F000 1858H U SV U SV 0000 0000H GPTA0_ FPCTIM2 GPTA0 Filter and Prescaler Cell Timer Regi...

Page 1024: ...er F000 1878H U SV U SV 0000 0000H Reserved F000 187CH nBE nBE GPTA0_ DCMCTR0 GPTA0 Duty Cycle Measurement Control Register 0 F000 1880H U SV U SV 0000 0000H GPTA0_ DCMTIM0 GPTA0 Duty Cycle Measurement Timer Register 0 F000 1884H U SV U SV 0000 0000H GPTA0_ DCMCAV0 GPTA0 Duty Cycle Measurement Capture Register 0 F000 1888H U SV U SV 0000 0000H GPTA0_ DCMCOV0 GPTA0 Duty Cycle Measurement Capture Co...

Page 1025: ...H GPTA0_ DCMCOV2 GPTA0 Duty Cycle Measurement Capture Compare Register 2 F000 18ACH U SV U SV 0000 0000H GPTA0_ DCMCTR3 GPTA0 Duty Cycle Measurement Control Register 3 F000 18B0H U SV U SV 0000 0000H GPTA0_ DCMTIM3 GPTA0 Duty Cycle Measurement Timer Register 3 F000 18B4H U SV U SV 0000 0000H GPTA0_ DCMCAV3 GPTA0 Duty Cycle Measurement Capture Register 3 F000 18B8H U SV U SV 0000 0000H GPTA0_ DCMCO...

Page 1026: ...U SV U SV 0000 0000H GPTA0_ GTREV0 GPTA0 Global Timer Reload Value Register 0 F000 18E4H U SV U SV 0000 0000H GPTA0_ GTTIM0 GPTA0 Global Timer Register 0 F000 18E8H U SV U SV 0000 0000H Reserved F000 18ECH nBE nBE GPTA0_ GTCTR1 GPTA0 Global Timer Control Register 1 F000 18F0H U SV U SV 0000 0000H GPTA0_ GTREV1 GPTA0 Global Timer Reload Value Register 1 F000 18F4H U SV U SV 0000 0000H GPTA0_ GTTIM1...

Page 1027: ...4H U SV U SV 0000 0000H GPTA0_ MMXCTR10 GPTA to MSC Multiplexer Control Register 10 F000 1F08H U SV U SV 0000 0000H GPTA0_ MMXCTR11 GPTA to MSC Multiplexer Control Register 11 F000 1F0CH U SV U SV 0000 0000H Reserved F000 1F10H F000 1F64H nBE nBE GPTA0_ SRC37 GPTA0 Service Request Control Register 37 F000 1F68H U SV U SV 0000 0000H GPTA0_ SRC36 GPTA0 Service Request Control Register 36 F000 1F6CH ...

Page 1028: ... 0000H GPTA0_ SRC25 GPTA0 Service Request Control Register 25 F000 1F98H U SV U SV 0000 0000H GPTA0_ SRC24 GPTA0 Service Request Control Register 24 F000 1F9CH U SV U SV 0000 0000H GPTA0_ SRC23 GPTA0 Service Request Control Register 23 F000 1FA0H U SV U SV 0000 0000H GPTA0_ SRC22 GPTA0 Service Request Control Register 22 F000 1FA4H U SV U SV 0000 0000H GPTA0_ SRC21 GPTA0 Service Request Control Re...

Page 1029: ...ontrol Register 10 F000 1FD4H U SV U SV 0000 0000H GPTA0_ SRC09 GPTA0 Service Request Control Register 09 F000 1FD8H U SV U SV 0000 0000H GPTA0_ SRC08 GPTA0 Service Request Control Register 08 F000 1FDCH U SV U SV 0000 0000H GPTA0_ SRC07 GPTA0 Service Request Control Register 07 F000 1FE0H U SV U SV 0000 0000H GPTA0_ SRC06 GPTA0 Service Request Control Register 06 F000 1FE4H U SV U SV 0000 0000H G...

Page 1030: ...s V2 0 GPTA0_ SRC01 GPTA0 Service Request Control Register 01 F000 1FF8H U SV U SV 0000 0000H GPTA0_ SRC00 GPTA0 Service Request Control Register 00 F000 1FFCH U SV U SV 0000 0000H Table 18 20 Address Map of GPTA0 cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1031: ...1 F000 2018H U SV U SV 0000 0000H GPTA1_ SRSS1 GPTA1 Service Request State Set Register 1 F000 201CH U SV U SV 0000 0000H GPTA1_ SRSC2 GPTA1 Service Request State Clear Register 2 F000 2020H U SV U SV 0000 0000H GPTA1_ SRSS2 GPTA1 Service Request State Set Register 2 F000 2024H U SV U SV 0000 0000H GPTA1_ SRSC3 GPTA1 Service Request State Clear Register 3 F000 2028H U SV U SV 0000 0000H GPTA1_ SRS...

Page 1032: ...ntrol Register 1 F000 2050H U SV U SV 0000 0000H GPTA1_ FPCTIM1 GPTA1 Filter and Prescaler Cell Timer Register 1 F000 2054H U SV U SV 0000 0000H GPTA1_ FPCCTR2 GPTA1 Filter and Prescaler Cell Control Register 2 F000 2058H U SV U SV 0000 0000H GPTA1_ FPCTIM2 GPTA1 Filter and Prescaler Cell Timer Register 2 F000 205CH U SV U SV 0000 0000H GPTA1_ FPCCTR3 GPTA1 Filter and Prescaler Cell Control Regist...

Page 1033: ...easurement Control Register 0 F000 2080H U SV U SV 0000 0000H GPTA1_ DCMTIM0 GPTA1 Duty Cycle Measurement Timer Register 0 F000 2084H U SV U SV 0000 0000H GPTA1_ DCMCAV0 GPTA1 Duty Cycle Measurement Capture Register 0 F000 2088H U SV U SV 0000 0000H GPTA1_ DCMCOV0 GPTA1 Duty Cycle Measurement Capture Compare Register 0 F000 208CH U SV U SV 0000 0000H GPTA1_ DCMCTR1 GPTA1 Duty Cycle Measurement Con...

Page 1034: ...cle Measurement Control Register 3 F000 20B0H U SV U SV 0000 0000H GPTA1_ DCMTIM3 GPTA1 Duty Cycle Measurement Timer Register 3 F000 20B4H U SV U SV 0000 0000H GPTA1_ DCMCAV3 GPTA1 Duty Cycle Measurement Capture Register 3 F000 20B8H U SV U SV 0000 0000H GPTA1_ DCMCOV3 GPTA1 Duty Cycle Measurement Capture Compare Register 3 F000 20BCH U SV U SV 0000 0000H GPTA1_ PLLCTR GPTA1 Phase Locked Loop Cont...

Page 1035: ...erved F000 20ECH nBE nBE GPTA1_ GTCTR1 GPTA1 Global Timer Control Register 1 F000 20F0H U SV U SV 0000 0000H GPTA1_ GTREV1 GPTA1 Global Timer Reload Value Register 1 F000 20F4H U SV U SV 0000 0000H GPTA1_ GTTIM1 GPTA1 Global Timer Register 1 F000 20F8H U SV U SV 0000 0000H Reserved F000 20FCH nBE nBE GPTA1_ GTCCTRn GPTA1 Global Timer Cell Control Register n n 00 31 F000 2100H n 08H 00H U SV U SV 0...

Page 1036: ...1 Service Request Control Register 31 F000 2780H U SV U SV 0000 0000H GPTA1_ SRC30 GPTA1 Service Request Control Register 30 F000 2784H U SV U SV 0000 0000H GPTA1_ SRC29 GPTA1 Service Request Control Register 29 F000 2788H U SV U SV 0000 0000H GPTA1_ SRC28 GPTA1 Service Request Control Register 28 F000 278CH U SV U SV 0000 0000H GPTA1_ SRC27 GPTA1 Service Request Control Register 27 F000 2790H U S...

Page 1037: ... 0000H GPTA1_ SRC15 GPTA1 Service Request Control Register 15 F000 27C0H U SV U SV 0000 0000H GPTA1_ SRC14 GPTA1 Service Request Control Register 14 F000 27C4H U SV U SV 0000 0000H GPTA1_ SRC13 GPTA1 Service Request Control Register 13 F000 27C8H U SV U SV 0000 0000H GPTA1_ SRC12 GPTA1 Service Request Control Register 12 F000 27CCH U SV U SV 0000 0000H GPTA1_ SRC11 GPTA1 Service Request Control Re...

Page 1038: ...ontrol Register 04 F000 27ECH U SV U SV 0000 0000H GPTA1_ SRC03 GPTA1 Service Request Control Register 03 F000 27F0H U SV U SV 0000 0000H GPTA1_ SRC02 GPTA1 Service Request Control Register 02 F000 27F4H U SV U SV 0000 0000H GPTA1_ SRC01 GPTA1 Service Request Control Register 01 F000 27F8H U SV U SV 0000 0000H GPTA1_ SRC00 GPTA1 Service Request Control Register 00 F000 27FCH U SV U SV 0000 0000H T...

Page 1039: ...e Set Register 2 F000 2824H U SV U SV 0000 0000H LTCA2_ SRSC3 LTCA2 Service Request State Clear Register 3 F000 2828H U SV U SV 0000 0000H LTCA2_ SRSS3 LTCA2 Service Request State Set Register 3 F000 282CH U SV U SV 0000 0000H Reserved F000 2830H F000 2834H nBE nBE 0000 0000H LTCA2_ MRACTL LTCA2 Multiplexer Register Array Control Register F000 2838H U SV U SV 0000 0000H LTCA2_ MRADIN LTCA2 Multipl...

Page 1040: ...ister 15 F000 2FC0H U SV U SV 0000 0000H LTCA2_ SRC14 LTCA2 Service Request Control Register 14 F000 2FC4H U SV U SV 0000 0000H LTCA2_ SRC13 LTCA2 Service Request Control Register 13 F000 2FC8H U SV U SV 0000 0000H LTCA2_ SRC12 LTCA2 Service Request Control Register 12 F000 2FCCH U SV U SV 0000 0000H LTCA2_ SRC11 LTCA2 Service Request Control Register 11 F000 2FD0H U SV U SV 0000 0000H LTCA2_ SRC1...

Page 1041: ... 0000H LTCA2_ SRC04 LTCA2 Service Request Control Register 04 F000 2FECH U SV U SV 0000 0000H LTCA2_ SRC03 LTCA2 Service Request Control Register 03 F000 2FF0H U SV U SV 0000 0000H LTCA2_ SRC02 LTCA2 Service Request Control Register 02 F000 2FF4H U SV U SV 0000 0000H LTCA2_ SRC01 LTCA2 Service Request Control Register 01 F000 2FF8H U SV U SV 0000 0000H LTCA2_ SRC00 LTCA2 Service Request Control Re...

Page 1042: ...14H U SV BE 0000 0000H DMA_ STREQ DMA Software Transaction Request Register F000 3C18H U SV SV 0000 0000H DMA_ HTREQ DMA Hardware Transaction Request Register F000 3C1CH U SV SV 0000 0000H DMA_ EER DMA Enable Error Register F000 3C20H U SV SV 0000 0000H DMA_ ERRSR DMA Error Status Register F000 3C24H U SV BE 0000 0000H DMA_ CLRE DMA Clear Error Register F000 3C28H U SV SV 0000 0000H DMA_ GINTR DMA...

Page 1043: ... Clear Register F000 3C58H U SV SV 0000 0000H DMA_ WRPSR DMA Wrap Status Register F000 3C5CH U SV BE 0000 0000H Reserved F000 3C60H BE BE DMA_ OCDSR DMA OCDS Register F000 3C64H U SV SV E 0000 0000H DMA_ SUSPMR DMA Suspend Mode Register F000 3C68H U SV SV E 0000 0000H Reserved F000 3C6CH F000 3C7CH BE BE DMA_ CHSR00 DMA Channel 00 Status Register F000 3C80H U SV BE 0000 0000H DMA_ CHCR00 DMA Chann...

Page 1044: ...V 0000 0000H DMA_ SADR01 DMA Channel 01 Source Address Register F000 3CB0H U SV SV 0000 0000H DMA_ DADR01 DMA Channel 01 Destination Address Reg F000 3CB4H U SV SV 0000 0000H DMA_ SHADR01 DMA Channel 01 Shadow Address Register F000 3CB8H U SV BE 0000 0000H Reserved F000 3CBCH BE BE DMA_ CHSR02 DMA Channel 02 Status Register F000 3CC0H U SV BE 0000 0000H DMA_ CHCR02 DMA Channel 02 Control Register ...

Page 1045: ...SV 0000 0000H DMA_ SADR03 DMA Channel 03 Source Address Register F000 3CF0H U SV SV 0000 0000H DMA_ DADR03 DMA Channel 03 Destination Address Reg F000 3CF4H U SV SV 0000 0000H DMA_ SHADR03 DMA Channel 03 Shadow Address Register F000 3CF8H U SV BE 0000 0000H Reserved F000 3CFCH BE BE DMA_ CHSR04 DMA Channel 04 Status Register F000 3D00H U SV BE 0000 0000H DMA_ CHCR04 DMA Channel 04 Control Register...

Page 1046: ...SV 0000 0000H DMA_ SADR05 DMA Channel 05 Source Address Register F000 3D30H U SV SV 0000 0000H DMA_ DADR05 DMA Channel 05 Destination Address Reg F000 3D34H U SV SV 0000 0000H DMA_ SHADR05 DMA Channel 05 Shadow Address Register F000 3D38H U SV BE 0000 0000H Reserved F000 3D3CH BE BE DMA_ CHSR06 DMA Channel 06 Status Register F000 3D40H U SV BE 0000 0000H DMA_ CHCR06 DMA Channel 06 Control Register...

Page 1047: ...SV 0000 0000H DMA_ SADR07 DMA Channel 07 Source Address Register F000 3D70H U SV SV 0000 0000H DMA_ DADR07 DMA Channel 07 Destination Address Reg F000 3D74H U SV SV 0000 0000H DMA_ SHADR07 DMA Channel 07 Shadow Address Register F000 3D78H U SV BE 0000 0000H Reserved F000 3D7CH BE BE DMA_ CHSR10 DMA Channel 10 Status Register F000 3D80H U SV BE 0000 0000H DMA_ CHCR10 DMA Channel 10 Control Register...

Page 1048: ...V 0000 0000H DMA_ SADR11 DMA Channel 11 Source Address Register F000 3DB0H U SV SV 0000 0000H DMA_ DADR11 DMA Channel 11 Destination Address Reg F000 3DB4H U SV SV 0000 0000H DMA_ SHADR11 DMA Channel 11 Shadow Address Register F000 3DB8H U SV BE 0000 0000H Reserved F000 3DBCH BE BE DMA_ CHSR12 DMA Channel 12 Status Register F000 3DC0H U SV BE 0000 0000H DMA_ CHCR12 DMA Channel 12 Control Register ...

Page 1049: ...SV 0000 0000H DMA_ SADR13 DMA Channel 13 Source Address Register F000 3DF0H U SV SV 0000 0000H DMA_ DADR13 DMA Channel 13 Destination Address Reg F000 3DF4H U SV SV 0000 0000H DMA_ SHADR13 DMA Channel 13 Shadow Address Register F000 3DF8H U SV BE 0000 0000H Reserved F000 3DFCH BE BE DMA_ CHSR14 DMA Channel 14 Status Register F000 3E00H U SV BE 0000 0000H DMA_ CHCR14 DMA Channel 14 Control Register...

Page 1050: ...SV 0000 0000H DMA_ SADR15 DMA Channel 15 Source Address Register F000 3E30H U SV SV 0000 0000H DMA_ DADR15 DMA Channel 15 Destination Address Reg F000 3E34H U SV SV 0000 0000H DMA_ SHADR15 DMA Channel 15 Shadow Address Register F000 3E38H U SV BE 0000 0000H Reserved F000 3E3CH BE BE DMA_ CHSR16 DMA Channel 16 Status Register F000 3E40H U SV BE 0000 0000H DMA_ CHCR16 DMA Channel 16 Control Register...

Page 1051: ...17 Address Control Register F000 3E6CH U SV SV 0000 0000H DMA_ SADR17 DMA Channel 17 Source Address Register F000 3E70H U SV SV 0000 0000H DMA_ DADR17 DMA Channel 17 Destination Address Reg F000 3E74H U SV SV 0000 0000H DMA_ SHADR17 DMA Channel 17 Shadow Address Register F000 3E78H U SV BE 0000 0000H Reserved F000 3E7CH F000 3E88H BE BE DMA_ SYSSRC4 DMA System Interrupt Service Request Control Reg...

Page 1052: ...0H Reserved F000 3EB0H F000 3EB4H BE BE DMA_ MLI1SRC1 DMA MLI1 Service Request Control Reg 1 F000 3EB8H U SV SV 0000 0000H DMA_ MLI1SRC0 DMA MLI1 Service Request Control Reg 0 F000 3EBCH U SV SV 0000 0000H Reserved F000 3EC0H F000 3EDCH BE BE DMA_ SRC7 DMA Service Request Control Register 7 F000 3EE0H U SV SV 0000 0000H DMA_ SRC6 DMA Service Request Control Register 6 F000 3EE4H U SV SV 0000 0000H...

Page 1053: ...07 07 Regs V2 0 DMA_ SRC1 DMA Service Request Control Register 1 F000 3EF8H U SV SV 0000 0000H DMA_ SRC0 DMA Service Request Control Register 0 F000 3EFCH U SV SV 0000 0000H Table 18 23 Address Map of DMA cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1054: ...ce Request Control Register 14 F000 40C4H U SV U SV 0000 0000H CAN_ SRC13 CAN Service Request Control Register 13 F000 40C8H U SV U SV 0000 0000H CAN_ SRC12 CAN Service Request Control Register 12 F000 40CCH U SV U SV 0000 0000H CAN_ SRC11 CAN Service Request Control Register 11 F000 40D0H U SV U SV 0000 0000H CAN_ SRC10 CAN Service Request Control Register 10 F000 40D4H U SV U SV 0000 0000H CAN_ ...

Page 1055: ... 007F 7F00H CAN_ LIST1 CAN List Register 1 F000 4104H U SV U SV 0100 0000H CAN_ LIST2 CAN List Register 2 F000 4108H U SV U SV 0100 0000H CAN_ LIST3 CAN List Register 3 F000 410CH U SV U SV 0100 0000H CAN_ LIST4 CAN List Register 4 F000 4110H U SV U SV 0100 0000H CAN_ LIST5 CAN List Register 5 F000 4114H U SV U SV 0100 0000H CAN_ LIST6 CAN List Register 6 F000 4118H U SV U SV 0100 0000H CAN_ LIST7...

Page 1056: ...x Register 1 F000 4144H U SV U SV 0000 0020H CAN_ MSID2 CAN Message Index Register 2 F000 4148H U SV U SV 0000 0020H CAN_ MSID3 CAN Message Index Register 3 F000 414CH U SV U SV 0000 0020H CAN_ MSID4 CAN Message Index Register 4 F000 4150H U SV U SV 0000 0020H CAN_ MSID5 CAN Message Index Register 5 F000 4154H U SV U SV 0000 0020H CAN_ MSID6 CAN Message Index Register 6 F000 4158H U SV U SV 0000 0...

Page 1057: ... Port Control Register F000 420CH U SV U SV 0000 0000H CAN_ NBTR0 CAN Node 0 Bit Timing Register F000 4210H U SV U SV 0000 0000H CAN_ NECNT0 CAN Node 0 Error Counter Register F000 4214H U SV U SV 0060 0000H CAN_ NFCR0 CAN Node 0 Frame Counter Register F000 4218H U SV U SV 0000 0000H Reserved F000 421CH F000 427CH nBE nBE CAN Node 0 TTCAN Registers CAN_ LTR CAN Local Time Register F000 4280H U SV U...

Page 1058: ...ontrol Register F000 42C0H U SV U SV 0000 0000H CAN_ TTCFGR CAN Time Trigger Configuration Register F000 42C4H U SV U SV 0000 0000H CAN_ TTSR CAN Time Trigger Status Register F000 42C8H U SV U SV 0000 1000H CAN_ TTFMR CAN Time Trigger Flag Modification Register F000 42CCH U SV U SV 0000 0000H CAN_ TTIRR CAN Time Trigger Interrupt Request Register F000 42D0H U SV U SV 0000 0000H CAN_ TTIER CAN Time...

Page 1059: ...00 0000H CAN_ NBTR1 CAN Node 1 Bit Timing Register F000 4310H U SV U SV 0000 0000H CAN_ NECNT1 CAN Node 1 Error Counter Register F000 4314H U SV U SV 0060 0000H CAN_ NFCR1 CAN Node 1 Frame Counter Register F000 4318H U SV U SV 0000 0000H Reserved F000 431CH F000 43FCH nBE nBE CAN Node 2 Registers CAN_ NCR2 CAN Node 2 Control Register F000 4400H U SV U SV 0000 0001H CAN_ NSR2 CAN Node 2 Status Regi...

Page 1060: ...3 CAN Node 3 Port Control Register F000 450CH U SV U SV 0000 0000H CAN_ NBTR3 CAN Node 3 Bit Timing Register F000 4510H U SV U SV 0000 0000H CAN_ NECNT3 CAN Node 3 Error Counter Register F000 4514H U SV U SV 0060 0000H CAN_ NFCR3 CAN Node 3 Frame Counter Register F000 4518H U SV U SV 0000 0000H Reserved F000 451CH F000 45FCH nBE nBE CAN Message Object 0 CAN_ MOFCR0 CAN Message Object 0 Function Co...

Page 1061: ...ister Write U SV CAN Message Object 1 CAN_ MOFCR1 CAN Message Object 1 Function Control Register F000 4620H U SV U SV 0000 0000H CAN_ MOFGPR1 CAN Message Object 1 FIFO Gateway Pointer Register F000 4624H U SV U SV 0000 0000H CAN_ MOIPR1 CAN Message Object 1 Interrupt Pointer Register F000 4628H U SV U SV 0000 0000H CAN_ MOAMR1 CAN Message Object 1 Acceptance Mask Register F000 462CH U SV U SV 3FFF...

Page 1062: ...sk Register F000 464CH U SV U SV 3FFF FFFFH CAN_ MODATAL2 CAN Message Object 2 Data Register Low F000 4650H U SV U SV 0000 0000H CAN_ MODATAH2 CAN Message Object 2 Data Register High F000 4654H U SV U SV 0000 0000H CAN_ MOAR2 CAN Message Object 2 Arbitration Register F000 4658H U SV U SV 0000 0000H CAN_ MOSTAT2 CAN Message Object 2 Status Register Read F000 465CH U SV 0301 0000H CAN_ MOCTR2 CAN Me...

Page 1063: ... 0000 0000H CAN_ MOSTATn CAN Message Object n Status Register Read F000 4600H n 20H 1CH U SV n 1 24 n 1 16 CAN_ MOCTRn CAN Message Object n Control Register Write U SV CAN Message Object 126 CAN_ MOFCR126 CAN Message Object 126 Function Control Register F000 55C0H U SV U SV 0000 0000H CAN_ MOFGPR 126 CAN Message Object 126 FIFO Gateway Pointer Register F000 55C4H U SV U SV 0000 0000H CAN_ MOIPR126...

Page 1064: ...egister F000 55E0H U SV U SV 0000 0000H CAN_ MOFGPR 127 CAN Message Object 127 FIFO Gateway Pointer Register F000 55E4H U SV U SV 0000 0000H CAN_ MOIPR127 CAN Message Object 127 Interrupt Pointer Register F000 55E8H U SV U SV 0000 0000H CAN_ MOAMR127 CAN Message Object 127 Acceptance Mask Register F000 55ECH U SV U SV 3FFF FFFFH CAN_ MOAR127 CAN Message Object 127 Arbitration Register F000 55F0H U...

Page 1065: ...N_ MOCTR127 CAN Message Object 127 Control Register Write U SV TTCAN Scheduler Memory TTCAN Scheduler Memory F000 5600H F000 57F8H U SV U SV 0000 0000H CAN_ STPTR0 CAN Scheduler Start Pointer Node 0 Register F000 57FCH U SV U SV 0000 0000H Reserved F000 5800H F000 5FFCH nBE nBE Table 18 24 Address Map of CAN cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1066: ...043F18H F004 3F1CH BE BE PCP_ICR PCP Interrupt Control Register F004 3F20H U SV 32 SV 32 0000 0000H PCP_ITR PCP Interrupt Threshold Control Register F004 3F24H U SV 32 SV 32 0000 0000H PCP_ICON PCP Interrupt Configuration Register F004 3F28H U SV 32 BE 0000 03E4H PCP_SSR PCP Stall Status Register F004 3F2CH U SV 32 SV 32 0000 0000H Reserved this location must not be written F004 3F30H U SV 32 SV 3...

Page 1067: ...0000 1000H PCP_SRC4 PCP Service Request Control Register 4 F004 3FECH U SV 32 SV 32 0000 1000H PCP_SRC3 PCP Service Request Control Register 3 F004 3FF0H U SV 32 SV 32 0000 1400H PCP_SRC2 PCP Service Request Control Register 2 F004 3FF4H U SV 32 SV 32 0000 1400H PCP_SRC1 PCP Service Request Control Register 1 F004 3FF8H U SV 32 SV 32 0000 1000H PCP_SRC0 PCP Service Request Control Register 0 F004 ...

Page 1068: ... SV SV 0000 0000H RBCU_ EADD RBCU Error Address Capture Register F010 0024H U SV SV 0000 0000H RBCU_ EDAT RBCU Error Data Capture Register F010 0028H U SV SV 0000 0000H Reserved F010 002CH BE BE RBCU_ DBCNTL RBCU Debug Control Register F010 0030H U SV SV 0000 7003H RBCU_ DBGRNT RBCU Debug Grant Mask Register F010 0034H U SV SV 0000 FFFFH RBCU_ DBADR1 RBCU Debug Address 1 Register F010 0038H U SV S...

Page 1069: ...OST RBCU Debug Trapped Bus Operation Signals Register F010 004CH U SV BE 0000 3180H Reserved F010 0050H F010 00F8H BE BE RBCU_ SRC RBCU Service Request Control Register F010 00FCH U SV SV 0000 0000H Table 18 26 Address Map of RBCU cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1070: ... SSC0 Baud Rate Timer Reload Register F010 0114H U SV U SV 0000 0000H SSC0_ SSOC SSC0 Slave Select Output Control Register F010 0118H U SV U SV 0000 0000H SSC0_ SSOTC SSC0 Slave Select Output Timing Control Register F010 011CH U SV U SV 0000 0000H SSC0_TB SSC0 Transmit Buffer Register F010 0120H U SV U SV 0000 0000H SSC0_RB SSC0 Receive Buffer Register F010 0124H U SV U SV 0000 0000H SSC0_ STAT SS...

Page 1071: ...BE 0000 45XXH SSC1_FDR SSC1 Fractional Divider Register F010 020CH U SV SV E 0000 0000H SSC1_CON SSC1 Control Register F010 0210H U SV U SV 0000 0000H SSC1_BR SSC1 Baud Rate Timer Reload Register F010 0214H U SV U SV 0000 0000H SSC1_ SSOC SSC1 Slave Select Output Control Register F010 0218H U SV U SV 0000 0000H SSC1_ SSOTC SSC1 Slave Select Output Timing Control Register F010 021CH U SV U SV 0000 ...

Page 1072: ...mit Interrupt Service Req Control Reg F010 02F4H U SV SV 0000 0000H SSC1_ RSRC SSC1 Receive Interrupt Service Req Control Reg F010 02F8H U SV SV 0000 0000H SSC1_ ESRC SSC1 Error Interrupt Service Req Control Reg F010 02FCH U SV SV 0000 0000H Table 18 27 Address Map of SSC0 SSC1 cont d Short Name Description Address Access Mode Reset Value Read Write ...

Page 1073: ...0000 0000H FADC_ NCTR FADC Neighbor Channel Trigger Register F010 0318H U SV U SV 0000 0000H FADC_GCR FADC Global Control Register F010 031CH U SV U SV 0000 0000H FADC_ CFGR0 FADC Channel 0 Configuration Register F010 0320H U SV U SV 0000 0000H FADC_ CFGR1 FADC Channel 1 Configuration Register F010 0324H U SV U SV 0000 0000H FADC_ CFGR2 FADC Channel 2 Configuration Register F010 0328H U SV U SV 00...

Page 1074: ...ster F010 0364H U SV U SV 0000 0000H FADC_ IRR10 FADC Filter 0 Intermediate Result Register 1 F010 0368H U SV U SV 0000 0000H FADC_ IRR20 FADC Filter 0 Intermediate Result Register 2 F010 036CH U SV U SV 0000 0000H FADC_ IRR30 FADC Filter 0 Intermediate Result Register 3 F010 0370H U SV U SV 0000 0000H FADC_ FRR0 FADC Filter 0 Final Result Register F010 0374H U SV U SV 0000 0000H Reserved F010 037...

Page 1075: ...BE BE FADC_ SRC3 FADC Service Request Control Register 3 F010 03F0H U SV U SV 0000 0000H FADC_ SRC2 FADC Service Request Control Register 2 F010 03F4H U SV U SV 0000 0000H FADC_ SRC1 FADC Service Request Control Register 1 F010 03F8H U SV U SV 0000 0000H FADC_ SRC0 FADC Service Request Control Register 0 F010 03FCH U SV U SV 0000 0000H Table 18 28 Address Map of FADC cont d Short Name Description ...

Page 1076: ...0414H U SV U SV 0000 0000H ADC0_ CHCON2 ADC0 Channel Control Register 2 F010 0418H U SV U SV 0000 0000H ADC0_ CHCON3 ADC0 Channel Control Register 3 F010 041CH U SV U SV 0000 0000H ADC0_ CHCON4 ADC0 Channel Control Register 4 F010 0420H U SV U SV 0000 0000H ADC0_ CHCON5 ADC0 Channel Control Register 5 F010 0424H U SV U SV 0000 0000H ADC0_ CHCON6 ADC0 Channel Control Register 6 F010 0428H U SV U SV...

Page 1077: ...10 0488H U SV U SV 0103 4067H ADC0_TTC ADC0 Timer Trigger Control Register F010 048CH U SV U SV 0000 0000H ADC0_ EXTC ADC0 External Trigger Control Register F010 0490H U SV U SV 0000 0000H Reserved F010 0494H BE BE ADC0_ SCON ADC0 Source Control Register F010 0498H U SV U SV 0000 0000H Reserved F010 049CH BE BE Reserved these locations must not be written F010 04A0H F010 04DCH nBE nBE Reserved F01...

Page 1078: ...0000H Reserved F010 052CH BE BE ADC0_ CHSTAT0 ADC0 Channel Status Register 0 F010 0530H U SV U SV 0000 0000H ADC0_ CHSTAT1 ADC0 Channel Status Register 1 F010 0534H U SV U SV 0000 0000H ADC0_ CHSTAT2 ADC0 Channel Status Register 2 F010 0538H U SV U SV 0000 0000H ADC0_ CHSTAT3 ADC0 Channel Status Register 3 F010 053CH U SV U SV 0000 0000H ADC0_ CHSTAT4 ADC0 Channel Status Register 4 F010 0540H U SV...

Page 1079: ...SV 0000 0000H ADC0_ CHSTAT15 ADC0 Channel Status Register 15 F010 056CH U SV U SV 0000 0000H ADC0_ QUEUE0 ADC0 Queue Status Register F010 0570H U SV U SV 0000 0000H Reserved F010 0574H F010 057CH BE BE ADC0_ SW0CRP ADC0 Software SW0 Conversion Request Pending Register F010 0580H U SV U SV 0000 0000H Reserved F010 0584H BE BE ADC0_ ASCRP ADC0 Auto Scan Conversion Request Pending Register F010 0588H...

Page 1080: ... MSS0 ADC0 Module Service Request Status Register 0 F010 05D0H U SV U SV 0000 0000H ADC0_ MSS1 ADC0 Module Service Request Status Register 1 F010 05D4H U SV U SV 0000 0000H Reserved F010 05D8H BE BE ADC0_ SRNP ADC0 Service Request Node Pointer Register F010 05DCH U SV U SV 0000 0000H Reserved F010 05E0H F010 05ECH BE BE ADC0_ SRC3 ADC0 Service Request Control Register 3 F010 05F0H U SV U SV 0000 0...

Page 1081: ...0000H ADC1_ CHCON5 ADC1 Channel Control Register 5 F010 0624H U SV U SV 0000 0000H ADC1_ CHCON6 ADC1 Channel Control Register 6 F010 0628H U SV U SV 0000 0000H ADC1_ CHCON7 ADC1 Channel Control Register 7 F010 062CH U SV U SV 0000 0000H ADC1_ CHCON8 ADC1 Channel Control Register 8 F010 0630H U SV U SV 0000 0000H ADC1_ CHCON9 ADC1 Channel Control Register 9 F010 0634H U SV U SV 0000 0000H ADC1_ CHC...

Page 1082: ...U SV U SV 0000 0000H Reserved F010 0694H BE BE ADC1_ SCON ADC1 Source Control Register F010 0698H U SV U SV 0000 0000H Reserved F010 069CH BE BE Reserved these locations must not be written F010 06A0H F010 06DCH nBE nBE Reserved F010 06E0H F010 06FCH BE BE ADC1_ LCCON0 ADC1 Limit Check Control Register 0 F010 0700H U SV U SV 0000 0000H ADC1_ LCCON1 ADC1 Limit Check Control Register 1 F010 0704H U ...

Page 1083: ...SV U SV 0000 0000H ADC1_ CHSTAT2 ADC1 Channel Status Register 2 F010 0738H U SV U SV 0000 0000H ADC1_ CHSTAT3 ADC1 Channel Status Register 3 F010 073CH U SV U SV 0000 0000H ADC1_ CHSTAT4 ADC1 Channel Status Register 4 F010 0740H U SV U SV 0000 0000H ADC1_ CHSTAT5 ADC1 Channel Status Register 5 F010 0744H U SV U SV 0000 0000H ADC1_ CHSTAT6 ADC1 Channel Status Register 6 F010 0748H U SV U SV 0000 00...

Page 1084: ... F010 0770H U SV U SV 0000 0000H Reserved F010 0774H F010 077CH BE BE ADC1_ SW0CRP ADC1 Software SW0 Conversion Request Pending Register F010 0780H U SV U SV 0000 0000H Reserved F010 0784H BE BE ADC1_ ASCRP ADC1 Auto Scan Conversion Request Pending Register F010 0788H U SV U SV 0000 0000H Reserved F010 078CH BE BE ADC1_ SYSTAT ADC1 Synchronization Status Register F010 0790H U SV U SV 0000 0000H Re...

Page 1085: ...10 07D0H U SV U SV 0000 0000H ADC1_ MSS1 ADC1 Module Service Request Status Register 1 F010 07D4H U SV U SV 0000 0000H Reserved F010 07D8H BE BE ADC1_ SRNP ADC1 Service Request Node Pointer Register F010 07DCH U SV U SV 0000 0000H Reserved F010 07E0H F010 07ECH BE BE ADC1_ SRC3 ADC1 Service Request Control Register 3 F010 07F0H U SV U SV 0000 0000H ADC1_ SRC2 ADC1 Service Request Control Register ...

Page 1086: ...Register F010 C018H U SV BE 0000 0000H MLI0_ TP1STATR MLI0 Transmitter Pipe 1 Status Register F010 C01CH U SV BE 0000 0000H MLI0_ TP2STATR MLI0 Transmitter Pipe 2 Status Register F010 C020H U SV BE 0000 0000H MLI0_ TP3STATR MLI0 Transmitter Pipe 3 Status Register F010 C024H U SV BE 0000 0000H MLI0_ TCMDR MLI0 Transmitter Command Register F010 C028H U SV U SV 0000 0000H MLI0_ TRSTATR MLI0 Transmitt...

Page 1087: ...00 0000H MLI0_ TP2BAR MLI0 Transmitter Pipe 2 Base Address Register F010 C05CH U SV U SV 0000 0000H MLI0_ TP3BAR MLI0 Transmitter Pipe 3 Base Address Register F010 C060H U SV U SV 0000 0000H MLI0_ TCBAR MLI0 Transmitter Copy Base Address Register F010 C064H U SV BE 0000 0000H MLI0_ RCR MLI0 Receiver Control Register F010 C068H U SV U SV 0100 0000H MLI0_ RP0BAR MLI0 Receiver Pipe 0 Base Address Reg...

Page 1088: ...ansmitterInterrupt Status Register F010 C09CH U SV BE 0000 0000H MLI0_ TINPR MLI0TransmitterInterrupt Node Pointer Register F010 C0A0H U SV U SV 0000 0000H MLI0_RIER MLI0 Receiver Interrupt Enable Register F010 C0A4H U SV U SV 0000 0000H MLI0_RISR MLI0 Receiver Interrupt Status Register F010 C0A8H U SV BE 0000 0000H MLI0_ RINPR MLI0 Receiver Interrupt Node Pointer Register F010 C0ACH U SV U SV 000...

Page 1089: ...nsmitter Pipe 2 Status Register F010 C120H U SV BE 0000 0000H MLI1_ TP3STATR MLI1 Transmitter Pipe 3 Status Register F010 C124H U SV BE 0000 0000H MLI1_ TCMDR MLI1 Transmitter Command Register F010 C128H U SV U SV 0000 0000H MLI1_ TRSTATR MLI1 Transmitter Registers Status Register F010 C12CH U SV BE 0000 0000H MLI1_ TP0AOFR MLI1 Transmitter Pipe 0 Address Offset Register F010 C130H U SV BE 0000 00...

Page 1090: ...SV U SV 0000 0000H MLI1_ TP3BAR MLI1 Transmitter Pipe 3 Base Address Register F010 C160H U SV U SV 0000 0000H MLI1_ TCBAR MLI1 Transmitter Copy Base Address Register F010 C164H U SV BE 0000 0000H MLI1_RCR MLI1 Receiver Control Register F010 C168H U SV U SV 0100 0000H MLI1_ RP0BAR MLI1 Receiver Pipe 0 Base Address Register F010 C16CH U SV BE 0000 0000H MLI1_ RP1BAR MLI1 Receiver Pipe 1 Base Address...

Page 1091: ...C19CH U SV BE 0000 0000H MLI1_ TINPR MLI1TransmitterInterrupt Node Pointer Register F010 C1A0H U SV U SV 0000 0000H MLI1_RIER MLI1 Receiver Interrupt Enable Register F010 C1A4H U SV U SV 0000 0000H MLI1_RISR MLI1 Receiver Interrupt Status Register F010 C1A8H U SV BE 0000 0000H MLI1_ RINPR MLI1 Receiver Interrupt Node Pointer Register F010 C1ACH U SV U SV 0000 0000H MLI1_ GINTR MLI1 Global Interrup...

Page 1092: ...gister F010 C208H U SV BE 001B C0XXH Reserved F010 C20CH BE BE MCHK_IR Memory Checker Input Register F010 C210H U SV U SV 0000 0000H MCHK_RR Memory Checker Result Register F010 C214H U SV U SV 0000 0000H Reserved F010 C218H F010 C21CH BE BE MCHK_WR Memory Checker Write Register F010 C220H U SV U SV 0000 0000H Reserved F010 C224H F010 C2FCH BE BE 1 The reset values of the memory checker registers c...

Page 1093: ...F08H U SV U SV NC 0015 C0XXH Reserved F7E0 FF0CH FFFE FFB8H BE BE CPU_ SBSRC0 CPU Software Break Service Request Control Register 0 F7E0 FFBCH U SV SV 0000 0000H Reserved F7E0 FFC0H F7E0 FFECH BE BE CPU_SRC3 CPU Service Request Control Register 3 F7E0 FFF0H U SV SV 0000 0000H CPU_SRC2 CPU Service Request Control Register 2 F7E0 FFF4H U SV SV 0000 0000H CPU_SRC1 CPU Service Request Control Register...

Page 1094: ...r Boundary F7E1 C000H U SV 32 SV 32 0000 0000H DPR0_0U Data Seg Prot Reg Set 0 Range 0 Upper Boundary F7E1 C004H U SV 32 SV 32 0000 0000H DPR0_1L Data Seg Prot Reg Set 0 Range 1 Lower Boundary F7E1 C008H U SV 32 SV 32 0000 0000H DPR0_1U Data Seg Prot Reg Set 0 Range 1 Upper Boundary F7E1 C00CH U SV 32 SV 32 0000 0000H DPR0_2L Data Seg Prot Reg Set 0 Range 2 Lower Boundary F7E1 C010H U SV 32 SV 32 ...

Page 1095: ...PR1_2L Data Seg Prot Reg Set 1 Range 2 Lower Boundary F7E1 C410H U SV 32 SV 32 0000 0000H DPR1_2U Data Seg Prot Reg Set 1 Range 2 Upper Boundary F7E1 C414H U SV 32 SV 32 0000 0000H DPR1_3L Data Seg Prot Reg Set 1 Range 3 Lower Boundary F7E1 C418H U SV 32 SV 32 0000 0000H DPR1_3U Data Seg Prot Reg Set 1 Range 3 Upper Boundary F7E1 C41CH U SV 32 SV 32 0000 0000H Reserved F7E1 C420H F7E1 CFFCH nE nE ...

Page 1096: ...0000H CPR1_1L Code Seg Prot Reg Set 1 Rng 1 Lower Boundary F7E1 D408H U SV 32 SV 32 0000 0000H CPR1_1U Code Seg Prot Reg Set 1 Rng 1 Upper Boundary F7E1 D40CH U SV 32 SV 32 0000 0000H Reserved F7E1 D410H F7E1 DFFCH nE nE DPM0 Data Protection Mode Register Set 0 F7E1 E000H U SV 32 SV 32 0000 0000H Reserved F7E1 E004H F7E1 E07CH nE nE DPM1 Data Protection Mode Register Set 1 F7E1 E080H U SV 32 SV 32...

Page 1097: ...k Event Specifier Register F7E1 FD10H U SV 32 SV 32 0000 0000H Reserved F7E1 FD14H F7E1 FD1CH nE nE TR0EVT Trigger Event 0 Specifier Register F7E1 FD20H U SV 32 SV 32 0000 0000H TR1EVT Trigger Event 1 Specifier Register F7E1 FD24H U SV 32 SV 32 0000 0000H Reserved F7E1 FD28H F7E1 FD3CH nE nE DMS Debug Monitor Start Address Register F7E1 FD40H U SV 32 U SV 32 NC DE00 0000H DCX Debug Context Save Ar...

Page 1098: ...000H BTV Trap Vector Table Pointer F7E1 FE24H U SV 32 SV E 32 A000 0100H ISP Interrupt Stack Pointer F7E1 FE28H U SV 32 SV E 32 0000 0100H ICR ICU Interrupt Control Register F7E1 FE2CH U SV 32 SV 32 0000 0000H Reserved F7E1 FE30H F7E1 FE34H nE nE FCX Free Context List Head Pointer F7E1 FE38H U SV 32 SV 32 0000 0000H LCX Free Context List Limit Pointer F7E1 FE3CH U SV 32 SV 32 0000 0000H F7E1 FE40H...

Page 1099: ... D15 Data Register 15 F7E1 FF3CH XXXX XXXXH Reserved F7E1 FF40H F7E1 FF7CH nE nE A0 Address Register 0 Global Address Register F7E1 FF80H XXXX XXXXH A1 Address Register 1 Global Address Register F7E1 FF84H XXXX XXXXH A2 Address Register 2 F7E1 FF88H XXXX XXXXH A3 Address Register 3 F7E1 FF8CH XXXX XXXXH A4 Address Register 4 F7E1 FF90H XXXX XXXXH A5 Address Register 5 F7E1 FF94H XXXX XXXXH A6 Addr...

Page 1100: ...Register 13 F7E1 FFB4H XXXX XXXXH A14 Address Register 14 F7E1 FFB8H XXXX XXXXH A15 Address Register 15 F7E1 FFBCH XXXX XXXXH Reserved F7E1 FFC0H F7E1 FFFCH nE nE 1 Read write operations from to these locations have no effect 2 Note that all GPRs are undefined XXXX XXXXB after a reset operation Table 18 33 Address Map of CPU Core SFRs GPRs cont d Short Name Description Address Access Mode Reset Va...

Page 1101: ...3 Reserved F800 0014H F800 001CH BE BE EBU_ BFCON EBU Burst Flash Control Register F800 0020H U SV 32 SV 32 0010 01D0H Reserved F800 0024H F800 003CH BE BE Reserved do not read write to this location F800 0040H U SV 32 SV 32 Reserved F800 0044H BE BE Reserved do not read write to this location F800 0048H U SV 32 SV 32 Reserved F800 004CH BE BE Reserved do not read write to this location F800 0050H...

Page 1102: ...E BE EBU_ ADDRSEL2 EBU Address Select Register 2 F800 0090H U SV 32 SV 32 0000 0000H Reserved F800 0094H BE BE EBU_ ADDRSEL3 EBU Address Select Register 3 F800 0098H U SV 32 SV 32 0000 0000H Reserved F800 009CH BE BE Reserved do not read write to this location F800 00A0H U SV 32 SV 32 Reserved F800 00A4H BE BE Reserved do not read write to this location F800 00A8H U SV 32 SV 32 Reserved F800 00ACH...

Page 1103: ...do not read write to this location F800 00E8H U SV 32 SV 32 Reserved F800 00ECH BE BE Reserved do not read write to this location F800 00F0H U SV 32 SV 32 Reserved F800 00F4H F800 00FCH BE BE EBU_ BUSAP0 EBU Bus Access Parameter Register 0 F800 0100H U SV 32 SV 32 FFFF FFFFH Reserved F800 0104H BE BE EBU_ BUSAP1 EBU Bus Access Parameter Register 1 F800 0108H U SV 32 SV 32 FFFF FFFFH Reserved F800 ...

Page 1104: ... F800 0160H U SV 32 SV 32 DE00 0031H Reserved F800 0164H BE BE EBU_ EMUBC EBU Emulator Bus Configuration Register F800 0168H U SV 32 SV 32 0190 2077H Reserved F800 016CH BE BE EBU_ EMUBAP EBU Emulator Bus Access Parameter Register F800 0170H U SV 32 SV 32 5248 4911H Reserved F800 0174H BE BE EBU_ EMUOVL EBU Emulator Overlay Register F800 0178H U SV 32 SV 32 0000 0000H Reserved F800 017CH F800 018C...

Page 1105: ...ption Address Access Mode Reset Value Read Write Program Memory Unit PMU Reserved F800 0500H F800 0504H BE BE PMU_ID PMU Module Identification Register F800 0508H U SV BE 002E C0XXH Reserved F800 050CH BE BE Reserved must not be read or written otherwise unpredictable results may occur F800 0510H U SV SV Reserved F800 0514H F800 05FCH BE BE ...

Page 1106: ...us Register F800 2010H U SV BE 0XXX X0X0H FLASH_ FCON Flash Configuration Register F800 2014H U SV SV E 000X 0636H FLASH_ MARP Flash Margin Control Register PFlash F800 2018H U SV SV E 0000 8000H FLASH_ MARD Flash Margin Control Register DFlash F800 201CH U SV U SV 0000 8000H FLASH_ PROCON0 Flash Protection Config Register User 0 F800 2020H U SV BE 0000 XXXXH FLASH_ PROCON1 Flash Protection Config...

Page 1107: ...0 F801 0120H U SV SV 0000 0000H DMU_ OTAR0 DMU Overlay Target Address Register 0 F801 0124H U SV SV 0000 0000H DMU_ OMASK0 DMU Overlay Mask Register 0 F801 0128H U SV SV 0FFF FE00H DMU_ RABR1 DMU Redirected Address Base Register 1 F801 012CH U SV SV 0000 0000H DMU_ OTAR1 DMU Overlay Target Address Register 1 F801 0130H U SV SV 0000 0000H DMU_ OMASK1 DMU Overlay Mask Register 1 F801 0134H U SV SV 0...

Page 1108: ...H U SV SV 0000 0000H DMU_ OMASK5 DMU Overlay Mask Register 5 F801 0164H U SV SV 0FFF FE00H DMU_ RABR6 DMU Redirected Address Base Register 6 F801 0168H U SV SV 0000 0000H DMU_ OTAR6 DMU Overlay Target Address Register 6 F801 016CH U SV SV 0000 0000H DMU_ OMASK6 DMU Overlay Mask Register 6 F801 0170H U SV SV 0FFF FE00H DMU_ RABR7 DMU Redirected Address Base Register 7 F801 0174H U SV SV 0000 0000H ...

Page 1109: ...FFF FE00H DMU_ RABR11 DMU Redirected Address Base Register 11 F801 01A4H U SV SV 0000 0000H DMU_ OTAR11 DMU Overlay Target Address Register 11 F801 01A8H U SV SV 0000 0000H DMU_ OMASK11 DMU Overlay Mask Register 11 F801 01ACH U SV SV 0FFF FE00H DMU_ RABR12 DMU Redirected Address Base Register 12 F801 01B0H U SV SV 0000 0000H DMU_ OTAR12 DMU Overlay Target Address Register 12 F801 01B4H U SV SV 000...

Page 1110: ...5 DMU Redirected Address Base Register 15 F801 01D4H U SV SV 0000 0000H DMU_ OTAR15 DMU Overlay Target Address Register 15 F801 01D8H U SV SV 0000 0000H DMU_ OMASK15 DMU Overlay Mask Register 15 F801 01DCH U SV SV 0FFF FE00H DMU_ SBRCTR DMU Stand by SRAM Control Register F801 01E0H U SV SV 0000 0000H Reserved F801 01E4H F801 01FCH BE BE 1 Do not read from or write to these address locations Otherw...

Page 1111: ... Register F87F FA08H U SV BE 000F C0XXH Reserved F87F FA0CH F87F FA18H BE BE DBCU_ LEATT DBCU LMB Error Attribute Register F87F FA20H U SV 32 SV 32 XXXX XXX0H DBCU_ LEADDR DBCU LMB Error Address Register F87F FA24H U SV 32 BE XXXX XXXXH DBCU_ LEDATL DBCU LMB Error Data Low Register F87F FA28H U SV 64 BE XXXX XXXXH DBCU_ LEDATH DBCU LMB Error Data High Register F87F FA2CH XXXX XXXXH Reserved F87F F...

Page 1112: ...H Reserved F87F FC24H nBE nBE DMI_CON1 DMI Control Register 1 F87F FC28H U SV 32 SV E 32 0000 0000H Reserved F87F FC2CH F87F FCFCH nBE nBE 1 Access to the DMI registers must only be made with double word aligned word accesses An access not conforming to this rule or an access that does not follow the specified privilege mode supervisor mode Endinit protection or a write access to a read only regis...

Page 1113: ...isters Reserved F87F FD00H F87F FD04H BE BE PMI_ID PMI Module Identification Register F87F FD08H U SV 32 U SV NC 32 000B C0XXH Reserved F87F FD0CH BE BE PMI_CON0 PMI Control Register 0 F87F FD10H U SV 32 SV E 32 0000 0002H PMI_CON1 PMI Control Register 1 F87F FD14H U SV 32 SV 32 0000 0000H PMI_CON2 PMI Control Register 2 F87F FD18H U SV 32 SV NC 32 0000 0073H Reserved F87F FD1CH F87F FDFCH BE BE ...

Page 1114: ...n Register F87F FE08H U SV BE 000F C0XXH Reserved F87F FE0CH F87F FE18H BE BE PBCU_ LEATT PBCU LMB Error Attribute Register F87F FE20H U SV 32 SV 32 XXXX XXX0H PBCU_ LEADDR PBCU LMB Error Address Register F87F FE24H U SV 32 BE XXXX XXXXH PBCU_ LEDATL PBCU LMB Error Data Low Register F87F FE28H U SV 64 BE XXXX XXXXH PBCU_ LEDATH PBCU LMB Error Data High Register F87F FE2CH XXXX XXXXH Reserved F87F ...

Page 1115: ...Name Description Address Access Mode Reset Value Read Write Local Memory to FPI Bus Bridge LFI Bridge Reserved F87F FF00H F87F FF04H BE BE LFI_ID LFI Module Identification Register F87F FF08H U SV BE 000C C0XXH Reserved F87F FF0CH BE BE LFI_CON LFI Configuration Register F87F FF10H U SV SV 0000 0B02H Reserved F87F FF14H F87F FFFFH BE BE ...

Page 1116: ... Page 19 30 Note The ASC kernel register names described in Section 19 2 will be referenced in the TC1796 User s Manual by the module name prefix ASC0_ for the ASC0 interface and by ASC1_ for the ASC1 interface 19 1 ASC Kernel Description Figure 19 1 shows a global view of the ASC interface Figure 19 1 General Block Diagram of the ASC Interface The ASC module communicates with the external world v...

Page 1117: ...double buffered For multiprocessor communication a mechanism is included to distinguish address bytes from data bytes Testing is supported by a loop back option A 13 bit baud rate generator provides the ASC with a separate serial clock signal which can be accurately adjusted by a prescaler implemented as fractional divider Features Full duplex asynchronous operating modes 8 bit or 9 bit data frame...

Page 1118: ...is double buffered so a new character may be written to TBUF before the transmission of the previous character is complete This allows a back to back transmission of characters to take place without gaps Data reception is enabled by the receiver enable bit CON REN After a reception has been completed the received data and if provided by the selected operating mode the received parity bit can be re...

Page 1119: ...on pin RXD Figure 19 2 shows the block diagram of the ASC when operating in Asynchronous Mode Figure 19 2 Asynchronous Mode of the ASC Serial Port Control MCA05763 13 Bit Baud Rate Timer 13 Bit Reload Register fBRT fDIV R fASC Fractional Divider FDE fBR BRS Receive Int Req Transmit Int Req Transmit Buffer Int Req Error Int Req EIR TBIR TIR RIR M ODD STP OE PE FE Shift Clock Shift Clock Receive Shi...

Page 1120: ...arity bit will be set if the modulo 2 sum of the seven data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit CON PEN always OFF in 8 bit data mode The parity error flag CON PE will be set along with the error interrupt request flag if a wrong parity bit is received The received parity bit itself will be stored in RBUF too Figure 19 3 Asynchronous 8 Bit Fr...

Page 1121: ...ve interrupt request will be activated and no data will be transferred This feature can be used to control communication in multi processor systems for example When the master processor aims to transmit a block of data to one of several slaves it first sends out an address byte in this case a byte consists of nine bits that identifies the target slave An address byte differs from a data byte in th...

Page 1122: ...ronous Reception Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXD on condition that bits CON R and CON REN are set The receive data input pin RXD is sampled at sixteen times the rate of the selected baud rate A majority decision of the 7th 8th and 9th sample determines the effective sampled bit value This avoids erroneous results that may be caused by noise If the...

Page 1123: ...he wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred 19 1 3 4 RXD TXD Data Path Selection in Asynchronous Modes The data paths for the serial input and output data in Asynchronous Modes are affected by control bit CON LB loop back as shown in Figure 19 5 Figure 19 5 RXD TXD Data Path Selection in Asynchronous Modes MCA05766 ASC Asynch ...

Page 1124: ...elected with CON M 000B Eight data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is active only as long as data bits are transmitted or received Figure 19 6 Synchronous Mode of Serial Channel ASC MUX Serial Port Control MCA05767 BRS fBRT fDIV R fASC fBR REN OEN LB Receive Int Req Transmit Int Req Transmit Buffer Int Req ...

Page 1125: ...chronous transmission 19 1 4 2 Synchronous Reception Synchronous reception is initiated by setting bit CON REN 1 If bit CON R 1 the data applied at RXD is clocked into the receive shift register synchronously to the clock which is output at TXD After the 8th bit has been shifted in the contents of the receive shift register are transferred to the receive data buffer RBUF the receive interrupt requ...

Page 1126: ... shift clock If a data byte is received through RXD data is latched with the rising edge of the shift clock One shift clock cycle fBR delay is inserted between two consecutive receive or transmit data bytes Figure 19 7 ASC Synchronous Mode Waveforms D0 Valid Data n 2 Valid Data n Valid Data n 1 Data Bit n 2 Data Bit n Data Bit n 1 MCT05768 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D...

Page 1127: ... CON BRS and CON FDE In the asynchronous operating modes a fractional divider prescaler unit is available in addition to the two fixed dividers that allows selection of prescaler divider ratios of n 512 with n 0 511 Therefore the baud rate of ASC is determined by the module clock the content of register FDV the reload value in register BG and the operating mode asynchronous or synchronous Register...

Page 1128: ...aud rate of the baud rate generator depends on the settings of the following bits and register values Input clock fASC Selection of the baud rate timer input clock fDIV by bits CON FDE and CON BRS If bit CON FDE 1 fractional divider value of register FDV Value of the 13 bit reload register BG The output clock of the baud rate timer with the reload register is the sample clock in the asynchronous o...

Page 1129: ...ly used baud rates together with the required reload values and the deviation errors compared to the intended baud rate Note CON FDE must be 0 to achieve the baud rates in the table above The deviation errors given in the table are rounded Using a baud rate crystal will provide correct baud rates without deviation errors Table 19 1 Asynchronous Baud Rate Formulas using the Fixed Input Clock Divide...

Page 1130: ... stages Note In fractional divider mode the clock fDIV can have a maximum period jitter of one fASC clock period BG represents the content of the reload register bit field BG BR_VALUE taken as an unsigned 13 bit integer FDV represents the contents of the fractional divider register bit field FDV FD_VALUE taken as an unsigned 9 bit integer Table 19 3 Asynchronous Baud Rate Formulas using the Fracti...

Page 1131: ...eration of the serial channel ASC can be determined by the formulas as shown in Table 19 5 BG represents the content of the reload register bit field BG BR_VALUE taken as an unsigned 13 bit integer The maximum baud rate that can be achieved in Synchronous Mode when using a module clock of 75 MHz is 9 38 Mbit s Table 19 5 Synchronous Baud Rate Formulas BRS BG Formula 0 0 8191 1 MCA05770 13 Bit Baud...

Page 1132: ...uffer by software or DMA transfer at the time the reception of a new frame is complete the overrun error flag CON OE is set indicating that the error interrupt request is due to an overrun error Asynchronous Mode and Synchronous Mode 19 1 7 Interrupts Four interrupt sources are provided for serial channel ASC Line TIR indicates a transmit interrupt TBIR indicates a transmit buffer interrupt RIR in...

Page 1133: ...the transmitter interrupt request in Synchronous Mode it is entirely impossible Using the Transmit Buffer Interrupt TBIR to reload transmit data provides the time necessary to transmit a complete frame for the service routine as TBUF may be reloaded while the previous data is still being transmitted Figure 19 10 ASC Interrupt Generation As shown in Figure 19 10 TBIR is an early trigger for the rel...

Page 1134: ...modules is described in Table 18 8 on Page 18 20 of the TC1796 User s Manual System Units part Volume 1 Table 19 6 Registers Address Space Module Base Address End Address Note ASC0 F000 0A00H F000 0AFFH ASC1 F000 0B00H F000 0BFFH Table 19 7 Registers Overview ASC Kernel Registers Register Short Name Register Long Name Offset Address1 Description see PISEL Peripheral Input Select Register 04H Page ...

Page 1135: ... follows Module Base Address Table 19 6 Offset Address shown in this column ID Module Identification Register 08H Reset Value 0000 44XXH 31 16 15 8 7 0 0 MODNUM MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODNUM 15 8 r Module Number Value This bit field defines t...

Page 1136: ...RXD_I1 Bit RIS in the Peripheral Input Select Register PISEL determines which of theses two input lines is taken for RXD receive input purposes PISEL Peripheral Input Select Register 04H Reset Value 0000 0000H 31 1 0 0 R I S r rw Field Bits Type Description RIS 0 rw Receive Input Select 0B ASC receiver input RXD_I0 selected 1B ASC receiver input RXD_I1 selected 0 31 1 r Reserved Read as 0 should b...

Page 1137: ... rw rw rw rw rwh rwh rwh rw rw rw rwh rw rw Field Bits Type Description M 2 0 rw Mode Selection 000B 8 bit data Synchronous Mode 001B 8 bit data Asynchronous Mode 010B Reserved Do not use this combination 011B 7 bit data parity Asynchronous Mode 100B 9 bit data Asynchronous Mode 101B 8 bit data wake up bit Asynchronous Mode 110B Reserved Do not use this combination 111B 8 bit data parity Asynchron...

Page 1138: ... overrun error OEN 1 Must be cleared by software FDE 11 rw Fractional Divider Enable 0B Fractional divider disabled 1B Fractional divider is enabled and used as prescaler for baud rate timer bit BRS is don t care ODD 12 rw Parity Selection 0B Even parity selected parity bit 1 on odd number of 1s in data parity bit 0 on even number of 1s in data 1B Odd parity selected parity bit 1 on even number of...

Page 1139: ...dware after the read access but before the write back access of the RMW instruction it is overwritten with the old bit value and the hardware change of the bit gets lost This problem does not affect the bits that are intended to be modified by the RMW instruction It only affects bits that were not intended to be changed with the RMW instruction The three error flags in register CON and the REN bit...

Page 1140: ...T OE SET FE SET PE CLR OE CLR FE CLR PE 0 SET REN CLR REN 0 r w w w w w w r w w r Field Bits Type Description CLRREN 4 w Clear Receiver Enable Bit 0B No effect 1B Bit CON REN is cleared Bit is always read as 0 SETREN 5 w Set Receiver Enable Bit 0B No effect 1B Bit CON REN is set Bit is always read as 0 CLRPE 8 w Clear Parity Error Flag 0B No effect 1B Bit CON PE is cleared Bit is always read as 0 ...

Page 1141: ...ation e g SETPE CLRPE 1 the error flag in CON is not affected SETPE 11 w Set Parity Error Flag 0B No effect 1B Bit CON PE is set Bit is always read as 0 SETFE 12 w Set Framing Error Flag 0B No effect 1B Bit CON FE is set Bit is always read as 0 SETOE 13 w Set Overrun Error Flag 0B No effect 1B Bit CON OE is set Bit is always read as 0 0 3 0 7 6 31 14 r Reserved Read as 0 should be written with 0 F...

Page 1142: ...wh Field Bits Type Description BR_VALUE 12 0 rwh Baud Rate Timer Reload Register Value Reading BR_VALUE returns the 13 bit content of the baud rate timer Writing BR_VALUE loads the baud rate timer reload register BG should only be written if CON R 0 0 31 13 r Reserved Read as 0 should be written with 0 FDV Fractional Divider Register 18H Reset Value 0000 0000H 31 9 8 0 0 FD_VALUE r rw Field Bits T...

Page 1143: ...onous Mode TBUF Transmit Buffer Register 20H Reset Value 0000 0000H 31 9 8 0 0 TD_VALUE r rw Field Bits Type Description TD_VALUE 8 0 rw Transmit Data Register Value TBUF contains the data to be transmitted in the asynchronous and synchronous operating modes of the ASC Data transmission is double buffered therefore a new value can be written to TBUF before the transmission of the previous value is...

Page 1144: ...ue 0000 0000H 31 9 8 0 0 RD_VALUE r rh Field Bits Type Description RD_VALUE 8 0 rh Receive Data Register Value RBUF contains the received data bits and depending on the selected mode the parity bit in the asynchronous and synchronous operating modes of the ASC In Asynchronous Mode with CON M 011B 7 bit data parity the received parity bit is written into RBUF 7 In Asynchronous Mode with CON M 111B ...

Page 1145: ... supplied with interrupt control address decoding and port control logic Two DMA requests can be generated by each ASC module Both ASC modules are supplied by one common clock control unit Figure 19 12 ASC0 ASC1 Module Implementation and Interconnections MCB05773 ASC0 Module Kernel Port 5 Port 6 Control ASC1 Module Kernel P6 8 RXD0B P6 9 TXD0B Interrupt Control EIR TBIR TIR RIR Clock Control Addre...

Page 1146: ...lated external registers which are required for ASC0 ASC1 programming see also Figure 19 7 for the module kernel specific registers Figure 19 13 ASC0 ASC1 Implementation specific Special Function Registers MCA05774 ASC0_CLC ASC0_TSRC P5_IOCR0 ASC0_RSRC ASC0_ESRC ASC0_TBSRC ASC1_TSRC ASC1_RSRC ASC1_ESRC ASC1_TBSRC Control Registers Interrupt Registers Port Registers ASC0_PISEL ASC1_PISEL P6_IOCR8 P...

Page 1147: ...ck Control Register 00H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMC 0 FS OE SB WE E DIS SP EN DIS S DIS R rw r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 ...

Page 1148: ...a destructive read access means flags bits are set cleared by one read access to ASC module register depends on the selected CLC clock frequency which is selected via bit field RMC in the CLC register Therefore increasing ASC0_CLC RMC may result in a longer SPB read cycle access time Note Further details of the clock control register functionality are described in section Clock Control Register CL...

Page 1149: ...0 ASC1 module kernels alternatively to Port 5 or Port 6 as shown in Table 19 14 Register ASC0_PISEL controls the RXD input selection for ASC0 and ASC1_PISEL controls the RXD input selection for ASC1 Figure 19 14 RXD Input Line Selection of the ASC Modules ASC0 Module Kernel ASC1 Module Kernel MCA05775 P5 0 RXD0A P5 1 TXD0A RXD_I1 RXD_O PISEL RXD_I0 Port 5 Control TXD_O P5 2 RXD1A P5 3 TXD1A RXD_I1...

Page 1150: ...w Receive Input Select 0B ASC0 receiver input RXD0A P5 0 selected 1B ASC0 receiver input RXD0B P6 8 selected 0 31 1 0 Reserved Read as 0 should be written with 0 ASC1_PISEL ASC1 Peripheral Input Select Register 04H Reset Value 0000 0000H 31 1 0 0 R I S r rw Field Bits Type Description RIS 0 rw Receive Input Select 0B ASC1 receiver input RXD1A P5 2 selected 1B ASC1 receiver input RXD1B P6 10 select...

Page 1151: ...tput open drain and alternate output selections individually for each pin The I O lines for the ASC modules are controlled by the port input output control registers P5_IOCR0 and P6_IOCR8 Table 19 8 shows how bits and bit fields must be programmed for the required I O functionality of the ASC I O lines This table also shows the values of the peripheral input select registers Table 19 8 ASC0 ASC1 I...

Page 1152: ...egisters P5_IOCR0 Port 5 Input Output Control Register 0 10H Reset Value 2020 2020H 31 28 23 20 15 12 7 4 0 PC3 0 PC2 0 PC1 0 PC0 0 rw r rw r rw r rw r Field Bits Type Description PC0 PC1 PC2 PC3 7 4 15 12 23 20 31 28 rw Port Output Control for Port 5 Pins 0 31 These bit fields determine the output port functionality Port input output control for P5 0 RXD0A Port input output control for P5 1 TXD0A...

Page 1153: ...XD0B Port input output control for P6 9 TXD0B Port input output control for P6 10 RXD1B Port input output control for P6 11 TXD1B 1 Coding of bit field see Table 19 9 Shaded bits and bit fields are don t care for ASC I O port control Table 19 9 PCx Coding Class A2 Pads PCx 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function 0X00B Input No pull device connected 0X01B ...

Page 1154: ... rw r rw r Field Bits Type Description PDASC0 18 16 rw Pad Driver Mode for P5 0 RXD0A and P5 1 TXD0A1 1 Coding of bit field see Table 19 10 Shaded bits and bit fields are don t care for ASC I O port control PDASC1 22 20 rw Pad Driver Mode for P5 2 RXD1A and P5 3 TXD1A1 P6_PDR Port 6 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 26 24 0 0 PD CAN23 0 PD CAN01 0 PD SSC1 0 PD SSC0 0 r rw r rw...

Page 1155: ...ts ASC0_RSRC ASC1_RSRC control the receive interrupts ASC0_ESRC ASC1_ESRC control the error interrupts ASC0_TBSRC ASC1_TBSRC control the transmit buffer empty interrupts Table 19 10 Pad Driver Mode Mode Selection Class A2 Pads PDx Bit Field Driver Strength Signal Transitions 000B Strong driver Sharp edge1 1 In strong driver mode the output driver characteristics of class A2 pads can be additionall...

Page 1156: ...ster F4H Reset Value 0000 0000H ESRC Error Interrupt Service Request Control Register F8H Reset Value 0000 0000H TBSRC Transmit Buffer Interrupt Service Request Control Register FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Requ...

Page 1157: ...equest lines are connected to the DMA controller as shown in Table 19 11 Note Further details on DMA handling and processing are described in the chapter DMA Controller of the TC1796 System Units User s Manual Table 19 11 DMA Request Lines of ASC0 ASC1 Module Related ASC Interrupt DMA Request Line Description ASC0 RIR ASC0_RDR ASC0 Receive DMA Request TIR ASC0_TDR ASC0 Transmit DMA Request ASC1 RI...

Page 1158: ...dules port connections and control interrupt control address decoding clock control see Page 20 46 Note The SSC kernel register names described in Section 20 2 will be referenced in the TC1796 User s Manual by the module name prefix SSC0_ for the SSC0 interface and by SSC1_ for the SSC1 interface 20 1 SSC Kernel Description Figure 20 1 shows a global view of the SSC interface Figure 20 1 General B...

Page 1159: ... 2 are not valid for the SSC1 module Features Master and Slave Mode operation Full duplex or half duplex operation Automatic pad control possible Flexible data format Programmable number of data bits 2 to 16 bits Programmable shift direction LSB or MSB shift first Programmable clock polarity Idle low or idle high state for the shift clock Programmable clock data phase Data shift with leading or tr...

Page 1160: ...ble so it can work with other synchronous serial interfaces can serve for master slave or multi master interconnections or can operate compatibly with the popular SPI interface It can be used to communicate with shift registers I O expansion peripherals e g EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins...

Page 1161: ...al Bus Transmit Buffer Register TB TXFIFO 16 Bit Shift Register Pin Control Logic SSC Control Block Registers CON STAT EFM Status Control Receive Int Request Transmit Int Request TIR RIR EIR Shift Clock Clock Control fSSC Slave Select Output Generation Unit SLSO0 SLSO7 MTSRB MRST MTSRA MRSTB 1 MTSR 1 MRSTA 1 SCLKB SCLK 1 SCLKA 1 These signals are used in master mode only Baud Rate Generator fCLC S...

Page 1162: ...a given time The following features of the serial data bit transfer can be programmed The data width can be selected from 2 bits to 16 bits A transfer may start with the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading or trailing edge of the clock signal The baud rate shift clock can be set from 572 2 bit s up to 37 5 Mbit s 75 MHz module c...

Page 1163: ...ve line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift...

Page 1164: ...ives the line and enables the driver of its MRST pin All the other slaves must program their MRST pins to input Therefore only one slave can put its data onto the master s receive line Only reception of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then...

Page 1165: ...he SCLK line With the opposite clock edge the master simultaneously latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detec...

Page 1166: ...vice controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations As in full duplex mode there are two ways to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver The ...

Page 1167: ...p between the two successive frames if no delays are selected For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices that can operate with or require more than 16 data bits per transfer It is just a matter for software how long a total data frame length can be This option can also be used e g to interface to byte wide and word wid...

Page 1168: ...depends on the operating mode The SSC will automatically use the correct kernel output or kernel input line of the ports when switching modes Port pins assigned as SSC I O lines can be controlled either by hardware or by software When the SSC I O lines are connected to dedicated pins hardware I O control should typically be used In this case two output signals reflect the state of the CON EN and C...

Page 1169: ...mmed in CON BM Figure 20 6 shows an example of a TXFIFO operation with a typical data width of 8 bits representing a byte In this example seven bytes are transmitted via the transmit output line The TXFIFO interrupt trigger level TXFCON TXFITL is set to 0011B The first byte written into the empty TXFIFO via TB is directly transferred into the transmit shift register and is not written into the FIF...

Page 1170: ...Operation Example MCA05781 Byte 2 Byte 3 Byte 5 Byte 6 Byte 7 TIR TIR TIR 0010 MTSR FSTAT TXFFL 0001 0000 0010 0011 0100 0101 0000 Byte 5 Byte 3 Byte 4 Byte 6 Byte 5 Byte 4 Byte 6 Byte 5 Byte 6 Byte 7 TX FIFO empty Byte 5 Byte 3 Byte 4 Byte 6 Byte 2 Byte 5 Byte 3 Byte 4 Byte 2 Byte 3 Byte 4 Byte 2 Byte 3 Byte 2 Byte 2 Byte 5 Byte 6 Byte 7 Byte 7 Byte 6 Write Byte 1 Write Byte 2 Write Byte 3 Write ...

Page 1171: ...ata width of 8 bits representing a byte In this example six bytes are received via the receive input line The RXFIFO interrupt trigger level RXFCON RXFITL is set to 0011B Therefore the first receive interrupt request RIR is generated after the reception of Byte 3 RXFIFO is filled with three messages After the reception of Byte 4 three bytes are read out of the RXFIFO After this read operation the ...

Page 1172: ... that the receive operation of the SSC is stopped in this case without changing the content of the RXFIFO After setting CON EN again the RXFIFO with its content is again available Figure 20 7 Receive FIFO Operation Example MCA05782 RIR MRST FSTAT RXFFL 0001 0000 0011 0010 0001 0000 RX FIFO empty In this example RXFCON RXFITL 0011B 0100 Byte 1 Byte 2 Byte 3 Byte 1 Byte 2 Byte 1 Byte 4 Byte 1 Byte 2...

Page 1173: ...ty a receive interrupt request RIR is always generated when the first message is written into an empty RXFIFO FSTAT RXFFL changes from 0000B to 0001B If the RXFIFO is filled with at least one message the occurrence of further receive interrupts depends on the read operations of register RB The RIR will always be activated after a RB read operation if the RXFIFO still contains data FSTAT RXFFL is n...

Page 1174: ... Transparent Mode for the TXFIFO is enabled when bits TXFCON TXTMEN and TXFCON TXFEN are set TIR is also activated after a TXFIFO flush operation or when the TXFIFO becomes enabled TXFCON TXTMEN and TXFCON TXFEN set when it was previously disabled In these cases the TXFIFO is empty and ready to be filled with data If the TXFIFO is full FSTAT TXFFL 1000B and an additional message is written into th...

Page 1175: ...d value In this mode the desired reload value can be written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baud rate 20 1 BR_VALUE represents the content of the reload register taken as an unsigned 16 bit integer while Baud rateSSC is equal to fSCLK as shown in Figu...

Page 1176: ...e calculations the dependencies of fSSC from fSYS must be taken into account Section 20 3 2 1 on Page 20 48 describes these dependencies in detail Table 20 1 Typical Baud Rates of the SSC fSSC 75 MHz Reload Value BR_VALUE Baud Rate fSCLK Deviation 0000H 37 5 Mbit s only in Master Mode 0 0 0001H 18 75 Mbit s 0 0 0025H 1 Mbit s 1 3 0176H 100 kbit s 0 0 0EA5H 10 kbit s 0 0 9276H 1 kbit s 0 0 FFFFH 57...

Page 1177: ...ultiplexer which is controlled by PISEL SLSIS Figure 20 10 Slave Select Input Logic With PISEL SLSIS 000B and Slave Mode selected the SLSI input line does not control the SSC I O lines The slave receive input signal MTSRA or MTSRB selected by PISEL SRIS and the slave clock input signal SCLKA or SCLKB selected by PISEL SCIS are passed further as MTRSI and SCLKI to the internal SSC control logic The...

Page 1178: ...EL SCIS Slave Mode clock input select 20 1 2 11 Slave Select Output Generation Unit In Master Mode the slave select output generation unit of the SSC automatically generates up to eight slave select output lines for serial transmit operations The slave select output generation unit further makes it possible to adjust the chip select timing parameters The active inactive state of a slave select out...

Page 1179: ...he first SCLK edge already latches the first data bit at MRST The three parameters of a chip select period are controlled by bit fields in the Slave Select Output Timing Control Register SSOTC Each of these bit fields can contain a value from 0 to 3 defining delay cycles of 0 to 3 multiples of the tSCLK shift clock period The three parameters are 1 Number of leading delay cycles tSLSOL SSOTC LEAD ...

Page 1180: ...show the timing of SLSO7 in delayed mode Figure 20 13 SLSO7 Delayed Mode Slave Select Register Update At the start of an internal transmit sequence with the TB register write operation the parameters in registers SSOC and SSOTC are buffered This means that they remain stable while a serial transmission is in progress Therefore it is always guaranteed that the data of one serial transmission is alw...

Page 1181: ...determine the cause of the error interrupt The error flags are not cleared automatically but must be cleared via register EFM after servicing This allows servicing of some error conditions via interrupt while others may be polled by software The error status flags can be set and cleared by software via the error flag modification register EFM Note The error interrupt handler must clear the associa...

Page 1182: ...ture detects false additional pulses or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit CON AREN 1 an automatic reset of the SSC will be performed This is done to re initialize the SSC if too few or too many clock pulses have been detected Note This error can occur after any transfer if the communication is stopped This is due to the fact that SS...

Page 1183: ... push pull output drivers not selected for transmission will normally have its output drivers switched off However to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer The cause of an error interrupt request receive phase baud rate transmit error can be identified by the error status flags in control register CON Note ...

Page 1184: ...isters The complete and detailed address map of the SSC modules is described in Table 18 27 on Page 18 81 of the TC1796 User s Manual System Units part Volume 1 Table 20 2 Registers Address Space SSC Kernel Registers Module Base Address End Address Note SSC0 F010 0100H F010 01FFH SSC1 F010 0200H F010 02FFH Table 20 3 Registers Overview SSC Kernel Registers Register Short Name Register Long Name Of...

Page 1185: ...TC Slave Select Output Timing Control Register 1CH Page 20 38 TB Transmit Buffer Register 20H Page 20 45 RB Receive Buffer Register 24H Page 20 45 RXFCON Receive FIFO Control Register 30H Page 20 40 TXFCON Transmit FIFO Control Register 34H Page 20 42 FSTAT FIFO Status Register 38H Page 20 44 1 The absolute register address is calculated as follows Module Base Address Table 20 2 Offset Address sho...

Page 1186: ... SSC module version ID Module Identification Register 08H Reset Value 0000 45XXH 31 16 15 8 7 0 0 MODNUM MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODNUM 15 8 r Module Number Value This bit field defines the module identification number for the SSC 45H 0 31 16 ...

Page 1187: ...4 3 2 1 0 0 STIP 0 SLSIS SCIS SRIS MRI S r rw r rw rw rw rw Field Bits Type Description MRIS 0 rw Master Mode Receive Input Select MRIS selects the receive input line in Master Mode 0B Receive input line MRSTA is selected 1B Receive input line MRSTB is selected SRIS 1 rw Slave Mode Receive Input Select SRIS selects the receive input line in Slave Mode 0B Receive input line MTSRA is selected 1B Rec...

Page 1188: ...ation 101B SLSI input line 5 is selected for operation 110B SLSI input line 6 is selected for operation 111B SLSI input line 7 is selected for operation In the TC1796 other combinations of SLSIS except 000B and 001B are reserved and must not be used STIP 8 rw Slave Transmit Idle State Polarity This bit determines the logic level of the Slave Mode transmit signal when the SSC slave select input sig...

Page 1189: ...3 0 rw Data Width Selection BM determines the number of data bits of the serial frame 0000B Reserved do not use this combination 0001B Transfer Data Width is 2 bit 0010B Transfer Data Width is 3 bit B 1110B Transfer Data Width is 15 bit 1111B Transfer Data Width is 16 bit HB 4 rw Heading Bit Control 0B Transmit Receive LSB First 1B Transmit Receive MSB First PH 5 rw Clock Phase Control 0B Shift tr...

Page 1190: ...rate errors AREN 12 rw Automatic Reset Enable 0B No additional action upon a baud rate error 1B SSC is automatically reset on a baud rate error MS 14 rw Master Select 0B Slave Mode Operate on shift clock received via SCLK 1B Master Mode Generate shift clock and output it via SCLK The inverted state of this bit is available on module output line M S selected see Figure 20 2 EN 15 rw Enable Bit 0B T...

Page 1191: ...e Description BC 3 0 rh Bit Count Status BC indicates the current status of the shift counter The shift counter is updated with every shifted bit TE 8 rh Transmit Error Flag 0B No error 1B Transfer starts with the slave s transmit buffer not being updated RE 9 rh Receive Error Flag 0B No error 1B Reception completed before the receive buffer was read PE 10 rh Phase Error Flag 0B No error 1B Receiv...

Page 1192: ...3 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET BE SET PE SET RE SET TE CLR BE CLR PE CLR RE CLR TE 0 w w w w w w w w r Field Bits Type Description CLRTE 8 w Clear Transmit Error Flag 0B No effect 1B Bit STAT TE is cleared Bit is always read as 0 CLRRE 9 w Clear Receive Error Flag 0B No effect 1B Bit STAT RE is cleared Bit is always read as 0 CLRPE 10 w Clear Phase Error Flag ...

Page 1193: ...ffected SETTE 12 w Set Transmit Error Flag 0B No effect 1B Bit STAT TE is set Bit is always read as 0 SETRE 13 w Set Receive Error Flag 0B No effect 1B Bit STAT RE is set Bit is always read as 0 SETPE 14 w Set Phase Error Flag 0B No effect 1B Bit STAT PE is set Bit is always read as 0 SETBE 15 w Set Baud Rate Error Flag 0B No effect 1B Bit STAT BE is set Bit is always read as 0 0 7 0 31 16 r Reser...

Page 1194: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OEN 7 OEN 6 OEN 5 OEN 4 OEN 3 OEN 2 OEN 1 OEN 0 AOL 7 AOL 6 AOL 5 AOL 4 AOL 3 AOL 2 AOL 1 AOL 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description AOLn n 0 7 n rw Active Output Level 0B SLSOn is at low level during the chip select active time tSLSOACT The high level is the inactive level of SLSOn 1B SLSO line n is at high level during th...

Page 1195: ...ding Delay This bit field determines the number of leading delay clock cycles A leading delay clock cycle is always a multiple of an SCLK shift clock period 00B Zero leading delay clock cycle selected1 01B One leading delay clock cycle selected 10B Two leading delay clock cycles selected 11B Three leading delay clock cycles selected TRAIL 3 2 rw Slave Output Select Trailing Delay This bit field de...

Page 1196: ...delay clock cycles selected 11B Three inactive delay clock cycles selected SLSO7MOD 8 rw SLSO7 Delayed Mode Selection This bit selects the delayed mode for the SLSO7 slave select output 0B Normal mode selected for SLSO7 1B Delayed mode selected for SLSO7 0 7 6 31 9 r Reserved Read as 0 should be written with 0 1 For getting a best case timing with no timing delays see Figure 20 11 this bit field v...

Page 1197: ...7 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RXFITL 0 RX TM EN RXF FLU RXF EN r rw r rw w rw Field Bits Type Description RXFEN 0 rw RXFIFO Enable 0B RXFIFO is disabled 1B RXFIFO is enabled Note Resetting RXFEN automatically flushes the RXFIFO RXFFLU 1 w RXFIFO Flush 0B No operation 1B RXFIFO is flushed Note Setting RXFFLU clears bit field RXFFL in register FSTAT RXFFLU is always read as 0 RXTM...

Page 1198: ... 0000B Reserved Do not use this combination 0001B Interrupt trigger level is set to 1 0010B Interrupt trigger level is set to 2 B 0111B Interrupt trigger level is set to 7 1000B Interrupt trigger level is set to 8 Other combinations of RXFITL are reserved and should not be used Note In Transparent Mode this bit field is don t care 0 7 3 31 12 r Reserved Read as 0 should be written with 0 1 In the ...

Page 1199: ...17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TXFITL 0 TX TM EN TXF FLU TXF EN r rw r rw w rw Field Bits Type Description TXFEN 0 rw TXFIFO Enable 0B TXFIFO is disabled 1B TXFIFO is enabled Note Resetting TXFEN automatically flushes the TXFIFO TXFFLU 1 w TXFIFO Flush 0B No operation 1B TXFIFO is flushed Note Setting TXFFLU clears bit field TXFFL in register FSTAT TXFFLU is always read as 0 TXT...

Page 1200: ...000B Reserved Do not use this combination 0001B Interrupt trigger level is set to 1 0010B Interrupt trigger level is set to 2 B 0111B Interrupt trigger level is set to 7 1000B Interrupt trigger level is set to 8 Other combinations of TXFITL are reserved and should not be used Note In Transparent Mode this bit field is don t care 0 7 3 31 12 r Reserved Read as 0 should be written with 0 1 In the SS...

Page 1201: ... 0111B RXFIFO is filled with 7 bytes 1000B RXFIFO is filled with 8 bytes RXFFL is cleared after a RXFIFO flush operation 1 The data width of a RXFIFO and TXFIFO stage can be programmed from 2 to 15 bits The data width byte mentioned in this description represents a data width of 8 bits 2 In the SSC0 module with 8 stage RXFIFO and TXFIFO the most significant bits of RXFFL and TXFFL FSTAT 4 and FSTA...

Page 1202: ... Field Bits Type Description TB_VALUE 15 0 rw Transmit Data Register Value Register TB_VALUE stores the data value to be transmitted TB_VALUE Unused bits of TB_VALUE as defined by CON BM are ignored during transmission 0 31 16 r Reserved Read as 0 should be written with 0 RB Receive Buffer Register 24H Reset Value 0000 0000H 31 16 15 0 0 RB_VALUE r rh Field Bits Type Description RB_VALUE 15 0 rh R...

Page 1203: ...dress Decoder Interrupt Control fSSC0 Address Decoder Interrupt Control To DMA fCLC0 fSSC1 fCLC1 Clock Control SSC0_RDR SSC0_TDR To DMA SSC1_RDR SSC1_TDR Port 2 Control MRSTB MTSR Master SLSI1 SLSO 7 2 MRSTA MTSRB MRST MTSRA SCLKB SCLK SCLKA Slave Slave Master Slave Master Port 6 Control MRSTB MTSR Master SLSO 7 2 MRSTA MTSRB MRST MTSRA SCLKB SCLK SCLKA Slave Slave Master Master MTSR0 MRST0 SCLK0 ...

Page 1204: ...rt 2 Two SLSOx outputs of SSC0 are connected to dedicated pins Note that only SSC0 contains an 8 stage Receive and Transmit FIFO SSC1 does not provide any FIFO functionality 20 3 2 SSC0 SSC1 Module Related External Registers Figure 20 17 summarizes the module related external registers which are required for SSC0 SSC1 programming see also Figure 20 15 for the module kernel specific registers Figur...

Page 1205: ...ator which finally determines the baud rate of the serial data The fractional divider registers SSC0_FDR and SSC1_FDR control the frequency of fSSC0 and fSSC1 and make it possible to enable disable it independently of fCLC0 and fCLC1 The Baud Rate Timer Reload Register SSC0_BR and SSC1_BR define serial data baud rate dependent from the frequency of fSSC0 and fSSC1 Figure 20 18 SSC Clock Generation...

Page 1206: ... rate generator see Page 20 18 and the fractional divider see chapter System Control Unit of the TC1796 System Units User s Manual the resulting serial data baud rate is defined by 20 4 20 5 Note Equation 20 2 and Equation 20 4 apply to normal divider mode of the fractional divider FDR DM 01B Equation 20 3 and Equation 20 5 apply to fractional divider mode FDR DM 10B fSSCx fSYS 1 n with n 1024 FDR...

Page 1207: ...H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for ...

Page 1208: ...SSC1_FDR SSC1 Fractional Divider Register 0CH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS CLK EN HW SUS REQ SUS ACK 0 RESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend m...

Page 1209: ... not provide open drain capability The SSC1 I O functionality must be selected by the following port control operations additionally to the PISEL programming Input output function selection IOCR registers Pad driver characteristics selection for the outputs PDR registers The SSC1 port input output control registers contain the bit fields that select the digital output and input driver characterist...

Page 1210: ...pins are always outputs that are tri stated when SSC0 is disabled SSC0_CON EN 0 Figure 20 19 SLSO Output Selection Table 20 4 shows how bits and bit fields must be programmed for the required I O functionality of the SSC I O lines Table 20 4 SSC0 and SSC1 I O Line Selection and Setup Module Port Lines Input Output Control Register Bits1 I O SSC0 MTSR0 SSC0_CON MS 0 SSC0_ CON EN 1 Input SSC0_CON MS...

Page 1211: ...R0 PC2 1X10B SSC0 SSC1 P2_IOCR0 PC2 1X11B SSC0 P2 3 SLSO3 P2_IOCR0 PC3 1X01B Output SSC1 P2_IOCR0 PC3 1X10B SSC0 SSC1 P2_IOCR0 PC3 1X11B SSC0 P2 4 SLSO4 P2_IOCR4 PC4 1X01B Output SSC1 P2_IOCR4 PC4 1X10B SSC0 SSC1 P2_IOCR4 PC4 1X11B SSC0 P2 5 SLSO5 P2_IOCR4 PC5 1X01B Output SSC1 P2_IOCR4 PC5 1X10B SSC0 SSC1 P2_IOCR4 PC5 1X11B SSC0 P2 6 SLSO6 P2_IOCR4 PC6 1X01B Output SSC1 P2_IOCR4 PC6 1X10B SSC0 SS...

Page 1212: ...ontrol for P2 3 SLSO3 1 Coding of bit field see Table 20 5 Shaded bits and bit fields are don t care for SSC I O port control P2_IOCR4 Port 2 Input Output Control Register 4 14H Reset Value 2020 2020H 31 28 23 20 15 12 7 4 0 PC7 0 PC6 0 PC5 0 PC4 0 rw r rw r rw r rw r Field Bits Type Description PC4 PC5 PC6 PC7 7 4 15 12 23 20 31 28 rw Port Output Control for Port 2 7 4 1 These bit fields determin...

Page 1213: ... input output control for P6 5 MRST1 Port input output control for P6 6 SCLK1 Port input output control for P6 7 SLSI1 1 Coding of bit field see Table 20 5 Shaded bits and bit fields are don t care for SSC I O port control Table 20 5 PCx Coding PCx 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function 0X00B Input No pull device connected 0X01B Pull down device connecte...

Page 1214: ...r rw r rw r Field Bits Type Description PDSLS0 18 16 rw Pad Driver Mode for P2 3 2 SLSO 3 2 1 1 Coding of bit field see Table 20 6 Shaded bits and bit fields are don t care for SSC I O port control PDSLS1 22 20 rw Pad Driver Mode for P2 7 4 SLSO 7 4 1 P6_PDR Port 6 Pad Driver Mode Register 40H Reset Value 0000 0000HH 31 22 20 18 16 0 0 PD CANCD 0 PD CANAB 0 PD SSC1 0 0 0 r rw r rw r rw r rw r Fiel...

Page 1215: ...on Class A2 Pads PDx Bit Field Driver Strength Signal Transitions 000B Strong driver Sharp edge1 1 In strong driver mode the output driver characteristics of class A2 pads can be additionally controlled by the temperature compensation logic 001B Medium edge1 010B Soft edge1 011B Weak driver 100B Medium driver Sharp edge 101B Medium edge 110B Soft edge 111B Weak driver ...

Page 1216: ...ce Request Control Register F4H Reset Value 0000 0000H RSRC Receive Interrupt Service Request Control Register F8H Reset Value 0000 0000H ESRC Error Interrupt Service Request Control Register FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 r...

Page 1217: ...me active whenever the corresponding interrupt request line becomes activated The DMA request lines are connected to the DMA controller as shown in Table 20 7 Note Further details on DMA handling and processing are described in Chapter 12 of the TC1796 System Units User s Manual Volume 1 Table 20 7 DMA Request Lines of SSC0 SSC1 Module SSCInterrupt Request Line DMA Request Line Description SSC0 RI...

Page 1218: ...ctional description of the MSC kernel see Page 21 3 MSC kernel register descriptions see Page 21 36 TC1796 implementation specific details and registers of the MSC module port connections and control interrupt control address decoding and clock control see Page 21 62 Note The MSC kernel register names described in Section 21 2 will be referenced in the TC1796 User s Manual by the module name prefi...

Page 1219: ...stream channel The MSC receives data and status back from the power device via a low speed asynchronous serial data stream upstream channel Figure 21 1 shows a typical TC1796 application in which an MSC interfaces controls two power devices Output data is provided by the GPTA modules Figure 21 1 MSC to External Power Device Connection Some applications are Control of the external power switching u...

Page 1220: ...ine I O lines Eight output lines are required for the serial communication of the downstream channel clock data and enable signals One out of eight input lines SDI 7 0 is used as serial data input signal for the upstream channel The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL ALTINH input lines These inpu...

Page 1221: ...erial output clock frequency fFCL fMSC 2 Fractional clock divider for precise frequency control of serial clock fMSC Command data and passive frame types Start of serial frame Software controlled timer controlled or free running Programmable upstream data frame length 16 or 12 bits Transmission with or without SEL bit Flexible chip select generation indicates status during serial frame transmissio...

Page 1222: ...Figure 21 3 Downstream Channel Block Diagram The enable signals ENL ENH and ENC indicate certain phases of the serial transmission in relation to the serial clock FCL In the I O control logic these signals can be combined to four enable select outputs EN 3 0 For supporting differential output drivers the serial clock output FCL and the serial data output SO are available in both polarities indicat...

Page 1223: ...is split into two parts The SRL active phase in which the content of the shift register low part SRL is transmitted and the SRH active phase in which the content of the shift register high part SRH is transmitted At the beginning of the SRL and SRH active phase a selection bit SELL can be optionally inserted into the serial data stream In the frame shown in Figure 21 4 SELL is generated at the beg...

Page 1224: ...ed from 0 up to 32 bits In other words whenever bits of SRH are transmitted they are always preceded by the transmission of the complete SRL content During the active phase of a command frame the enable output signal ENC becomes active The enable output signals ENL and ENH remain inactive The passive phase of a command frame always has a fixed length of 2 tFCL The diagram shown in Figure 21 4 assu...

Page 1225: ...ods 000000B No bit shifted out 1 0 2 3 000001B SRL 0 shifted out 1 1 2 4 000010B SRL 1 0 shifted out 1 2 2 5 000011B SRL 2 0 shifted out 1 3 2 6 001111B SRL 14 0 shifted out 1 15 2 18 010000B SRL 15 0 shifted out 1 16 2 19 010001B SRL 15 0 and SRH 0 shifted out 1 17 2 20 010010B SRL 15 0 and SRH 1 0 shifted out 1 18 2 21 010011B SRL 15 0 and SRH 2 0 shifted out 1 19 2 22 011111B SRL 15 0 and SRH 1...

Page 1226: ...ENL becomes active and during the SRH active phase of a data frame the enable output signal ENH becomes active The enable output signal ENC remains inactive The length of the data frame s passive phase is variable and is defined by bit field DSC PPD It can be within a range of 2 tFCL up to 31 tFCL The diagram shown in Figure 21 5 assumes that the FCL clock is only generated during the active phase...

Page 1227: ...ning of the SRH active phase Table 21 3 Data Frame SRL SRH Length Parameters DSC NDBL SRL Bits Transmitted in SRL Active Phase DSC NDBH SRH Bits Transmitted in SRH Active Phase 00000B No SRL bit transmitted 00000B No SRH bit transmitted 00001B SRL 0 00001B SRHL 0 00010B SRL 1 0 00010B SRH 1 0 00011B SRL 2 0 00011B SRH 2 0 01111B SRL 14 0 01111B SRH 14 0 10000B SRL 15 0 10000B SRH 15 0 Other bit co...

Page 1228: ...ve time frame has the length defined by the five data frame parameters according Equation 21 1 They are generated only in Data Repetition Mode Under special conditions command frame insertion passive time frames can be shortened see Figure 21 9 During passive time frames the data output SO have to be considered as invalid at the receiving device and the clock output FCL may toggle or not as select...

Page 1229: ...gister Figure 21 7 shows the logic that is implemented for the SRL shift register loading operation The logic for the SRH shift register loading operation is equivalent to the one for the SRL register Its differences in data sources and register controls are described later in this section Figure 21 7 SRL Shift Register Data Loading Control MCA05801 ALTINL x To SRL bit x SLx DSDSL DDH 32 15 16 0 D...

Page 1230: ...it part DCL of the downstream control register is loaded completely into SRL Table 21 5 summarizes all SRL data source selection capabilities x 0 15 SRH Shift Register Loading The SRH shift register load operation is equivalent to the SRL shift register load operation The following differences must be taken into account for SRH shift register loading Input lines ALTINH are connected instead of ALT...

Page 1231: ...d sent out if the downstream channel is idle If a data frame or a command frame is currently processed and output the data frame transmission is delayed and started when the active downstream frame has been finished The data pending bit DSC DP becomes cleared by hardware when the first bit of the data frame is sent out A command frame always has priority over the data frame This means that if both...

Page 1232: ...rame is started if no command frame has been requested and DSC DP is cleared again by hardware after the data frame has been started Data Frames are always aligned to time reference points This means they always start at a TRP Passive time frames can be shortened This is especially the case when command frames are inserted Continuous data frame transmission can be interrupted by insertion of comma...

Page 1233: ...rame is again aligned to a TRP Figure 21 10 is a flow diagram of the Data Repetition Mode This diagram especially shows the behavior of the data and command pending bits DSC DP and DSC CP If both frame pending bits are set DSC DP DSC CP 1 the command frame will always be sent first followed by the data frame when the next TRP is reached assuming no further command frame has been requested When the...

Page 1234: ...d since the start of the current data command or passive time frame As in Triggered Mode the shift register loading event described in Section 21 1 2 2 occurs in Data Repetition Mode just before a TRP i e shortly before a command or data frame transmission is started MCA05804 Starting Data Repetition Mode writing DSC TM 1 DSC CP 1 yes no TRP reached DSC DP 1 Start passive time frame no yes Load sh...

Page 1235: ...assive time frame counter counts up from 0000B to the value which has been written into bit field DSS NPTF number of passive time frames DSS PFC 0000B indicates that a data frame is requested for transmission Figure 21 11 Passive Frame Counter Operation with DSS NPTF 0101B MCT05805 DF PTF PTF PTF PTF DF PTF Passive Time Frame DF Data Frame TRP Time Reference Point PTF PTF TRP TRP TRP TRP TRP TRP T...

Page 1236: ...unting up again with the next frame independently whether a data frame command frame or passive time frame is started as next frame Figure 21 12 shows an example of downstream channel data frame transmission In this example the selection bit for the SRL active frame is enabled ENSELL 1 and the selection bit for the SRH active frame is disabled ENSELL 0 With loading of the shift register SRL SRH th...

Page 1237: ...eneration is device specific and depends on the implementation of the MSC module The TC1796 specific clock generation is described on Page 21 65 21 1 2 6 Abort of Frames Only a reset condition of the device can abort a current transmission The MSC module does not start a new frame transmission when the downstream channel becomes disabled the suspend mode is requested or the sleep mode is entered I...

Page 1238: ...m Channel Block Diagram The incoming data at SI is sampled after it has been filtered for spikes The detected logic states of the serial input are clocked into a shift register After the complete reception of the serial data frame the content of the shift register is transferred into one of the four data registers and an interrupt can be generated optionally The receive baud rate is directly coupl...

Page 1239: ...d the parity error flag PERR in the related Upstream Data Register UDx is set Note that a setting of the parity error flag PERR does not generate an interrupt The PERR bits must be checked by software Further the UDx registers store the parity bit of the incoming data frame UDx P and the parity bit that is generated internally UDx IPF Bit USR PCTR determines the parity mode even or odd that is sel...

Page 1240: ...tion is described on Page 21 30 Frame Reception with Address Field Frame reception for a 16 bit data frame see Figure 21 16 is selected by USR UFT 1 When the content of the receive buffer has been received completely it is transferred to one of the four UDx registers The two most significant address bits A 3 2 of the received 4 bit address field select the number x of register UDx in which the rec...

Page 1241: ...eption scheme is comparable with that of the 16 bit data frame reception but there are a few differences The upstream counter USR UC is initially loaded with 01100B The received frame content is always stored in register UD0 Bit field UD0 LABF is always loaded with 00B when the frame is stored MCT05810 D0 D1 D7 D6 Start P 16 Bit Upstream Data Frame A3 A2 Stop Stop 16 15 14 13 12 11 10 4 3 2 1 0 0 ...

Page 1242: ...y a programmable clock divider The frequency of fBR determines the width of a received bit cell and therefore the baud rate for the receive data The content of bit field USR URR selects the baud rate according Table 21 6 The resulting baud rate formula is 21 2 Note With the USR URR 000B the upstream channel is disabled and data reception is not possible Table 21 6 Upstream Channel Divide Factor DF...

Page 1243: ...divide factor DF shown in Table 21 6 is reached In the middle of the sampling counter s count range the logic state at SI is evaluated and in case of a data bit latched in the receive buffer s shift register With the reload of the sampling counter the shift register is shifted by one bit position Figure 21 18 Upstream Channel Sampling with URR 010B 21 1 3 5 Spike Filter The upstream channel input ...

Page 1244: ...wnstream Channel Output Control As shown in Figure 21 5 and Figure 21 6 the active phases during downstream channel operation are indicated by three enable signals ENL indicates the SRL active phase of a data frame ENH indicates the SRH active phase of a data frame ENC indicates the active phase of a command frame The chip select output control logic of the MSC uses a signal compressing scheme sim...

Page 1245: ...and CSC determine which chip enable output becomes active on a valid internal enable signal In the MSC enable signals are high level active signals If required in a specific application all chip enable outputs ENx can be assigned for low level active polarity by setting bit OCR CSLP Figure 21 20 Downstream Channel Chip Enable Output Control MCA05814 CSL OCR CSH OCR CSC OCR 1 EN0 1 1 CSLP OCR EN1 E...

Page 1246: ...Control With OCR CLP 0 FCLP has identical and FCLN has inverted polarity compared to FCL Setting OCR CLP exchanges the signal polarities of FCLP and FCLN An equivalent control capability is available for the SOP and SON data outputs controlled by OCR SLP One additional control capability not shown in Figure 21 21 is available for the FCL signal With OCR CLKCTRL 1 the FCL clock signal will always b...

Page 1247: ...nnel can be connected to up to eight SDI 7 0 serial inputs Bit field OCR SDISEL selects one out of these input lines input signal SDI If OCR ILP 0 SDI is directly connected to the serial receive buffer input SI If OCR ILP 1 SDI is connected to input SI via an inverter Figure 21 22 Upstream Channel Serial Data Input Control MCA05816 ILP OCR SI SDI SDI 7 0 8 SDISEL OCR 3 1 0 ...

Page 1248: ...tware set clear capability and an interrupt node pointer An interrupt event internally generated as a request pulse is always stored in an interrupt status flag that is located in the Interrupt Status Register ISR All interrupt status flag can be set or cleared individually by software via the interrupt Set Clear Register ISC Software controlled interrupt generation can be initiated by setting the...

Page 1249: ...Data Frame Interrupt Control 21 1 5 2 Command Frame Interrupt A command frame interrupt can be generated at the end of a downstream channel command frame see also Figure 21 5 Figure 21 24 Command Frame Interrupt Control MCA05817_mod DEDI ISR Data Frame Interrupt to Int Comp EDI Set Software Clear ISC SDEDI CDEDI EDIE 00 11 1 Software Set Hardware Set EDIE ICR 01 10 2 First data bit shifted Last da...

Page 1250: ...rame Finished Interrupt A time frame finished interrupt can be generated at the end of a downstream channel passive time phase Figure 21 25 Time Frame Interrupt Control TFIE ICR TFI DTFI ISR Software Clear Set MCA05819_mod Time Frame Interrupt to Int Comp Time Frame Finished ISC SDTFI CDTFI 1 Software Set Hardware Set ...

Page 1251: ...upt when the updated value is not equal 00H Only an update of register UD3 generates a receive data interrupt The selection of the interrupt generation condition is controlled by bit field ICR RDIE Setting ICR RDIE 0 disables the receive data interrupt in general ISR URDI is the interrupt status flag that can be set or cleared when writing bits ISC SRDI or ISC CRDI with a 1 Figure 21 26 Receive Da...

Page 1252: ...so makes it possible to connect more than one interrupt source to one interrupt output SRx Figure 21 27 MSC Interrupt Request Compressor Note The number of available MSC interrupt outputs depends on the implementation of the MSC module s in the specific product see Section for TC1796 details MCA05821 EDIP ICR ECIP ICR TFIP ICR RDIP ICR Service Request Output SR0 Service Request Output SR1 Service ...

Page 1253: ... the MSC0 module is described in Table 18 7 on Page 18 16 of the TC1796 User s Manual System Units part Volume 1 Table 21 8 Registers Address Space MSC Kernel Registers Module Base Address End Address Note MSC0 F000 0800H F000 08FFH MSC1 F000 0900H F000 09FFH Table 21 9 Registers Overview MSC Kernel Registers Register Short Name Register Long Name Offset Address1 Descriptio n see ID Module Identif...

Page 1254: ... 2CH Page 21 48 UD0 Upstream Data Register 0 30H Page 21 60 UD1 Upstream Data Register 1 34H UD2 Upstream Data Register 2 38H UD3 Upstream Data Register 3 3CH ICR Interrupt Control Register 40H Page 21 49 ISR Interrupt Status Register 44H Page 21 52 ISC Interrupt Set Clear Register 48H Page 21 54 OCR Output Control Register 4CH Page 21 56 1 The absolute register address is calculated as follows Mo...

Page 1255: ...fication Register 008H Reset Value 0028 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines t...

Page 1256: ...h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 P CTR URR UFT r rw rw rw Field Bits Type Description UFT 0 rw Upstream Channel Frame Type This bit determines the frame type used by the upstream channel for data reception 0B 12 bit upstream frame selected 1B 16 bit upstream frame selected with 4 bit address field URR 3 1 rw Upstream Channel Receiving Rate This bit field determines the baud rate for the u...

Page 1257: ...e is selected A parity bit is set on an odd number of 1s in the serial address data stream 1B Odd parity mode is selected A parity bit is set on an even number of 1s in the serial address data stream UC 20 16 rh Upstream Counter This bit field indicates the content of the upstream counter that counts the bits during upstream channel reception 0 15 5 31 21 r Reserved Read as 0 should be written wit...

Page 1258: ... SEL H EN SEL L NDBH NDBL DP CP TM rh rw rw rw rw rh rh rw Field Bits Type Description TM 0 rw Transmission Mode This bit selects the transmission mode of the downstream channel 0B Triggered Mode selected 1B Data Repetition Mode selected CP 1 rh Command Pending This bit is set when the downstream command register DC is written CP is cleared when the first bit of the related command frame is sent o...

Page 1259: ...ed out on SO during a data frame 00000B No SRH bit shifted no selection bit is generated the SRH active phase is completely skipped 00001B SRH 0 shifted 00010B SRH 1 0 shifted B 01111B SRH 14 0 shifted 10000B SRH 15 0 shifted Other bit combinations are reserved do not use these bit combinations ENSELL 13 rw Enable SRL Active Phase Selection Bit This bit determines whether a low level selection bit...

Page 1260: ...es how many bits of the SRL SRH shift registers are shifted out during transmission of a command frame 000000B No bit shifted 000001B SRL 0 shifted 000010B SRL 1 0 shifted 000011B SRL 2 0 shifted B 010000B SRL 15 0 shifted 010001B SRL 15 0 and SRH 0 shifted 010010B SRL 15 0 and SRH 1 0 shifted B 011111B SRL 15 0 and SRH 14 0 shifted 100000B SRL 15 0 and SRH 15 0 shifted Other bit combinations are ...

Page 1261: ...ode this bit field indicates the count of passive time frames that are currently transmitted In Triggered Mode PFC remains at 0000B 0000B Data frame is transmitted 0001B First passive time frame is transmitted 0010B Second passive time frame is transmitted B 1111B Fifteenth passive time frame is transmitted NPTF 11 8 rw Number Of Passive Time Frames This bit field indicates the number of passive t...

Page 1262: ...clock elapsed B 7FH 127 shift clocks elapsed The DC is reset at the end of a downstream frame DFA 24 rh Data Frame Active This bit indicates if a data frame is currently sent out 0B No data frame is currently sent out 1B A data frame is currently sent out CFA 25 rh Command Frame Active This bit indicates if a command frame is currently sent out 0B No command frame is currently sent out 1B A comman...

Page 1263: ... 22 21 20 19 18 17 16 SL15 SL14 SL13 SL12 SL11 SL10 SL9 SL8 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 rw rw rw rw rw rw rw rw Field Bits Type Description SLx x 0 15 2 x 1 2 x rw Select Source for SRL SLx determines which data source is used for the shift register bit SRL x during data frame transmission 00B SRL x is taken from data register DD DD...

Page 1264: ...24 23 22 21 20 19 18 17 16 SH15 SH14 SH13 SH12 SH11 SH10 SH9 SH8 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SH7 SH6 SH5 SH4 SH3 SH2 SH1 SH0 rw rw rw rw rw rw rw rw Field Bits Type Description SHx x 0 15 2 x 1 2 x rw Select Source for SRH SHx determines which data source is used for the shift register bit SRL x during data frame transmission 00B SRL x is taken from data register ...

Page 1265: ...rw rw rw rw rw rw rw rw Field Bits Type Description ENLx x 0 15 x rw Emergency Stop Enable for Bit x in SRL This bit enables the emergency stop feature selectively for each SRL bit If the emergency stop condition is met and enabled ENLx 1 the SRL x bit is of the data register DD DDL x is used for the shift register load operation 0B Emergency stop feature for bit SRL x is disabled 1B The emergency...

Page 1266: ...lects the service request output line SRn n 3 0 for the data frame interrupt 00B Service request output SR0 selected 01B Service request output SR1 selected 10B Service request output SR2 selected 11B Service request output SR3 selected EDIE 3 2 rw Data Frame Interrupt Enable This bit field determines the enable conditions for the data frame interrupt 00B Interrupt generation disabled 01B An inter...

Page 1267: ... TFIP 9 8 rw Time Frame Interrupt Pointer TFIP selects the service request output line SRn n 3 0 for the time frame interrupt 00B Service request output SR0 selected 01B Service request output SR1 selected 10B Service request output SR2 selected 11B Service request output SR3 selected TFIE 11 rw Time Frame Interrupt Enable This bit enables the time frame interrupt 0B Interrupt generation disabled ...

Page 1268: ...interrupt 00B Interrupt generation disabled 01B An interrupt is generated when data is received and written into the upstream data registers UDx x 0 3 10B An interrupt is generated as with RDIE 01B but only if the received data is not equal to 00H 11B An interrupt is generated when data is received and written into register UD3 0 6 10 31 16 r Reserved Read as 0 should be written with 0 Field Bits ...

Page 1269: ...n a downstream channel data frame interrupt is generated DEDI can be set or cleared by software when writing to register ISC with the appropriate bits ISC SDEDI or ISC CDEDI set DECI 1 rh Command Frame Interrupt Flag This flag is always set by hardware when a downstream channel command frame interrupt is generated whether or not it is enabled DECI can be set or cleared by software when writing to ...

Page 1270: ...rrupt Flag This flag is always set by hardware when an upstream channel receive data interrupt is generated whether or not it is enabled URDI can be set or cleared by software when writing to register ISC with the appropriate bits SURDI or CURDI set 0 31 4 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1271: ...DEDI r w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 C DDIS C CP C DP C URDI C DTFI C DECI C DEDI r w w w w w w w Field Bits Type Description CDEDI 0 w Clear DEDI Flag 0B No operation 1B Bit ISR DEDI is cleared CDECI 1 w Clear DECI Flag 0B No operation 1B Bit ISR DECI is cleared CDTFI 2 w Clear DTFI Flag 0B No operation 1B Bit ISR DTFI is cleared CURDI 3 w Clear URDI Flag 0B No operation 1...

Page 1272: ...g 0B No operation 1B Bit ISR DEDI is set SDECI 17 w Set DECI Flag 0B No operation 1B Bit ISR DECI is set SDTFI 18 w Set DTFI Flag 0B No operation 1B Bit ISR DTFI is set SURDI 19 w Set URDI Flag 0B No operation 1B Bit ISR URDI is set SDP 20 w Set DP Bit 0B No effect 1B Bit DSC DP is set SCP 21 w Set CP Flag 0B No operation 1B Bit DSC CP is set SDDIS 22 w Set DSDIS Flag 0B No operation 1B Bit DSC DS...

Page 1273: ...ignal has inverted FCL signal polarity 1B FCLP signal has inverted FCL signal polarity FCLN and FCL signal polarities are identical SLP 1 rw SOP Line Polarity 0B SOP and SO signal polarity is identical SON signal has inverted SO signal polarity 1B SOP signal has inverted SO signal polarity SON and SO signal polarities are identical CSLP 2 rw Chip Selection Lines Polarity 0B EN 3 0 and ENL ENH ENC ...

Page 1274: ...ENL 01B EN1 line is selected for ENL 10B EN2 line is selected for ENL 11B EN3 line is selected for ENL CSH 12 11 rw Chip Enable Selection for ENH This bit field selects the chip enable output ENx that becomes active during the SRL active phase ENH 1 of a data frame The active level of ENx is defined by bit CSLP 00B EN0 line is selected for ENH 01B EN1 line is selected for ENH 10B EN2 line is selec...

Page 1275: ...t SDI of the upstream channel 000B SDI 0 input is selected as SDI 001B SDI 1 input is selected as SDI 010B SDI 2 input is selected as SDI 011B SDI 3 input is selected as SDI 100B SDI 4 input is selected as SDI 101B SDI 5 input is selected as SDI 110B SDI 6 input is selected as SDI 111B SDI 7 input is selected as SDI 0 7 4 15 31 19 r Reserved Read as 0 should be written with 0 Field Bits Type Descr...

Page 1276: ...ata for SRL Shift Register Contains the data bits to be transmitted during the SRL active phase of a data frame DDH 31 16 rw Downstream Data for SRH Shift Register Contains the data bits to be transmitted during the SRH active phase of a data frame DC Downstream Command Register 20H Reset Value 0000 0000H 31 16 15 0 DCH DCL rw rw Field Bits Type Description DCL 15 0 rw Downstream Command for SRL S...

Page 1277: ... contains the 8 bit receive data V 16 rh Valid Bit This bit is set by hardware when the received data is written to UDx Writing bit C 1 clears V If hardware setting and software clearing of the valid bit occur simultaneously bit V will be cleared P 17 rh Parity Bit This flag contains the parity bit that has been received with the data frame C 18 w Clear Bit 0B No operation 1B Bit V is cleared Bit ...

Page 1278: ... 61 V2 0 2007 07 MSC V2 0 PERR 22 rh Parity Error This bit indicates if a start bit error parity error or stop bit error occurred during frame reception 0B No error detected 1B Error detected 0 15 8 31 23 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1279: ...h the DMA controller Outputs of the GPTA0 GPTA1 and LTCA2 modules are connected to the alternate input buses ALTINL ALTINH The emergency stop output from the SCU controls the corresponding inputs of both MSC modules The serial data and clock outputs of the downstream channels of each MSC module are connected to dedicated LVDS differential output drivers After a reset operation all LVDS outputs are...

Page 1280: ...DMA P5 5 SDI0 SON0 SOP0A P9 4 EN03 P9 5 EN02 P9 6 EN01 P5 4 EN00 FCLN0 FCLP0A P9 8 FCLP0B P9 7 SOP0B SR 3 2 from GPTA from SCU MSC1 Module Kernel MCA05823 Port 5 Port 9 Control FCLN Clock Control Address Decoder Interrupt Control fMSC1 fCLC1 Downstream Channel Upstr Channel FCLP EN0 EN1 EN2 SON SOP SDI 0 1 SR 1 0 ALTINL 15 0 ALTINH 15 0 To DMA SR 3 2 from GPTA P5 7 SDI1 SON1 SOP1A P9 0 EN12 P9 1 E...

Page 1281: ...hich are required for programming of MSC0 and MSC1 see also Figure 21 28 for the module kernel specific registers These registers are described in the following sections Figure 21 30 MSC Implementation specific Special Function Registers MCA05824 MSC0_SRCx Interrupt Registers P5_IOCR4 Port Registers Clock Control Registers MSC0_CLC x 0 1 MSC1_CLC MSC0_FDR MSC1_FDR MSC1_SRCx P5_PDR P9_IOCR0 P9_IOCR...

Page 1282: ...of the serial upstream and downstream channel The fractional divider registers MSC0_FDR and MSC1_FDR control the frequency of fMSC0 and fMSC1 and make it possible to enable disable it independently of fCLC0 and fCLC1 For module test purposes only the service request output SR15 of the MultiCAN controller makes it possible to synchronize the fractional divider clock generation of both MSC modules t...

Page 1283: ...annel is derived from the module clock fMSCx by a programmable clock divider selected by bit field MSCx_USR URR see also Equation 21 2 on Page 21 25 The divide factor DF can be at minimum 4 and at maximum 256 21 7 21 8 Equation 21 3 Equation 21 5 and Equation 21 7 are valid for normal divider mode MSCx FDR DM 01B Equation 21 4 Equation 21 6 and Equation 21 8 are valid for fractional divider mode M...

Page 1284: ...lue 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used ...

Page 1285: ...00 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS CLK EN HW SUS REQ SUS ACK 0 RESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines th...

Page 1286: ...ty are described in section Fractional Divider Operation on Page 3 29 of the TC1796 User s Manual System Units part Volume 1 ENHW 30 rw Enable Hardware Clock Control Controls operation of ECEN input and DISCLK bit DISCLK 31 rwh Disable Clock Hardware controlled disable for fOUT signal 0 10 27 26 rw Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1287: ...ntrolled by the Port 5 and Port 9 input output control registers Table 21 10 shows in an overview how bits and bit fields must be programmed for the required I O functionality of the MSC I O lines Table 21 10 MSC0 and MSC1 I O Line Selection and Setup Module Port Lines Input Output Control Register Bits1 1 Possible Px bit field combinations see Table 21 11 I O MSC0 P5 4 EN00 P5_IOCR4 PC4 1X11B Out...

Page 1288: ...trol for P5 6 EN10 Port input output control for P5 7 SDI1 1 Coding of bit field see Table 21 11 Shaded bits and bit fields are don t care for MSC I O port control P9_IOCR0 Port 9 Input Output Control Register 0 10H Reset Value 2020 2020H 31 28 23 20 15 12 7 4 0 PC3 0 PC2 0 PC1 0 PC0 0 rw r rw r rw r rw r Field Bits Type Description PC0 PC1 PC2 PC3 7 4 15 12 23 20 31 28 rw Port Input Output Contro...

Page 1289: ...t control for P9 4 EN03 Port input output control for P9 5 EN02 Port input output control for P9 6 EN01 Port input output control for P9 7 SOP0B 1 Coding of bit field see Table 21 11 Shaded bits and bit fields are don t care for MSC I O port control P9_IOCR8 Port 9 Input Output Control Register 8 18H Reset Value 0000 0020H 31 7 4 0 0 PC8 0 r rw r Field Bits Type Description PC8 7 4 rw Port Input O...

Page 1290: ...x 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function 0X00B Input No pull device connected 0X01B Pull down device connected 0X10B 1 1 This bit field value is default after reset Pull up device connected 0X11B No pull device connected 1011B Output Push pull Output function ALT3 1111B Open drain Output function ALT3 ...

Page 1291: ... PDMSC0 26 24 rw Pad Driver Mode for P5 4 EN001 1 Coding of bit field see Table 21 12 Shaded bits and bit fields are don t care for MSC I O port control PDMSC1 30 28 rw Pad Driver Mode for P5 6 EN101 P9_PDR Port 9 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 22 20 18 16 2 0 0 PD MSC1 0 PD MSC0 0 PD0 r rw r rw r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P9 8 FCLP0B1 1 ...

Page 1292: ... Mode Selection Class A2 Pads PDx Bit Field Driver Strength Signal Transitions 000B Strong driver Sharp edge1 1 In strong driver mode the output driver characteristics of class A2 pads can be additionally controlled by the temperature compensation logic 001B Medium edge1 010B Soft edge1 011B Weak driver 100B Medium driver 101B 110B 111B Weak driver ...

Page 1293: ...its User s Manual Volume 1 21 3 5 2 ALTINH and ALTINL Connections In the TC1796 output lines of GPTA0 GPTA1 and LTCA2 are connected to ALTINH and ALTINL inputs of the MSC0 MSC1 downstream channels as shown in Figure 21 32 The setting of the GPTA to MSC multiplexer determines which output of the three GPTA sub modules is connected to a specific ALTINL ALTINH line Details about the functionality of ...

Page 1294: ... Module Service Request Line Connected To Description MSC0 SR0 MSC0_SRC0 MSC0 Service Request Node 0 SR1 MSC0_SRC1 MSC0 Service Request Node 1 SR2 CH06_REQI2 DMA Channel 06 Request Input 2 SR3 CH07_REQI2 CH14_REQI5 CH16_REQI6 DMA Channel 07 Request Input 2 DMA Channel 14 Request Input 5 DMA Channel 16 Request Input 6 MSC1 SR0 MSC1_SRC0 MSC1 Service Request Node 0 SR1 MSC1_SRC1 MSC1 Service Request...

Page 1295: ...est control registers are described on Page 14 3 of the TC1796 User s Manual System Units part Volume 1 SRC1 Service Request Control Register 1 F8H Reset Value 0000 0000H SRC0 Service Request Control Register 0 FCH Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Des...

Page 1296: ...le in the TC1796 see Page 22 14 Functional description of the MultiCAN Kernel see Page 22 18 MultiCAN Kernel register description see Page 22 58 Functional description of the TTCAN extension see Page 22 114 TTCAN extension register description see Page 22 154 TC1796 implementation specific details port connections and control interrupt control address decoding clock control see Page 22 199 Note Th...

Page 1297: ...message The identifier indicates the contents of the message and its priority The lower the binary value of the identifier the higher is the priority of the message For bus arbitration CSMA CD with NDA Carrier Sense Multiple Access Collision Detection with Non Destructive Arbitration is used If bus node A attempts to transmit a message across the network it first checks that the bus is in the idle...

Page 1298: ...f Frame bit SOF dominant level for hard synchronization of all nodes The SOF is followed by the Arbitration Field consisting of 12 bits the 11 bit Identifier reflecting the contents and priority of the message and the RTR Remote Transmission Request bit With RTR at dominant level the frame is marked as Data Frame With RTR at recessive level the frame is defined as a Remote Frame The next field is ...

Page 1299: ...If after the Inter Frame Space no other nodes attempt to transmit the bus remains in idle state with a recessive level Figure 22 1 CAN Data Frame 1 1 Bus Idle Dominant Level Recessive Level Bus Idle Bus Idle Dominant Level Recessive Level MCT05827 Standard Data Frame ACK Delimiter ACK Slot CRC Delimiter CRC Sequence Data Field Reserved D IDE Bit D RTR Bit D Identifier 4 1 1 1 1 1 1 15 Start of Fra...

Page 1300: ...IDE bit Therefore the SRR bit in an Extended CAN frame is recessive to allow the assertion of a dominant RTR bit by a node that is sending a Standard CAN Remote Frame The SRR and IDE bits are followed by the remaining 18 bits of the extended identifier and the RTR bit Control field and frame termination is identical to the Standard Data Frame 22 1 2 2 Remote Frames Normally data transmission is pe...

Page 1301: ... Recessive Level MCT05828 11 Standard Remote Frame ACK Delimiter ACK Slot CRC Delimiter CRC Sequence Data Length Code Reserved D IDE Bit D RTR Bit D Identifier 4 1 1 1 1 1 1 15 Start of Frame Control Field Arbitration Field 12 bit 1 7 3 Inter Frame Space End of Frame EOF Acknowledge Field CRC Field 11 4 1 1 1 1 1 15 1 7 3 18 2 1 Extended Remote Frame SRR Bit R IDE Bit R 29 bit Identfier Arbitratio...

Page 1302: ... field completes the Error Frame After completion of the Error Frame bus activity returns to normal and the interrupted node attempts to re send the aborted message If an error passive node detects a bus error the node transmits an error passive flag followed again by the Error Delimiter field The error passive flag consists of six consecutive recessive bits and therefore the Error Frame for an er...

Page 1303: ... delays are caused by signal propagation delay on the bus line and through the electronic interface circuits of the bus nodes The Phase Segments 1 and 2 PHASE_SEG1 PHASE_SEG2 are used to compensate for edge phase errors These segments can be lengthened or shortened by re synchronization PHASE_SEG2 is reserved for calculation of the subsequent bit level and is 2 tQ At the sample point the bus level...

Page 1304: ...Error has occurred and an Error Frame is generated The message is repeated Bit Error A Bit Error occurs if a a transmitter sends a dominant bit and detects a recessive bit or b if the transmitter sends a recessive bit and detects a dominant bit when monitoring the actual bus level and comparing it to the just transmitted bit In case b no error occurs during the Arbitration Field ID RTR IDE and the...

Page 1305: ...he host CPU load is quite high when using Basic CAN modules The main advantage of Basic CAN is a reduced chip size leading to low costs of these devices Full CAN devices this is the case for the MultiCAN controller as implemented in TC1796 manage the whole bus protocol in hardware including the acceptance filtering and message management Full CAN devices contain message objects that handle autonom...

Page 1306: ... reference makes it possible to synchronize the activities of all CAN nodes Each CAN node has its own local time represented by a counter that is incremented with each network time unit NTU The NTU is derived from the node s local clock and local Time Unit Ratio TUR In TTCAN synchronization is achieved by a periodic transmission of a reference message This reference message transmitted by a time m...

Page 1307: ...nsmitting reference message The other CAN nodes in the network operate as time slaves that calculate their local time offset to the global time by comparing their local time with the received global time To compensate for slightly different clock drifts in the CAN nodes and to provide a consistent view of the global time the nodes can perform a drift compensation operation They compare the length ...

Page 1308: ...is the time master in the TTCAN network The reference message includes the time master s by definition correct global time value for frame synchronization All nodes take a snap shot of their time values at the SOF bit sample point of the received reference message After reference message reception each node can calculate its local offset that indicates the difference between the master global time...

Page 1309: ...ndependent CAN nodes representing four serial communication interfaces Figure 22 6 Overview of the MultiCAN Module with Time Triggered Extension MultiCAN Module Kernel MCA05832 Interrupt Control fCAN Port Control CAN Node 1 CAN Control Message Object Buffer 128 Objects Timing Control and Synchronization Scheduler Schedule Timing Data Memory Time Triggered Extension TTCAN CAN Node 0 CAN Node 2 Link...

Page 1310: ... belonging to this message object list A powerful command driven list controller performs all message object list operations The bit timings for the CAN nodes are derived from the module timer clock fCAN and are programmable up to a data rate of 1 Mbit s External bus transceivers are connected to a CAN node via a pair of receive and transmit pins Features Compliant with ISO 11898 CAN functionality...

Page 1311: ...mber of gateways can be defined Advanced data management The message objects are organized in double chained lists List reorganizations can be performed at any time even during full operation of the CAN nodes A powerful command driven list controller manages the organization of the list structure and ensures consistency of the list Message FIFOs are based on the list structure and can easily be sc...

Page 1312: ...te in safety critical applications The new features allow for deterministic behavior of a CAN network and the synchronization of networks Global time information is available The time triggered extension is based on a scheduler mechanism with a timing control unit and a dedicated timing data part TTCAN Features Full support of basic cycle and system matrix functionality Support of reference messag...

Page 1313: ...standard This includes conversion between the serial data stream and the input output registers Bit Timing Unit The Bit Timing Unit determines the length of a bit time and the location of the sample point according to the user settings taking into account propagation delays and phase shift errors The Bit Timing Unit also performs re synchronization MCB05833 CAN Bus 0 Message Controller CAN Node 0 ...

Page 1314: ...toring of a received CAN frame Transmit acceptance filtering to determine the message object to be transmitted first individually for each CAN node Transfer contents between message objects and the CAN nodes taking into account the status control bits of the message objects Handling of the FIFO buffering and gateway functionality Aggregation of message pending notification bits List Controller The...

Page 1315: ...generate fCAN used for the bit timing calculation the generation of the NTU and the local time of the TTCAN part The frequency of fCAN is identical for all CAN nodes The TTCAN scheduler and the register file operate with the module control clock fCLC See also Module Clock Generation on Page 22 201 The output clock fCAN of the Fractional Divider is based on the system clock fCLC but only every n th...

Page 1316: ...le 22 1 Minimum Operating Frequencies MHz Number of Allocated Message Objects MO1 with or without TTCAN Functionality 1 Only those message objects that are allocated to a CAN node must be taken into account The unallocated message objects have no influence on the minimum operating frequency with1CAN Node Active with2CAN Nodes Active with3CAN Nodes Active with4CAN Nodes Active 16 MO without TTCAN 1...

Page 1317: ...s a dominant level A reset operation must be executed to leave Hard Suspend Mode The current action is finished Soft Suspend Mode The module clock fCLC keeps running Module functions are stopped automatically after internal actions have been finished for example after a CAN frame has been sent out The end of the internal actions is indicated to the fractional divider by a suspend mode acknowledged...

Page 1318: ... Frames are generated If CAN Analyze Mode is enabled Remote Frames are not responded by the corresponding Data Frame and Data Frames cannot be transmitted by setting the transmit request bit MOSTATn TXRQ Receive interrupts are generated In CAN Analyze Mode if enabled for all error free received frames The node specific interrupt configuration is also defined by the Node Control Logic via the NCRx ...

Page 1319: ... in the transmitter output driver on the CAN bus line and in the transceiver circuit For a working collision detection mechanism TProp must be two times the sum of all propagation delay quantities rounded up to a multiple of tq The phase buffer segments 1 and 2 Tb1 Tb2 before and after the signal sample point are used to compensate for a mismatch between transmitter and receiver clock phase detect...

Page 1320: ...ion jump width A valid CAN bit timing must be written to the CAN Node Bit Timing Register NBTR before clearing the INIT bit in the Node Control Register i e before enabling the operation of the CAN node The Node Bit Timing Register may be written only if bit CCE Configuration Change Enable is set in the corresponding Node Control Register 22 3 5 2 Bitstream Processor Based on the message objects i...

Page 1321: ...eceive Error Counter REC and the Transmit Error Counter TEC bit fields of the Node x Error Counter Register NECNTx see Page 22 86 are incremented and decremented by commands from the Bitstream Processor If the Bitstream Processor itself detects an error while a transmit operation is running the Transmit Error Counter is incremented by 8 An increment of 1 is used when the error condition was report...

Page 1322: ...he CFC bit field of the NFCRx register After the successful transfer of the frame the captured value is copied to the CFCVAL bit field of the MOIPRn register of the message object involved in the transfer Bit Timing Mode Used for baud rate detection and analysis of the bit timing see Page 22 35 22 3 5 5 CAN Node Interrupts Each CAN node has four hardware triggered interrupt request types that are ...

Page 1323: ...1 CAN Node Interrupts MCA05837 TRIE TRINP TXOK RXOK Receive Transmit Correct Message Object Transfer LECIE LECINP LEC CAN Error EWRN BOFF ALINP ALIE ALERT LLE LOE List Length Error List Object Error CFCIE CFCINP CFCOV Frame Counter Overflow Event NSRx NSRx NCRx NIPRx NIPRx NIPRx NIPRx NSRx NSRx NCRx NCRx NSRx NSRx NSRx NFCRx NFCRx 1 3 1 ...

Page 1324: ...object 5 in the example and bit field END points to the last element in the list object 3 in the example The number of elements in the list is indicated by bit field SIZE of the List Register SIZE number of list elements 1 thus SIZE 2 for the 3 elements in the example The EMPTY bit of the List Register indicates whether or not a list is empty EMPTY 0 in the example because list 2 is not empty Each...

Page 1325: ... allocation of the message objects caused by reset the list of all unallocated message objects is ordered by message number predecessor of message object n is object n 1 successor of object n is object n 1 22 3 6 3 Connection to the CAN Nodes Each CAN node is linked to one unique list of message objects A CAN node performs message transfers only with the message objects that are allocated to the l...

Page 1326: ...dify the list structure result in a consistent list structure 2 Present maximum ease of use and flexibility to the user The list controller and the associated command panel allows the programmer to concentrate on the final properties of the list which are characterized by the allocation of message objects to a CAN node and the ordering relation between objects that are allocated to the same list T...

Page 1327: ... CAN RAM is automatically initialized after reset by the list controller in order to ensure correct list pointers in each message object The end of this CAN RAM initialization is indicated by bit PANCTR BUSY becoming inactive In case of a dynamic allocation command that takes an element from the list of unallocated objects the PANCTR RBUSY bit is also set along with the BUSY bit Table 22 2 Panel C...

Page 1328: ...ister resource located inside the RAM delays the ongoing allocation process by one access cycle As soon as the command is finished the BUSY flag becomes inactive BUSY 0 and write accesses to the Panel Control Register are enabled again Also the No Operation command code is automatically written to the PANCTR PANCMD field A new command may be started any time when BUSY 0 All fields of the Panel Con...

Page 1329: ...lity is available but no transmit request will be executed 22 3 7 2 Loop Back Mode The MultiCAN module provides a Loop Back Mode to enable an in system test of the MultiCAN module as well as the development of CAN driver software without access to an external CAN bus The loop back feature consists of an internal CAN bus inside the MultiCAN module and a bus select switch for each CAN node see Figur...

Page 1330: ...e timing of the CAN network Bit timing analysis for CAN node x is selected when bit field NFCRx CFMOD 10B Bit timing analysis does not affect the operation of the CAN node The bit timing measurement results are written into the NFCRx CFC bit field Whenever NFCRx CFC is updated in bit timing analysis mode bit NFCRx CFCOV is also set to indicate the CFC update event If NFCRx CFCIE is set an interrup...

Page 1331: ... monitored if NFCRx CFSEL 010B The time between the first dominant edge and the sample point is measured and stored in the NFCRx CFC bit field The bit timing synchronization offset may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points Synchronization analysis can be used for example fo...

Page 1332: ...e is don t care In this case message objects with standard and extended frames are accepted The identifier of the received frame matches the identifier stored in the Arbitration Register of the message object as qualified by the acceptance mask in the MOAMRn register This means that each bit of the received message object identifier is equal to the bit field MOARn ID except those bits for which th...

Page 1333: ...XEN1 are set A priority scheme determines which one of all qualifying message objects is transmitted first It is assumed that message object a MOa and message object b MOb are two message objects qualified for transmission MOa is a list successor of MOb For both message objects CAN messages CANa and CANb are defined identifier IDE and RTR are taken from the message specific bit fields and bits MOA...

Page 1334: ... CAN operation without TTCAN functionality as well as for arbitration windows within a TTCAN system matrix Figure 22 16 Effective Transmit Request of Message Object Transmission Acceptance Filtering in TTCAN Exclusive Windows In exclusive windows of a TTCAN transmit acceptance filtering is performed as described in the previous section but with the exception that only message objects with MOARn PR...

Page 1335: ...terrupt output lines see Figure 22 17 A receive interrupt occurs also after a frame storage event that has been induced by a FIFO or a gateway action The status bits TXPND and RXPND in the Message Object n Status Register are always set after a successful transmission reception whether or not the respective message interrupt is enabled A third FIFO full interrupt condition of a message object is p...

Page 1336: ...2 0 Figure 22 17 Message Interrupt Request Routing MCA05843 TXIE TXINP TXPND Message n Received Message n Transmitted RXINP MOSTATn MOFCRn MOIPRn MOIPRn Message n FIFO full OVIE RXIE RXPND MMC 1 0001B 0010B 1 MMC 0001B Message object n is a Receive FIFO Base Object MMC 0010B Message object n is a Transmit FIFO Base Object ...

Page 1337: ... 22 18 Message Pending Bit Allocation The location of a pending bit is defined by two demultiplexers selecting the number k of the MSPNDk registers 3 bit demux and the bit location within the corresponding MSPNDk register 5 bit demux 255 224 MCA05844 7 6 5 4 3 2 1 0 MPN Message Object n Interrupt Pointer Register MOIPRn 15 0 3 2 1 0 TXINP 3 2 1 0 RXINP 15 D E M U X 0 7 D E M U X 0 31 31 0 4 3 2 1 ...

Page 1338: ...vent the upper 3 bits of TXINP determine the number k of a Message Pending Register MSPNDk in which the pending bit will be set At a receive event the upper 3 bits of RXINP determine the number k The bit position 0 31 in MSPNDk for the pending bit to be set is selected by the lowest bit of TXINP or RXINP selects between low and high half word of MSPNDk and the four least significant bits of MPN Ge...

Page 1339: ... object wins receive acceptance filtering 2 The CPU clears MSGVAL to re configure the message object 3 The CPU sets MSGVAL again after re configuration 4 The end of the received frame is reached As MSGVAL is set the received data is stored in the message object a message interrupt request is generated gateway and FIFO actions are processed etc After the re configuration of the message object after...

Page 1340: ...o longer wins receive acceptance filtering RXUPD NEWDAT and MSGLST An ongoing frame storage process is indicated by the RXUPD Receive Updating flag in the MOSTATn register RXUPD is set with the start and cleared with the end of a message object update which consists of frame storage as well as flag updates After storing the received frame identifier IDE bit DLC and for Data Frames also the Data Fi...

Page 1341: ...t wins acc filtering yes yes no no CAN rec successful MSGVAL RTSEL 1 MSGVAL 1 DIR 1 NEWDAT 1 RXIE 1 RTSEL 1 RXUPD 1 Copy frame to message object TXRQ 1 in this or in foreign objects Copy frame to message object RXUPD 1 MSGLST 1 yes NEWDAT 1 RXUPD 0 RXPND 1 no no yes yes no yes MSGLST 1 no yes 1 2 3 4 no Time Milestones Get data from gateway FIFO source Start receiving CAN frame Done ...

Page 1342: ...ve different semantics Table 22 3 Message Transmission Bit Definitions Bit Description MSGVAL Message Valid This is the main switch bit of the message object TXRQ Transmit Request This is the standard transmit request bit This bit must be set whenever a message object should be transmitted TXRQ is cleared by hardware at the end of a successful transmission except when there is new data indicated b...

Page 1343: ...EWDAT clearing TXRQ time stamp update message interrup etc within the old context of the object can occur after the message object becomes valid again but within a new context NEWDAT When the contents of a message object have been transferred to the internal transmit buffer of the CAN node bit MOSTATn NEWDAT New Data is cleared by hardware to indicate that the transmit message object data is no lo...

Page 1344: ...age Object yes MCA05846 RTSEL 1 NEWDAT 1 TXIE 1 RTSEL 1 NEWDAT 0 no yes 1 2 3 Copy Message to internal transmit buffer MSGVAL TXRQ TXEN0 TXEN1 1 continuously valid Request transmission of internal buffer on CAN bus yes Transmission successful yes yes MSGVAL RTSEL 1 yes TXRQ 0 Issue interrupt no no no no no Time Milestones Done Object wins transmit acc filtering ...

Page 1345: ...ived message indicated by MSGLST 1 If SDT is set Single Data Transfer Mode activated bit MSGVAL of the message object is automatically cleared by hardware after the storage of a received Data Frame This prevents the reception of further messages After the reception of a Remote Frame bit MSGVAL is not automatically cleared Message Transmission When a message object receives a series of multiple rem...

Page 1346: ... object does not need be allocated to the same list as the slave objects Only the slave object must be allocated to a common list as they are chained together Several pointers BOT CUR and TOP that are located in the Message Object n FIFO Gateway Pointer Register MOFGPRn link the base object to the slave objects regardless whether the base object is allocated to the same or to another list than the...

Page 1347: ...EL makes it possible to detect the end of a predefined message transfer series or to issue a warning interrupt when the FIFO becomes full Figure 22 21 FIFO Structure with FIFO Base Object and n FIFO Slave Objects MCA05847 Slave Object fi PPREV f i 1 PNEXT f i 1 Slave Object fn PPREV f n 1 PNEXT Slave Object f2 PPREV f1 PNEXT f3 Slave Object f1 PPREV PNEXT f2 Base Object PPREV PNEXT TOP fn CUR fi B...

Page 1348: ...ave object is ignored For the slave object no acceptance filtering takes place that checks the received frame for a match with the identifier IDE bit and DIR bit With the reception of a CAN frame the current pointer CUR of the base object is set to the number of the next message object in the FIFO structure This message object will then be used to store the next incoming message If bit field MOFCR...

Page 1349: ...e base object must be tagged valid MSGVAL 1 first Before a Transmit FIFO becomes de installed during operation its slave objects must be tagged invalid MSGVAL 0 The Transmit FIFO uses the TXEN1 bit in the Message Object Control Register of all FIFO elements to select the actual message for transmission Transmit acceptance filtering evaluates TXEN1 for each message object and a message object can w...

Page 1350: ...ength code MOFCRs DLC is copied from the gateway source object to the gateway destination object 2 If bit MOFCRs IDC is set the identifier MOARs ID and the identifier extension MOARs IDE are copied from the gateway source object to the gateway destination object 3 If bit MOFCRs DATC is set the data bytes stored in the two data registers MODATALs and MODATAHs are copied from the gateway source obje...

Page 1351: ...as well as for the reception of Remote Frames source object is transmit object Figure 22 22 Gateway Transfer from Source to Destination MCA05848 Copy if IDCSource 1 Pointer to Destination Message Object Destination CAN Bus Source CAN Bus Set CUR Identifier IDE DLC Data Source Message Object MMC 0100B Copy if DLCCSource 1 Copy if DATCSource 1 Set if GDFSSource 1 Identifier IDE DLC Data TXRQ NEWDAT ...

Page 1352: ...gateway destination object there are two capabilities to handle remote requests that appear on the destination side assuming that the source object is a receive object and the destination is a transmit object i e DIRsource 0 and DIRdestination 1 FRREN 0 in the Gateway Destination Object 1 A Remote Frame is received by gateway destination object 2 TXRQ is set automatically in the gateway destinatio...

Page 1353: ...isters Node Registers for each CAN node x Message Object Registers for each message object n Figure 22 23 MultiCAN Kernel Registers The complete and detailed address map of the MultiCAN module is described in Table 18 24 on Page 18 65 of the TC1796 User s Manual System Units part Volume 1 Table 22 4 Registers Address Space MultiCAN Kernel Registers Module Base Address End Address Note CAN F000 400...

Page 1354: ...ister 204H x 100H Page 22 77 NIPRx Node x Interrupt Pointer Reg 208H x 100H Page 22 81 NPCRx Node x Port Control Register 20CH x 100H Page 22 83 NBTRx Node x Bit Timing Register 210H x 100H Page 22 84 NECNTx Node x Error Counter Register 214H x 100H Page 22 86 NFCRx Node x Frame Counter Register 218H x 100H Page 22 87 MOFCRn Message Object n Function Control Register 400H n 20H Page 22 101 MOFGPRn...

Page 1355: ...H Node 0 Registers Node x Control Register Node x Status Register NO Node x 3 0 Node x Interrupt Ptr Reg Node x Port Control Reg Node x Bit Timing Reg Node x Error Counter Reg Node x Frame Counter Reg Node 1 Registers Node 2 Registers Node 3 Registers NOBASE 00H Message Object Registers MO n Function Control Reg MO n FIFO Gtw Ptr Reg MO Message Object n 127 0 MO n Interrupt Ptr Reg MO n Accept Mas...

Page 1356: ...odule Identification Register 008H Reset Value 002B C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Number Value This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This...

Page 1357: ...C4H Reset Value 0000 0301H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PANAR2 PANAR1 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RBU SY BUS Y PANCMD r rh rh rwh Field Bits Type Description PANCMD 7 0 rwh Panel Command This bit field is used to start a new command by writing a panel command code into it At the end of a panel command the NOP no operation command code is automatically written...

Page 1358: ...mand Description 00H No Operation Writing 00H to PANCMD has no effect No new command is started 01H Result Bit 7 ERR Bit 6 0 undefined Initialize Lists Run the initialization sequence to reset the CTRL and LIST fields of all message objects List registers LIST 7 0 are set to their reset values This results in the de allocation of all message objects The initialization command requires that bits NC...

Page 1359: ...te Allocate the first message object of the list of unallocated objects to the selected list The message object is appended to the end of the list The message number of the message object is returned in PANAR1 An ERR bit bit 7 of PANAR2 reports the success of the operation 0B Success 1B The operation has not been performed because the list of unallocated elements was empty 04H Argument Destination...

Page 1360: ...urce Object Number Static Insert Behind Remove a message object source object from the list that it currently belongs to and insert it behind a given destination object into the list structure of the destination object The source object thus becomes the successor of the destination object 07H Argument Destination Object Number Result Bit 7 ERR Bit 6 0 undefined Result Object Number of inserted obj...

Page 1361: ...00H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPSEL 0 rw r Field Bits Type Description MPSEL 15 12 rw Message Pending Selector Bit field MPSEL makes it possible to select the bit position of the message pending bit after a message reception transmission by a mixture of the MOIPRn register bit fields RXINP TXINP and MPN Selection details are given in ...

Page 1362: ...00 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IT w Field Bits Type Description IT 15 0 w Interrupt Trigger Writing a 1 to IT n n 0 15 generates an interrupt request on interrupt output line INT_O n Writing a 0 to IT n has no effect Bit field IT is always read as 0 Multiple interrupt requests can be generated with a single write operation to MITR...

Page 1363: ...or CAN node 1 LIST3 provides the list for CAN node 2 LIST4 provides the list for CAN node 3 LIST 7 5 are not associated to a CAN node free lists Each list is defined by a List Register that contains the first and the last element message object number and the size number of message objects assigned to the list of the list LIST0 List Register 0 100H Reset Value 007F 7F00H LISTk k 1 7 List Register ...

Page 1364: ... V2 0 SIZE 23 16 rh List Size SIZE indicates the number of elements in the list k SIZE number of list elements 1 EMPTY 24 rh List Empty Indication 0B At least one message object is allocated to list k 1B No message object is allocated to the list k List k is empty 0 31 25 r Reserved Read as 0 Field Bits Type Description ...

Page 1365: ...chanism is implemented in the MultiCAN module to select the highest priority object within a collection of message objects The Message Pending Register MSPNDk contains the pending interrupt notification of list k MSPNDk k 0 7 Message Pending Register k 120H k 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PND rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PND rwh Field Bits T...

Page 1366: ...27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 INDEX r rh Field Bits Type Description INDEX 5 0 rh Message Pending Index The value of INDEX is given by the bit position i of the pending bit of MSPNDk with the following properties 1 MSPNDk i IM i 1 2 i 0 or MSPNDk i 1 0 IM i 1 0 0 If no bit of MSPNDk satisfies these conditions then INDEX reads 100000B Thus INDEX sho...

Page 1367: ...Mask Register is used commonly for all Message Pending registers and their associated Message Index registers MSIMASK Message Index Mask Register 1C0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IM rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IM rw Field Bits Type Description IM 31 0 rw Message Index Mask Only those bits in MSPNDn for which the corresponding Index Mask bits ...

Page 1368: ...ain information that is directly related to the operation of the CAN nodes and are shared among the nodes The Node Control Register contains basic settings that determine the operation of the CAN node NCRx x 0 3 Node x Control Register 200H x 100H Reset Value 0000 0001H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SUS EN CAL M CCE 0 CAN DIS ALIE LEC I...

Page 1369: ...es the participation of this node in the CAN traffic Any ongoing frame transfer is cancelled and the transmit line goes recessive If the CAN node is in the bus off state then the running bus off recovery sequence is continued If the INIT bit is still set after the successful completion of the bus off recovery sequence i e after detecting 128 sequences of 11 consecutive recessive bits 11 1 then the...

Page 1370: ...upt is disabled 1B Alert interrupt is enabled Bit field NIPRx ALINP selects the interrupt output line which becomes activated at this type of interrupt CANDIS 4 rw CAN Disable Setting this bit disables the CAN node The CAN node first waits until it is bus idle or bus off Then bit INIT is automatically set and an alert interrupt is generated if bit ALIE is set CCE 6 rw Configuration Change Enable 0...

Page 1371: ...ode via OCDS on chip debug support 0B An OCDS suspend trigger is ignored by the CAN node 1B An OCDS suspend trigger disables the CAN node As soon as the CAN node becomes bus idle or bus off bit INIT is internally forced to 1 to disable the CAN node The actual value of bit INIT remains unchanged Bit SUSEN is cleared via OCDS Reset 0 31 9 5 r Reserved Read as 0 should be written with 0 Field Bits Ty...

Page 1372: ...e Description LEC 2 0 rwh Last Error Code This bit field indicates the type of the last most recent CAN error The encoding of this bit field is described in Table 22 7 TXOK 3 rwh Message Transmitted Successfully 0B No successful transmission since the last most recent clearance of the flag 1B A message has been transmitted successfully error free and acknowledged by at least another node TXOK must...

Page 1373: ...it EWRNLVL BOFF 7 rh Bus off Status 0B CAN controller is not in the bus off state 1B CAN controller is in the bus off state LLE 8 rwh List Length Error 0B No List Length Error since the last most recent clearance of the flag 1B A List Length Error has been detected during message acceptance filtering The number of elements in the list that belongs to this CAN node differs from the list SIZE given ...

Page 1374: ...ts in a sequence have occurred in a part of a received message where this is not allowed 010B Form Error A fixed format part of a received frame has the wrong format 011B Ack Error The transmitted message was not acknowledged by another node 100B Bit1 Error During a message transmission the CAN node tried to send a recessive level 1 outside the arbitration field and the acknowledge slot but the mo...

Page 1375: ...AN V2 0 110B CRC Error The CRC checksum of the received message was incorrect 111B CPU write to LEC Whenever the CPU writes the value 111B to LEC it takes the value 111B Whenever the CPU writes another value to LEC the written LEC value is ignored Table 22 7 Encoding of the LEC Bit Field cont d LEC Value Signification ...

Page 1376: ...CINP TRINP LECINP ALINP rw rw rw rw Field Bits Type Description ALINP 3 0 rw Alert Interrupt Node Pointer ALINP selects the interrupt output line INT_Om m 0 15 for an alert interrupt of CAN Node x 0000B Interrupt output line INT_O0 is selected 0001B Interrupt output line INT_O1 is selected B 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected LECINP 7 4 ...

Page 1377: ...T_O1 is selected B 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected CFCINP 15 12 rw Frame Counter Interrupt Node Pointer CFCINP selects the interrupt output line INT_Om m 0 15 for a frame counter overflow interrupt of CAN Node x 0000B Interrupt output line INT_O0 is selected 0001B Interrupt output line INT_O1 is selected B 1110B Interrupt output line ...

Page 1378: ...RXSEL 2 0 rw Receive Select RXSEL selects one out of 8 possible receive inputs of CAN node x The CAN receive signal is performed only through the selected input Note In TC1796 only specific combinations of RXSEL are available see also Receive Input Selection on Page 22 207 LBM 8 rw Loop Back Mode 0B Loop Back Mode is disabled 1B Loop Back Mode is enabled This node is connected to an internal virtu...

Page 1379: ...1 clock cycles if DIV8 0 The duration of one time quantum is given by 8 BRP 1 clock cycles if DIV8 1 SJW 7 6 rw Re Synchronization Jump Width SJW 1 time quanta are allowed for re synchronization TSEG1 11 8 rw Time Segment Before Sample Point TSEG1 1 time quanta is the user defined nominal time between the end of the synchronization segment and the sample point It includes the propagation segment w...

Page 1380: ...ion on the CAN bus then the SOF is sent with the beginning of a new bit time If the CAN bus is in the idle state and bit FTX is set FTX 1 a new bit time is started immediately with the transmit trigger of a new message This eliminates the variable delay between the transmit trigger of a message and the actual SOF signal on the transmit output Such a variable delay occurs when transmit triggers occ...

Page 1381: ...REC 7 0 rwh Receive Error Counter Bit field REC contains the value of the receive error counter of CAN node x TEC 15 8 rwh Transmit Error Counter Bit field TEC contains the value of the transmit error counter of CAN node x EWRNLVL 23 16 rw Error Warning Level Bit field EWRNLVL determines the threshold value warning level default 96 to be reached in order to set the corresponding error warning bit ...

Page 1382: ...IE 0 CFMOD CFSEL r rwh rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFC rwh Field Bits Type Description CFC 15 0 rwh CAN Frame Counter In Frame Count Mode CFMOD 00B this bit field contains the frame count value In Time Stamp Mode CFMOD 01B this bit field contains the captured bit time count value captured with the start of a new frame In all Bit Timing Analysis Modes CFMOD 10B CFC always displ...

Page 1383: ...ew bit time The value is sampled during the SOF bit of a new frame The sampled value is visible in the CFC field Bit Timing Mode The available bit timing measurement modes are shown in Table 22 8 This bit field selects the function of the frame counter for the chosen frame count mode CFMOD 20 19 rw CAN Frame Counter Mode This bit field determines the operation mode of the frame counter 00B Frame C...

Page 1384: ... a recessive edge transition from 0 to 1 is monitored on the receive input the time measured in clock cycles between this edge and the most recent dominant edge is stored in CFC 010B Whenever a dominant edge is received as a result of a transmitted dominant edge the time clock cycles between both edges is stored in CFC 011B Whenever a recessive edge is received as a result of a transmitted recessi...

Page 1385: ...andard ID transmit only RTR reserved bits IDE DLC MSB bit 7 MSB in each data byte and the first bit of the ID extension 10B Bit This code represents a bit inside a frame segment with a length of more than one bit not the first bit of those frame segments that is indicated by NewBit The current bit is processed within one of the following frame segments ID bits except first bit of standard ID for t...

Page 1386: ...H Reset Value 7F7E 0000H MOCTRn n 1 126 Message Object n Control Register 0061CH n 20H Reset Value n 1 01000000H n 1 00010000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SET DIR SET TX EN1 SET TX EN0 SET TX RQ SET RX EN SET RT SEL SET MSG VAL SET MSG LST SET NEW DAT SET RX UPD SET TX PND SET RX PND w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RES DIR RES TX EN1 RES TX E...

Page 1387: ... These bits control the clear set condition for RTSEL see Table 22 20 RESRXEN SETRXEN 7 23 w Reset Set Receive Enable These bits control the clear sett condition for RXEN see Table 22 20 RESTXRQ SETTXRQ 8 24 w Reset Set Transmit Request These bits control the clear set condition for TXRQ see Table 22 20 RESTXEN0 SETTXEN0 9 25 w Reset Set Transmit Enable 0 These bits control the clear set condition...

Page 1388: ...e 22 10 Clear Set Conditions for Bits in Register MOCTRn RESy Bit1 1 The parameter y stands for the second part of the bit name RXPND TXPND up to DIR SETy Bit Action on Write Write 0 Write 0 Leave element unchanged No write No write Write 0 Write 1 Write 1 Write 1 Write 0 Clear element No write Write 0 Write 1 Set element No write ...

Page 1389: ...ster 061CH n 20H Reset Value n 1 01000000H n 1 00010000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PNEXT PPREV rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIST DIR TX EN1 TX EN0 TX RQ RX EN RTS EL MSG VAL MSG LST NEW DAT RX UPD TX PND RX PND rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description RXPND 0 rh Receive Pending 0B No CAN message has been received 1B A CAN message has b...

Page 1390: ...eived CAN frame has been stored in message object n NEWDAT is cleared by hardware when a CAN transmission of message object n has been started NEWDAT should be set by software after the new transmit data has been stored in message object n to prevent the automatic clearing of TXRQ at the end of an ongoing transmission MSGLST 4 rh Message Lost 0B No CAN message is lost 1B A CAN message is lost beca...

Page 1391: ...re Frame Transmission RTSEL is set by hardware when message object n has been identified to be transmitted next A check is performed to determine if RTSEL is still set before message object n is actually set up for transmission and bit NEWDAT is cleared It is also checked that RTSEL is still set before it message object n is verified due to the successful transmission of a frame RTSEL needs to be ...

Page 1392: ...gain by software TXEN0 9 rh Transmit Enable 0 0B Message object n is not enabled for frame transmission 1B Message object n is enabled for frame transmission Message object n can be transmitted only if both bits TXEN0 and TXEN1 are set The user may clear TXEN0 in order to inhibit the transmission of a message that is currently updated or to disable automatic response of Remote Frames TXEN1 10 rh T...

Page 1393: ...15 12 rh List Allocation LIST indicates the number of the message list to which message object n is allocated LIST is updated by hardware when the list allocation of the object is modified by a panel command PPREV 23 16 rh Pointer to Previous Message Object PPREV holds the message object number of the previous message object in a message list structure PNEXT 31 24 rh Pointer to Next Message Object...

Page 1394: ...XINP selects the interrupt output line INT_Om m 0 15 for a receive interrupt event of message object n RXINP can also be taken for message pending bit selection see Page 22 42 0000B Interrupt output line INT_O0 is selected 0001B Interrupt output line INT_O1 is selected B 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected TXINP 7 4 rw Transmit Interrupt ...

Page 1395: ...it field selects the bit position of the bit in the Message Pending Register that is set upon a message object n receive transmit interrupt CFCVAL 31 16 rwh CAN Frame Counter Value When a message is stored in message object n or message object n has been successfully transmitted the CAN frame counter value NFCRx CFC is then copied to CFCVAL Field Bits Type Description ...

Page 1396: ...w rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DAT C DLC C ID C GDF S 0 MMC rw rw rw rw rw rw rw Field Bits Type Description MMC 3 0 rw Message Mode Control MMC controls the message mode of message object n 0000B Standard Message Object 0001B Receive FIFO Base Object 0010B Transmit FIFO Base Object 0011B Transmit FIFO Slave Object 0100B Gateway Source Object All other combinations are...

Page 1397: ...bject Applicable only to a gateway source object ignored in other nodes DATC 11 rw Data Copy 0B Data fields are not copied 1B Data fields in registers MODATALn and MODATAHn of the gateway source object after storing the received frame in the source are copied to the gateway destination Applicable only to a gateway source object Ignored in other nodes RXIE 16 rw Receive Interrupt Enable RXIE enable...

Page 1398: ... the value of SEL in the FIFO Gateway Pointer Register 0B FIFO full interrupt is disabled 1B FIFO full interrupt is enabled If message object n is a Receive FIFO base object bit field MOIPRn TXINP selects the interrupt output line which becomes activated at this type of interrupt If message object n is a Transmit FIFO base object bit field MOIPRn RXINP selects the interrupt output line which becom...

Page 1399: ...a FIFO base object then MSGVAL is cleared when this object has taken part in a successful data transfer receive or transmit If SDT 1 and message object n is a FIFO base object then MSGVAL is cleared when the pointer to the current object CUR reaches the value of SEL in the FIFO Gateway Pointer Register With SDT 0 bit MSGVAL is not affected STT 23 rw Single Transmit Trial If this bit is set TXRQ is...

Page 1400: ... S0 or S1 MSC is decremented by one If the transmission fails bit field MSC is incremented by one If the TTCAN is in error state S2 and detects CAN bus idle during the transmit enable window for message object n MSC is decremented by one although this message object is not transmitted Reception When message object n is scheduled for reception in an exclusive time window and the reception is succes...

Page 1401: ...Bit field BOT points to the first element in a FIFO structure TOP 15 8 rw Top Pointer Bit field TOP points to the last element in a FIFO structure CUR 23 16 rwh Current Object Pointer Bit field CUR points to the actual target object within a FIFO Gateway structure After a FIFO gateway operation CUR is updated with the message number of the next message object in the list structure given by PNEXT o...

Page 1402: ...0 Message Object n Acceptance Mask Register MOAMRn contains the mask bits for the acceptance filtering of message object n MOAMRn n 0 127 Message Object n Acceptance Mask Register 060CH n 20H Reset Value 3FFF FFFFH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MID E AM rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AM rw ...

Page 1403: ...e AMR contains the following information MOAMR 5 0 CYCLE MOAMR 13 8 MCYCLE MOAMR 21 16 COLUMN MOAMR 29 24 MCOLUMN where CYCLE is the cycle count transmit row and COLUMN is the transmission column of the system matrix MCYCLE and MCOLUMN are acceptance masks for matching CYCLE and COLUMN against the actual position within the system matrix of the time triggered communication network Message object n...

Page 1404: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PRI IDE ID rw rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID rwh Field Bits Type Description ID 28 0 rwh CAN Identifier of Message Object n Identifier of a standard message ID 28 18 or an extended message ID 28 0 For standard identifiers bits ID 17 0 are don t care IDE 29 rwh Identifier Extension Bit of Message Object n 0B Message object n handles...

Page 1405: ... may be transmitted Transmit acceptance filtering is based on the list order This means that message object n is considered for transmission only if there is no other message object with valid transmit request MSGVAL TXEN0 TXEN1 1 that matches the actual position within the transmission matrix somewhere before this object in the list 01B Transmit acceptance filtering is based on the list order Thi...

Page 1406: ...end Standard Frame B MOAR IDE 1 send Extended Frame Standard Frames have higher transmit priority than extended frames with equal standard identifier A MOAR 28 18 B MOAR 28 18 A MOAR IDE B MOAR IDE 0 A MOCTR DIR 1 send Data Frame B MOCTR DIR 0 send Remote Fame Standard Data Frames have higher transmit priority than Standard Remote Frames with equal identifier A MOAR 28 0 B MOAR 28 0 A MOAR IDE B M...

Page 1407: ...o upon reception and ignored for transmission MODATALn n 0 127 Message Object n Data Register Low 0610H n 20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB3 DB2 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB1 DB0 rwh rwh Field Bits Type Description DB0 7 0 rwh Data Byte 0 of Message Object n DB1 15 8 rwh Data Byte 1 of Message Object n DB2 23 16 rwh Data Byte 2 of Mes...

Page 1408: ...ro upon reception and ignored for transmission MODATAHn n 0 127 Message Object n Data Register High 0614H n 20H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 DB6 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 DB4 rwh rwh Field Bits Type Description DB4 7 0 rwh Data Byte 4 of Message Object n DB5 15 8 rwh Data Byte 5 of Message Object n DB6 23 16 rwh Data Byte 6 of M...

Page 1409: ...om the fractional divider an NTU timer action takes place with tq or with a multiple of 1 fCAN The sum of the NTU is the local time LT which is a 16 bit value to be considered as integer number and a fractional part LTFR Figure 22 25 Generation of the Local Time MCA05851 LREFM 16 LREFMFR REFM REFMFR 7 16 SYNM SYNMFR 7 16 LT LTFR 7 Reference Message Correctly Transferred Frame_Sync SOF 16 16 10 10 ...

Page 1410: ... to dt TURR TUR 1024 N tupd 22 5 2 Automatic TUR Adjust It is possible to automatically calculate the new value written to TURADJ for adjusting the correct value for the local time on TTCAN level 2 Each time a new reference message is correctly received the difference is calculated between the time values in the reference message GMR and the previous reference message LGMR This difference divided ...

Page 1411: ...ce message 22 5 3 2 Time Marks Each time a reference message is received correctly the cycle control unit starts again comparing the cycle time to the first time mark TM 1 If one time mark is reached it continues with the next one In order to be able to do an equal to comparison the time marks have to be programmed in increasing order and the first time mark must not be lower than the length of th...

Page 1412: ... master s clock or its local time has been corrected and a discontinuity has been introduced the discontinuity bit DISC is automatically set until the next reference message is started The discontinuity bit is set if a write access to LOF or LOFFR occurs As a result the reference message will contain the new reference mark and the discontinuity bit DISC set for the current time master 22 5 5 Trans...

Page 1413: ... Global Mark Register GMR The Local_Offset is stored in the local offset register LOR When a TTCAN node receives a reference message the global mark register is updated by the received value The value that has been received in the previous reference message is automatically transferred from the global mark register to the last global mark register The difference between these two values represents...

Page 1414: ...ssages to be sent in exclusive time windows The number of messages to be transmitted in exclusive time windows is defined by system application design for the entire system matrix expected transmit triggers EXPTT This theoretical value is used to verify if the real TTCAN node also requests the same amount of transmissions If fewer or more transmit triggers have been counted by the transmit trigger...

Page 1415: ...to a reference time mark or to an external event for synchronization If a correct reference message is received while REFTRG is set REFTRG is automatically cleared For transmission the identifier bits of the reference message object are taken except the 3 least significant bits ID 2 0 They are taken from the bit field TMCR TMPRIO The corresponding parts of its eight data bytes are directly connect...

Page 1416: ...TTSR ETR 1 indicates that the next reference message will be transferred as soon as the corresponding time mark is reached respecting the gap or when the selected trigger event ETREV is pending The evaluation of ETREV is not started before 1 CAN bit time has elapsed after the end of the transmit enable window of the last transfer window The transmit trigger generation logic for the reference messa...

Page 1417: ...gger Trigger by Reference Mark of this CAN node 0 Reference message transferred correctly or reset by software Set Reset by SW TRMC0 000 001 111 TRMC1 TRMC7 Trigger for Reference Mark of another TTCAN node input x for this TTCAN node 0 Set 00 01 10 11 ETREV 0 1 ETM Reset Trigger Event Reference message transferred correctly Reference message transferred correctly or reset by software Valid RME ent...

Page 1418: ...s include for example starting the transmission of a message checking if a message has been received opening or closing arbitration windows or generating interrupts Figure 22 30 Scheduler Overview The instructions following a time mark are read by the scheduler until the next time mark entry is found Then the instruction collection process is stopped until the next time mark is reached Note The ti...

Page 1419: ...he TC1796 the scheduler memory has a size of 128 words 32 bits Figure 22 31 TTCAN Scheduler Memory The last word address of the scheduler memory is reserved for the start pointer STPTR0 The value written at this address determines the start location of the first entry for the TTCAN node CAN node 0 in the TC1796 STPTR0 indicates how many 32 bit word entries below SPTR0 the first time mark entry TME...

Page 1420: ...mark the settings are cleared and must be set up by new scheduler instructions if desired The complete scheduler information must be finished with a basic cycle end entry that fixes the value for the watch trigger event Each entry in the scheduler memory contains a 4 bit wide code field that determines the type of the entry The possible scheduler memory entry types are listed in Table 22 13 The ge...

Page 1421: ...M IEN REC F1 IEN REC F0 IEN TRA F1 IEN TRA F0 INP rw rw rw rw r rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMV rw Field Bits Type Description TMV1 15 0 rw Time Mark Value This bit field determines the compare value used for the next compare action with the cycle time INP 19 16 rw Interrupt Node Pointer INP selects the interrupt output line INT_Om m 0 15 that will be activated when a m...

Page 1422: ... is detected between the cycle time and the time mark value defined by TMV 0B Interrupt generation is disabled 1B Interrupt generation is enabled IENRECF0 22 rw Interrupt Enable if RECF 0 This bit enables the generation of an interrupt when when bit TTSR RECF 0 and a match is detected between the cycle time and the time mark value defined by TMV 0B Interrupt generation is disabled 1B Interrupt gen...

Page 1423: ...w will be closed Closing a merged transfer window leads to a single short arbitration window transmission possible only during the transmit enable window The short arbitration window is automatically closed after one time window If there is no arbitration window open this entry will be ignored 11B A single short arbitration window transmission possible only during the transmit enable window is ope...

Page 1424: ...bit field determines the number of the basic cycle during which this interrupt control entry is valid The value of CYCLE is compared bit wise to the current value of the bit field CYCTMR BCC The result is then masked with the value given by the bit field MCYCLE in order to determine the repetition rate for this scheduler entry inside the matrix cycle This bit field is equivalent to the correspondi...

Page 1425: ...upt will not be generated 1B An interrupt will be generated IENTRAF1 21 rw Interrupt Enable if TRAF 1 This bit enables the generation of an interrupt when a match is detected between the cycle time and the time mark value defined by TMV and bit TRAF 1 0B An interrupt will not be generated 1B An interrupt will be generated IENRECF0 22 rw Interrupt Enable if RECF 0 This bit enables the generation of...

Page 1426: ...ler operation when EC 0011B ARBE Arbitration Entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 1 1 0 ARBM 0 rw rw rw rw r rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MCYCLE 0 CYCLE r rw r rw Field Bits Type Description CYCLE 5 0 rw Basic Cycle Number This bit field determines the number of the basic cycle during which this arbitration entry is valid The value of CYCLE is compared bit wise...

Page 1427: ...taken with an arbitration window 00B No action is taken the status of the window is not changed 01B A merged long arbitration window will be opened If it is already opened it is kept open 10B A merged long transfer window will be closed Closing a merged transfer window leads to a single short arbitration window transmission possible only during the transmit enable window The short arbitration wind...

Page 1428: ...e number of the basic cycle during which this transmit control entry is valid The value of CYCLE is compared bit wise to the current value of the bit field CYCTMR BCC The result is then masked with the value given by the bit field MCYCLE in order to determine the repetition rate for this transmit control entry inside the matrix cycle This bit field is equivalent to the corresponding part of the MO...

Page 1429: ...ntry according to ALTMSG If the message object delivered by the transmit control entry is not valid for transmission no transmission will be started If the implementation of the CAN controller supports fewer than 256 message objects higher values for MSGNR than the number of actually supported message objects will be treated with a modulo operation e g if 128 objects are supported the value of MSG...

Page 1430: ...be transmitted 00B If the message object number delivered by this entry is not valid for transmission no message will be sent 01B The message object number delivered by this entry is not taken into account for transmission the message object found by the transmit acceptance filtering will be sent if it is valid 10B If the message object delivered by this entry is not valid for transmission while t...

Page 1431: ...e number of the basic cycle during which this receive control entry is valid The value of CYCLE is compared bit wise to the current value of the bit field CYCTMR BCC The result is then masked with the value given by the bit field MCYCLE in order to determine the repetition rate for this scheduler entry inside the matrix cycle This bit field is equivalent to the corresponding part of the MOAMRn AM ...

Page 1432: ...cked for correct reception of a message during the last transfer window A received message is always stored in the message object that is determined by acceptance filtering When reaching a new time mark an RCE can be used to check if a desired message has actually been received in the desired message object CHEN 24 rw Check Enable Only time windows with an active receive control entry with CHEN 1 ...

Page 1433: ... next compare action with the cycle time If the CAN node is a time master the reference message will be sent out when the time mark is reached see also TMR RTO GM 27 rw Gap Mode This bit determines how the scheduler of a time master proceeds if the TTCAN node is in a gap 0B The reference message will be sent according to this RME entry without respecting a possible gap 1B If the TTCAN node is in a...

Page 1434: ...ster In the case that more valid reference message entries are detected the settings of the previously found reference message entries are overruled by a subsequent one If the TTCAN node is not configured as time master and the scheduler reads an RME a configuration error is generated While the system is in the synchronization state an RME entry with GM 1 is taken into account ...

Page 1435: ...ws BCE Basic Cycle End Entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1 1 GM 0 rw rw rw rw rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMV rw Field Bits Type Description TMV 15 0 rw Time Mark Value This bit field determines the compare value for the next time mark that is used for the next compare action with the cycle time TMV determines the watch trigger that is used to generate a watc...

Page 1436: ...mory and sets the TTCAN node into Configuration Mode EOS can be regarded as a kind of emergency stop entry It should not be used to control the scheduler itself but represents a security mechanism for the case that a scheduler entry does not show a valid EC bit field GM 27 rw Gap Mode This bit determines how the scheduler proceeds when the TTCAN node is in a gap and waits for a trigger event to se...

Page 1437: ...g status and from the scheduler instruction status register The information becomes valid when the next time mark is reached The information collected between time mark n 1 and time mark n becomes valid when the time mark n is reached Figure 22 32 Collecting the Instructions 22 6 4 1 Instructions During a Basic Cycle The handling of entries collected between the time marks n 1 and n is defined as ...

Page 1438: ...t used in this time window The TMV value collected after time mark n 1 will become the new compare value for the time mark n The value of CYCTMR CSM equals the time mark number of the last time mark reached CSM n after time mark n has been reached The value of CYCTMR BCC is number of the current basic cycle This information is needed to correctly set up the scheduler entries bit fields CYCLE MCYCL...

Page 1439: ...transmission can start during the complete time window This entry must be written into the scheduler memory after the entry TME1 Reference Message Entry The time mark value of a valid RME is defining the compare value for the reference time mark When this reference time mark plus the reference trigger offset is reached a reference message will be sent out depending on the gap state of the system T...

Page 1440: ...me window of a basic cycle In order to set up the scheduler instructions correctly the values of CSM and BCC in register CYCTMR must be respected carefully especially for the last time window of a basic cycle When leaving the Configuration Mode BCC and CSM are 0 and the scheduler starts with time mark 1 The values for BCC and CSM in Figure 22 23 represent the internal values that are updated after...

Page 1441: ...ers BCE for slave devices The scheduler entries must always be closed with a BCE with GM 0 For time masters the following sequence can be set up to close the scheduler entries RME GM 1 then BCE GM 1 then RME GM 0 then BCE GM 0 the entries RME GM 0 and BCE GM 0 are mandatory If the system is in a gap the first RME and BCE entries both with GM 1 are not taken into account With these entries the stan...

Page 1442: ...MCOLUMN In the case that the programmed values for CYCLE MCYCLE etc do not match the given values of CSM and BCC the respective entry is considered invalid and its information is not taken into account for the corresponding time window The following example shows a scheduler instruction sequence for the basic cycle m with n time mark entries TME1 RCE ICE CSM n BCC m 1 or CSM BCC 0 when the Configu...

Page 1443: ...red to TURR TUR hardware The scheduler memory entries must be initialized software The TTCAN control information ID of reference message etc and the TTCAN node itself must be set up completely and enabled for CAN message transfer software After the complete configuration software TTFMR CFGMEL must be set to 10B software The local time starts after leaving the Configuration Mode hardware The synchr...

Page 1444: ...node is set to Configuration Mode During the synchronization phase the scheduler entries RME or BCE with GM 1 are not taken into account 22 7 4 Time Masters 22 7 4 1 State of a Time Master A potential time master is a device that can transmit a reference message A backup time master is a potential time master that has received a reference message that was not its own The current time master is the...

Page 1445: ...3 Severe Error Notification of the application by an interrupt ERRS3 All CAN bus actions are stopped no dominant values are transmitted on the bus The configuration phase is entered automatically CFGM is set Source Application Watchdog Bus Off Config Error Watch Trigger Event Impact Bit INIT of the CAN node will be set the CAN node stops actions on the bus Note Any change of the error state can ge...

Page 1446: ...ace when the end of the transmit enable window of the following time marks is reached Because the transmit enable window length is known after each time mark even if no message shall be sent out this point in time can be used for the receive and the transmit check This feature makes it possible to have a positive check result even if the message in the preceding time window finishes during the tra...

Page 1447: ...w Basic Cycle and Notification Interrupt Structure MCA05860 NBCINP NBC New Matrix Cycle New Basic Cycle New Basic Cycle Interrupt TTIRR TTINPR 01 10 11 00 NMC NBCIE 2 TTIER State Change TTSR WFE DISC SYNCSC MSRC ERRSC TTIRR Last Reference Message indicates next is Gap TTIRR Last Reference Message indicates Discontinuity NOTIFIE ERRSCIE MSRCIE SYNCSCIE TTIER TTIER NOTIFINP TTINPR Notification Inter...

Page 1448: ...5861 Transmit Enable Window Error Interrupt TENWER TTIRR TENWERIE Transmit Trigger Error Interrupt TTOF TTUF TTERIE Overflow Underflow Watch Trigger Event Interrupt IWTE WTE WTEIE TTIER TTIRR TTIER TTIRR TTIER Application Watchdog Interrupt AWDERR TTIRR AWDIE TTIER Scheduler Error Interrupts CFGERR SERR2 TTIRR Error Type 2 Configuration Error EOS Entry Read Error Type 1 SERR1 EOS SEIE TTIER ERRINP...

Page 1449: ...r 280H Page 22 159 SYNMR Synchronization Mark Register 284H Page 22 160 REFMR Reference Mark Register 288H Page 22 161 LREFMR Last Reference Mark Register 28CH Page 22 162 TURR Time Unit Ratio Register 290H Page 22 157 CYCTMR Cycle Time Register 294H Page 22 163 LOR Local Offset Register 298H Page 22 164 GMR Global Mark Register 29CH Page 22 166 LGMR Last Global Mark Register 2A0H Page 22 167 AWDR...

Page 1450: ... 180 TTIRR Time Trigger Interrupt Request Register 2D0H Page 22 182 TTIER Time Trigger Interrupt Enable Register 2D4H Page 22 186 TTINPR Time Trigger Interrupt Node Pointer Register 2D8H Page 22 190 STSRL Scheduler Timing Status Register Low 2F0H Page 22 193 STSRH Scheduler Timing Status Register High 2F4H Page 22 194 SISR Scheduler Instruction Status Register 2F8H Page 22 195 STPTR0 Scheduler Sta...

Page 1451: ...g Local Time Register Synch Mark Register Reference Mark Register Time Unit Ratio Register Cycle Time Register Global Mark Register Local Offset Register Application Watchdog Reg Last Global Mark Register Last Reference Mark Register 280H 284H 288H 28CH 290H 294H 298H 29CH 2A0H 2A4H 2C0H 2C4H 2C8H 2CCH 2D0H 2D4H 2D8H TTCAN Timing Registers for Node 0 280H TTCAN Control Status Config Registers for ...

Page 1452: ...it ADJEN will be automatically cleared when an overflow or an underflow of the automatically calculated value occurs 0B The automatic TUR calculation is disabled The new value for time unit ratio for TURADJ must be calculated and written by software 1B The automatic TUR calculation is enabled After receiving a reference message a new value for TURADJ is calculated by hardware The calculated value ...

Page 1453: ...CS 17 rw Local Time Clock Source This bit determines the clock source for the local time generation addition of TUR to LT LTFR for TTCAN level 2 0B A new local time value is generated with each time quantum tq of the corresponding CAN node depending on the CAN bit timing 1B The local time generation is based on the CAN module clock fCAN independent from the CAN bit timing The update rate tupd is b...

Page 1454: ...Description LTFR 15 6 rh Local Time Fraction This bit field contains the fractional part of the NTU counter TTCAN level 2 only In the case of an overflow after the addition of the TUR value the value of LT is incremented by one LT 31 16 rh Local Time This bit field contains the integer part of the NTU counter In TTCAN level 1 it is incremented with each CAN bit time in level 2 it is incremented ea...

Page 1455: ...24 23 22 21 20 19 18 17 16 SYNM rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYNMFR 0 rh r Field Bits Type Description SYNMFR 15 9 rh Synchronization Mark Fraction This bit field contains the fractional part of the synchronization mark SYNMFR is the bit field LTR LTFR captured with the frame synchronization pulse SYNM 31 16 rh Synchronization Mark This bit field contains the integer part of the synchr...

Page 1456: ... 1 0 REFMFR 0 rh r Field Bits Type Description REFMFR 15 9 rh Reference Mark Fraction This bit field contains the fractional part of the reference mark REFMFR is the bit field SYNMR SYNMFR captured with the correct end of the reference message REFM 31 16 rh Reference Mark This bit field contains the integer part of the reference mark REFM is the bit field SYNMR SYNM captured with the correct end o...

Page 1457: ...MFR 0 rh r Field Bits Type Description LREFMFR 15 9 rh Last Reference Mark Fraction This bit field contains the fractional part of the last reference mark LREFMFR is the bit field REFMR REFMFR captured with the correct end of the reference message LREFM 31 16 rh Last Reference Mark This bit field contains the integer part of the last reference mark LREFM is the bit field REFMR REFM captured with t...

Page 1458: ... indicates the time already elapsed in the current basic cycle It is calculated by LTR LT REFMR REFM In the case of a negative result overflow of LTR LT the result is corrected BCC 21 16 rh Basic Cycle Count This bit field indicates the number of the current basic cycle It is incremented after each correctly transferred reference message CSM 29 24 rh Column of System Matrix This bit field indicate...

Page 1459: ...ce mark It is set automatically when a write action to LOR is detected It is cleared when the local time is captured at SOF for the transmission of the reference message 0B A write access to LOR has not occurred 1B A write access to LOR has occurred DISC 1 rh Discontinuity Bit This bit contains the DISC bit of the reference message that is sent out taken into account for a time master This bit is ...

Page 1460: ...y taken into account for the transmission of the reference message bit DISC is set automatically LOF 31 16 rwh Local Offset This bit field contains the integer part of the local offset Time master transmitting reference messages The sum of the local offset and the local time is stored as global time in register GTR Not time master receiving reference messages The local offset is the received globa...

Page 1461: ...ark Fraction This bit field contains the fractional part of the global mark GM 31 16 rh Global Mark This bit field contains the integer part of the global mark Time master transmitting reference messages The sum of the local offset and the local time is stored as global time Global_Sync_Mark in register GMR at the beginning of the reference message Not time master receiving reference messages The ...

Page 1462: ...the actual time master LGMR Last Global Mark Register 2A0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LGM rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LGMFR 0 rh r Field Bits Type Description LGMFR 15 9 rh Last Global Mark Fraction This bit field contains the value of GMFR of the last reference mark LGM 31 16 rh Last Global Mark This bit field contains the value of GM of th...

Page 1463: ...lue of the application watchdog The falling edge of bit LTR LT 7 1 to 0 transition indicates that the time of 256 NTUs has elapsed and the application watchdog value is automatically decremented by 1 If the value 0 is reached after decrementing an S3 error is signaled by bit TTIRR AWDERR AWDV is not decremented below 0 The application watchdog is serviced by the program by writing a new value to t...

Page 1464: ...0 rw Time Trigger Mode This bit determines the behavior of the TTCAN node concerning the time trigger and the time master functionality 00B CAN node is disabled for TTCAN operation and operates in event triggered mode other settings for TTCAN are inactive The reference message object operates for reception or transmission as any other message object 01B CAN node is enabled for TTCAN operation as a...

Page 1465: ... the transmission of the reference message 10B A positive edge at an external trigger input ECTTx as selected by ETSSEL triggers the transmission of the reference message 11B A negative or positive edge at an external trigger input ECTTx as selected by ETSSEL triggers the transmission of the reference message ETSSEL 6 4 rw External Trigger Source Selection This bit fields selects the input source ...

Page 1466: ...he level of the TTCAN functionality 0B TTCAN level 1 is selected 1B TTCAN level 2 is selected TMPRIO 14 12 rw Time Master Priority This bit field determines the priority of the potential time master This value will be used for the transmission of the ID bits 2 0 of the reference message In the case that the TTCAN node looses arbitration against another reference mark on the bus or receives a refer...

Page 1467: ... can elapse 1111B Sixteen CAN bit times can elapse RMDLC 31 28 rw Reference Message DLC This bit field determines the data length code DLC of reference messages sent out by this CAN node if it is a time master The DLC bit field in the reference message object contains the DLC of the previously received reference message Note that RMDLC must be programmed only to values from 1 to 8 for TTCAN level ...

Page 1468: ... are expected in a matrix cycle RTO 23 16 rh Reference Trigger Offset This bit field indicates the actual reference trigger offset This value is considered as 2 s complement and can reach values between 127 and 127 It is added to the time mark given by the basic cycle end entry in the scheduler memory for the trigger of the reference message The modification and the corresponding conditions are li...

Page 1469: ...ftware Set to TTCFGR IRO Each time a potential time master receives a reference message with a higher priority than its own Decrement by 1 Each time a potential time master receives a reference message with a lower priority than its own until 127 is reached Set to 127 When the S2 state is entered Set to 0 When the TTCAN node has correctly transmitted its reference message it is the current time ma...

Page 1470: ...7 6 5 4 3 2 1 0 REC F TRA F TM PC CFG M ARB REF TRG EFF EFI 0 SYNCS MSR ERRS rh rh rh rh rh rh rh rh r rh rh rh Field Bits Type Description ERRS 1 0 rh Error State This bit field indicates the current error severity level 00B No error 01B Warning 10B Error 11B Severe error MSR 3 2 rh Master Slave Relation This bit field indicates the current master to slave relation of the TTCAN node 00B Master of...

Page 1471: ... a LEC interrupt can be generated by the CAN node EFF 9 rh Error Frame Flag This bit monitors the Error Frame indication EFI when a time mark is reached 0B No CAN error has been detected in the last time window 1B A CAN error has been detected in the last time window REFTRG 10 rh Reference Trigger Flag This bit is set when the reference message of a TTCAN node is intended to be sent It is cleared ...

Page 1472: ...lower priority than the TTCAN node itself potential time master 0B A priority conflict has not been detected for the last reference message 1B The TTCAN node is a potential time master with a priority conflict the last reference message has been received with a lower priority than TTCR TMPRIO TRAF 14 rh Transmission Finished Flag This bit is set when the CAN node correctly terminates a transmissio...

Page 1473: ...ed a message MSCMIN 18 16 rh Minimum of MSC Bit Fields This bit field indicates the minimum value of the MSC bit fields of the message objects activated in exclusive time windows This value is set to 7 at the beginning of a new matrix cycle It is updated according to Note if MSC_cur MSCMIN then MSCMIN MSC_cur The value MSC_cur is the MSC value of the currently activated message object MSCMAX 22 20...

Page 1474: ...er Request This bit indicates the condition leading to the transmission of the next reference message only for the current time master The value of NIG is copied to ETR when a reference message is correctly transmitted It will be cleared automatically when the next reference message is correctly received 0B The next reference message will be transmitted when the corresponding time mark is reached ...

Page 1475: ... 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ETR EVR STE NIGSR CFGMEL r w w w w Field Bits Type Description CFGMEL 1 0 w Configuration Mode Enter Leave This bit field is used to enter leave the Configuration Mode 00B No action 01B The Configuration Mode will be entered set TTSR CFGM 10B The Configuration Mode will be left clear TTSR CFGM 11B No action NIGSR 3 2 w Next Is Gap Flag Set Reset This...

Page 1476: ... used to synchronize a TTCAN node by software 0B No action 1B The transmission of a reference message is triggered if TTCR ETESEL 11 and the system is in a gap ETREVR 5 w Reset External Trigger Event This bit clears the external trigger event flag 0B No action 1B The bit TTSR ETREV is cleared 0 31 6 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1477: ... rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description NMC 0 rwh New Matrix Cycle This bit indicates that a new matrix cycle has started It is set when a reference message with the cycle count 0 has been transferred correctly 0B A new matrix cycle has not yet been detected 1B A new matrix cycle has been detected NBC 1 rwh New Basic Cycle This bit indicates that a ...

Page 1478: ...rwh Watch Trigger Event1 This bit indicates a watch trigger event WTE This event is detected when the cycle time in CYCTMR CYCTM becomes equal to the watch trigger value given by the time mark of the BCE entry 0B The cycle time has not been equal to WTV 1B The cycle time has been equal to WTV IWTE 6 rwh Init Watch Trigger Event2 This bit indicates a watch trigger event WTE with the value of the In...

Page 1479: ...er reads an EOS entry In this case bit TTSR CFGM is automatically set 0B The TTCAN scheduler has not yet read an EOS entry 1B The TTCAN scheduler has read an EOS entry WFE 12 rwh Wait For Event Flag This bit is set when a reference message is received indicating a next is gap not for the current time master This event can generate a notification interrupt 0B The last reference message received was...

Page 1480: ...tion Error This bit indicates that a configuration error has been detected by the scheduler A configuration error is detected when an arbitration window is not closed when the BCE is reached When RME TMV is reached no other scheduler entries as RME and BCE are allowed See also EOSERR 0B A configuration error has not been detected 1B A configuration error has been detected S3 error condition TURERR...

Page 1481: ...bit TTIRR NBC or bit TTIRR NMC become set independent of its current state 00B A new basic or matrix cycle interrupt is disabled 01B A basic cycle interrupt is generated whenever TTIRR NBC becomes set 10B A matrix cycle interrupt is generated whenever TTIRR NMC becomes set 11B Reserved Bit field TTINPR NBCINP selects the interrupt output line that becomes activated at this type of interrupt TENWER...

Page 1482: ...t interrupt is disabled 1B Watch trigger event interrupt is enabled Bit field TTINPR ERRINP selects the interrupt output line that becomes activated at this type of interrupt AWDIE 7 rw Application Watchdog Interrupt Enable AWDIE enables the application watchdog interrupt This interrupt is generated when TTIRR AWDERR becomes set independent of its current state 0B Application watchdog interrupt is...

Page 1483: ...able SYNCSCIE enables the synchronization state change interrupt This interrupt is generated when bit field TTSR SYNCSC changes its state 0B Synchronization state change interrupt is disabled 1B Synchronization state change interrupt is enabled Bit field TTINPR NOTIFINP selects the interrupt output line that becomes activated at this type of interrupt SEIE 11 rw Scheduler Error Interrupt Enable SE...

Page 1484: ...es the notification interrupt This interrupt is generated whenever bits TTIRR WFE or TTIRR DISC are set by hardware 0B Notification interrupt is disabled 1B Notification interrupt is enabled Bit field TTINPR NOTIFINP selects the interrupt output line which becomes activated at this type of interrupt 0 5 4 31 13 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1485: ...Type Description ERRINP 3 0 rw Error Interrupt Node Pointer ERRINP selects the interrupt output line INT_Om m 0 15 for an error interrupt Possible error events for this interrupt node pointer are Transmit enable window error event Transmit trigger error event Initial Watch trigger event Application watchdog event TUR adjust error Scheduler error event 0000B Interrupt output line INT_O0 is selected...

Page 1486: ...tput line INT_O1 is selected B 1110B Interrupt output line INT_O14 is selected 1111B Interrupt output line INT_O15 is selected NOTIFINP 11 8 rw Notification Interrupt Node Pointer NOTIFINP selects the interrupt output line INT_Om m 0 15 for a notification interrupt Possible notification events for this interrupt node pointer are bit field TTSR ERRS changes bit field TTSR MSR changes bit field TTSR...

Page 1487: ...7 6 5 4 3 2 1 0 0 STPTR r rw Field Bits Type Description STPTR 6 0 rh Start Pointer This bit field determines the location of the first scheduler entry for TTCAN node 0 The value determines how many entries counted in units of 32 bits the first TME entry TME1 for this TTCAN node is located below the last address of the scheduler memory If two or more TTCAN nodes are implemented all start pointers ...

Page 1488: ...tries STSRL Scheduler Timing Status Register Low 2F0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BCETMV rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMETMV rh Field Bits Type Description RMETMV 15 0 rh Time Mark Value from RME This bit field indicates the compare value for the next time mark defined by an RME This value is valid only if SISR ICF 1 and SISR RMEV 1 BCETMV 31 ...

Page 1489: ...0 rh Time Mark Value from TME This bit field indicates the compare value for the next time mark defined by an TME This value is valid only if SISR ICF 1 and SISR TMEV 1 RCEMSGNR 23 16 rh Receive Control Entry Message Number This bit field indicates the collected RCEMSGNR information from an RCE This value is taken into account only if SISR ICF 1 and SISR RCEV 1 TCEMSGNR 31 24 rh Transmit Control E...

Page 1490: ... 7 6 5 4 3 2 1 0 ICF GM ARBM ALTMSG TR EN CH EN IEN REC F1 IEN REC F0 IEN TRA F1 IEN TRA F0 INP rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description INP 3 0 rh Interrupt Node Pointer This bit field indicates the collected INP information This value is taken into account only when at least one of the four interrupt requests is enabled IENTRAF0 4 rh Interrupt Enable if TRAF 0 This bit field ...

Page 1491: ... This bit field indicates the collected ARBM information from an TME or an ARBE GM 14 rh Gap Mode This bit field indicates the collected GM information from an RME or an BCE only valid if RME or a BCE has been found ICF 15 rh Instruction Collection Finished This bit field indicates that the instruction collection is finished for a time window It is automatically cleared when a time mark is reached...

Page 1492: ...n collection for this time window It is automatically cleared when a time mark is reached 0B The bit fields TREN ALTMSG and TCEMSGNR are invalid They are not taken into account for the next time window 1B The bit fields TREN ALTMSG and TCEMSGNR are valid They are taken into account for the next time window ICEV 18 rh Interrupt Control Entry Valid This bit indicates that a valid interrupt control e...

Page 1493: ...ME has been found RMEV 21 rh Reference Mark Entry Valid This bit indicates that a valid reference mark entry has been found during the instruction collection for this time window It is automatically cleared when a time mark is reached 0B No valid RME has been found 1B A valid RME has been found BCEV 22 rh Basic Cycle End Entry Valid This bit indicates that a valid basic cycle end entry has been fo...

Page 1494: ...he GPTA modules External trigger events for the TTCAN can be generated by the GPTA0 the External Request Unit located in the SCU or directly through to pins CAN interrupts are able to trigger DMA transfers and GPTA operations Figure 22 38 CAN Module Implementation and Interconnections MultiCAN Module Kernel MCA05864 Port 6 Control CAN Node 1 CAN Control Message Object Buffer 128 Objects Timing Con...

Page 1495: ...al Registers The registers listed in Figure 22 39 are not included in the MultiCAN module kernel but must be programmed for proper operation of the MultiCAN module Figure 22 39 CAN Implementation specific Special Function Registers CAN_CLC MCA05865 P6_IOCR8 Clock Control Registers Port Registers P6_IOCR12 P6_PDR CAN_SCRm Interrupt Registers CAN_FDR m 0 15 ...

Page 1496: ...al to the system clock frequency fSYS The clock control register CAN_CLC makes it possible to enable disable fCLC under certain conditions The module timer clock fCAN is used inside the MultiCAN module as input clock for all timing relevant operations e g bit timing The settings in the CAN_FDR register determine the frequency of the module timer clock fCAN according the following two formulas 22 1...

Page 1497: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for OCDS Used to enable the Suspend M...

Page 1498: ...11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate Suspend Mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in Suspend Mode DM 15 14 rw Divider Mode This bit field selects normal divider mode fract...

Page 1499: ...nal details on the fractional divider register functionality are described in section Fractional Divider Operation on Page 3 29 of the TC1796 User s Manual System Units part Volume 1 DISCLK 31 rwh Disable Clock Hardware controlled disable for fOUT signal 0 10 27 26 rw Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1500: ...racteristics such as pull up down devices port direction input output open drain and alternate output selections The I O lines for the MultiCAN module are controlled by the port input output control registers P6_IOCR8 and P6_OCR12 Table 22 16 shows how bits and bit fields must be programmed for the required I O functionality of the CAN I O lines Table 22 16 MultiCAN I O Control Selection and Setup...

Page 1501: ...ut output control for P6 10 RXDCAN1 Port input output control for P6 11 TXDCAN1 1 Coding of bit fields see Table 22 17 Shaded bits and bit fields are don t care for CAN I O port control P6_IOCR12 Port 6 Input Output Control Register 12 1CH Reset Value 2020 2020H 31 28 23 20 15 12 7 4 0 PC15 0 PC14 0 PC13 0 PC12 0 rw r rw r rw r rw r Field Bits Type Description PC12 PC13 PC14 PC15 7 4 15 12 23 20 3...

Page 1502: ...ultiCAN I O Lines PCx 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function 0X00B Input No pull device connected 0X01B Pull down device connected 0X10B 1 1 This bit field value is the default after reset Pull up device connected 0X11B No pull device connected 1001B Output Push pull Output function ALT1 1101B Open drain Output function ALT1 Table 22 18 Receive Input Sel...

Page 1503: ...1 0 PD SSC1 0 0 0 r rw r rw r rw r rw r Field Bits Type Description PDCAN01 26 24 rw Pad Driver Mode for P6 9 TXDCAN0 and P6 11 TXDCAN11 1 Coding of bit field see Table 22 19 Shaded bits and bit fields are don t care for CAN I O port control PDCAN23 30 28 rw Pad Driver Mode for P6 13 TXDCAN2 and P6 151 TXDCAN3 Table 22 19 Pad Driver Mode Mode Selection Class A2 Pads PDx Bit Field Driver Strength S...

Page 1504: ... requestor and are able to trigger DMA transfers INT_O 2 0 are connected to the DMA controller as shown in Table 22 21 Table 22 20 External CAN Time Trigger Inputs Receive Input Connected to From Module ECTT1 P1 3 REQ3 Input Port 1 ECTT2 P7 5 REQ7 Input Port 7 ECTT3 Output OUT5 GPTA0 ECTT4 Output IOUT2 External Request Unit SCU ECTT5 Output IOUT3 External Request Unit SCU ECTT6 0 ECTT7 0 Table 22 ...

Page 1505: ...e software initiated interrupt register MITR Each of the 274 hardware initiated interrupt sources is controlled by a 4 bit interrupt pointer that directs the interrupt source to one of the sixteen interrupt outputs INT_Om m 0 15 This makes it possible to connect more than one interrupt source to one interrupt output line The interrupt wiring matrix shown in Figure 22 41 is built up according to th...

Page 1506: ...867 4 bit Interrupt Pointer Interrupt Source 1 Interrupt Request Output INT_Om 0000 1111 147 Inputs Interrupt Pointer Control Interrupt Output Control CAN Node 0 CAN Node 3 16 TTCAN 16 Outputs INT_O0 INT_O1 INT_O14 INT_O15 Register MITR 4 16 16 16 16 16 16 16 16 16 16 16 148 148 148 148 1 1 1 1 Interrupt Wiring Matrix 16 16 Message Object 0 16 16 Message Object 127 ...

Page 1507: ...tem Units part Volume 1 Some of the sixteen interrupt outputs of the MultiCAN module can be used to trigger operations in the DMA controller and the GPTA module CAN_SRCm m 0 15 CAN Service Request Control Register m 0FCH m 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bi...

Page 1508: ...ed with a parity error detection logic that makes it possible to detect parity errors In case of a parity error a NMI is generated At a power on reset operation the corresponding MultiCAN module memories are initialized automatically Therefore unlike other TC1796 on chip memories the MultiCAN module memories must not be initialized by a user program before it can be enabled for parity error detect...

Page 1509: ...neral implementation specific registers for clock control module identification and interrupt service request control and adds the absolute address information Figure 22 42 Complete MultiCAN Module Register Address Map with TTCAN MCA05868_mod General Module Control Registers MultiCAN Registers F000 4000H F000 4100H Clock Control Register Module Identification Reg Fractional Divider Register 00H 08...

Page 1510: ... Functional description of the MLI see Page 23 2 Module kernel description see Page 23 25 Operation the MLI module see Page 23 67 MLI kernel register descriptions see Page 23 75 Device implementation specific descriptions and details see Page 23 124 Note The MLI kernel register names described in Section 23 3 are referenced in the TC1796 User s Manual by the module name prefix MLI0_ for the MLI0 i...

Page 1511: ... MLI is a fast synchronous serial interface to exchange data between microcontrollers or other devices such as stand alone peripheral components Figure 23 1 shows how two microcontrollers are typically connected together via their MLI interfaces Figure 23 1 Typical Micro Link Interface Connection Features Synchronous serial communication between an MLI transmitter and an MLI receiver Different sys...

Page 1512: ...flow transmission or reception except for Read Frames always transmitted by the Local Controller and Answer Frames always transmitted by the Remote Controller Due to the full duplex operation capability of an MLI module independent transmitter and receiver each microcontroller with an MLI module is able to operate as a Local Controller e g for data transmission as well as a Remote Controller e g f...

Page 1513: ...n the address space of the receiving controller Remote Window parameters base address and size of the receiving controller are programmable by the transmitting microcontroller by MLI transfers independently for each pipe Each Remote Window of a receiving controller is related to specific Transfer Window of the transmitting controller The Remote Windows are the logical data outputs of the MLI recei...

Page 1514: ...triggers actions in the MLI receiver Offset The offset is an address distance relative to the base address of the Transfer Window in the transmitting controller and the base address of the Remote Window in the receiving controller For example a write access to the 10th byte of the Transfer Window is transferred to a write to the 10th byte of the Remote Window The offset of a write access to a Tran...

Page 1515: ... been written to the Transfer Window together with the write offset to the MLI of the receiving controller The receiving controller stores the data internally and can also automatically place the data in the Remote Window of the receiving controller at the address location defined by the write offset plus the base address Read Access from a Transfer Window A read access from a location of a Transf...

Page 1516: ... Transfer Window can be accessed at both address locations its LTW and its STW Figure 23 3 Transfer Remote Window Assignment Example During initialization of the pipes base addresses and sizes of the Remote Windows are transmitted from the Local Controller to the Remote Controller In the example of Figure 23 3 pipe 1 and pipe 2 cover the full range of their Transfer and Remote Windows The ranges o...

Page 1517: ...dress part and additional variable address part The variable address part is determined by the available address area for each Remote Window also named buffer size value of BSx buffer size for Remote Window x indicates how many address bits are variable defining the available address range Figure 23 4 Base Address Definition of Remote Windows MLI_Rwindow_BAC Base Adresses of the four Pipes BS0 1 3...

Page 1518: ...ed and taken as lower address bits of the target address the upper address bits are given by the Remote Window s base address Figure 23 5 Remote Window Address Generation without Address Prediction Figure 23 6 Remote Window Address Generation with Address Prediction MLI_Rwindow_offs Transfer Window Pipe x BSx 31 0 Remote Window Pipe x BSx 1 0 MLI Transmitter Offset BSx 31 0 Offset MLI Receiver 1 R...

Page 1519: ...see Page 23 15 Optimized Read Frame to transmit the read request without read offset in case of an address prediction match see Page 23 16 Command Frame to transmit a command e g setup information or MLI service request generation see Page 23 17 Answer Frame to transmit the data previously requested by a Read Frame see Page 23 18 The local remote structure of an MLI connection between two microcon...

Page 1520: ... to the frame content the value of PN is defined as 00B for pipe 0 01B for pipe 1 10B for pipe 2 and 11B for pipe 3 The FC parameter is coded according to Table 23 1 If more than one frame type is defined with the same frame code value see FC 01H 10H or 11H the width of the received frame defines the type The value given by m in the table below represents the number of address bits transferred as ...

Page 1521: ...8 most significant bits of the 32 bit base address bits can be programmed by the transmitting controller the 4 LSBs are considered as 0 The base address of a Remote Window has to be aligned to its size e g a window of 1 Kbyte has to start at 1Kbyte address boundaries Remote Window size The size is defined by the 4 bit coded buffer size BS The maximum size is 64 Kbytes Parity bit P Figure 23 9 Copy...

Page 1522: ...ransfer Window that has been the target of the write operation m Bits of write offset These bits define the write offset The value of m depends on the size of the Remote Window defined by the Copy Base Address Frame m 1 16 Write data field The write data field can be 8 bit 16 bit or 32 bit wide depending on the data width of the write access to the Transfer Window Parity bit P Figure 23 10 Write O...

Page 1523: ...andwidth than Write Offset and Data Frames because they are shorter An optimized frame is only possible if the predicted address matches with the actually written one The Optimized Write Frame contains the following parts Header The header starts with frame code FC 11B followed by the pipe number PN of the Transfer Window that has been the target of the write operation Write data field The write d...

Page 1524: ...een the target of the read operation m Bits of write offset These bits define the read offset The value of m depends on the size of the Remote Window defined by the Copy Base Address Frame m 1 16 Data Width DW The data width DW indicates if the read from the Transfer Window was a 8 bit 16 bit or 32 bit read action It defines how many bytes have to be delivered to the Local Controller by the Answer...

Page 1525: ...Frame contains the following parts Header The header starts with frame code FC 11B followed by the pipe number PN of the Transfer Window that has been the target of the read operation Data Width DW The data width DW indicates if the read from the Transfer Window was a 8 bit 16 bit or 32 bit read action It defines how many bytes have to be delivered to the Local Controller by the Answer Frame Same ...

Page 1526: ... bit field is pipe specific and depends on the transmitted pipe number x Parity bit P Figure 23 14 Command Frame More details on the Command Frame handling of the MLI module are described on Page 23 39 Table 23 4 PN for Command Coding Pipe Number PN Command Type 00B Activate MLI service request or other control signal s of the receiving controller The definition which signal becomes activated is d...

Page 1527: ...cal Controller to request data from the Remote Controller The Answer Frame contains the following parts Header The header starts with frame code FC 10B followed by the pipe number PN The value of PN is taken from the Read Frame that has triggered the Answer Frame Read data field The read data field can be 8 bit 16 bit or 32 bit wide depending on the data width requested by the Read Frame that trig...

Page 1528: ... MLI connection allows high data rates and at the same time supports significant signal propagation delays between the transmitter and the receiver As shown in Figure 23 16 each output signal passes through the port stage reaches the physical interface line between the MLI modules enters via an input stage and can be finally evaluated All these steps introduce an accumulating propagation delay In ...

Page 1529: ...als parallel connection to the Remote Controllers whereas the handshake signals VALID and READY have to be established as independent signal pairs for each device As a result a Local Controller only needs one CLK and one DATA output but an individual set of READY and VALID handshake signals for each Remote Controller Please note that Read Frames and Answer Frames are based on an established connec...

Page 1530: ...dges of TCLK whereas sampling on the receiver side takes place with falling edges of RCLK Transmitter valid handshake VALID This signal indicates the start and the end of each frame It is active 1 level during a frame transmission and passive 0 level while no frame is transferred Changes of TVALID on transmitter side take place with rising edges of TCLK whereas sampling of RVALID on the receiver s...

Page 1531: ...he MLI transmitter checks its TREADY input with each rising edge of TCLK after TVALID has become 0 and increments a counter This counter is started from 0 at the end of a frame transmission TVALID becomes 0 and counts TCLK periods Ready Delay Time Counter If the condition TREADY 1 is detected before the programmed Ready Delay Time has elapsed the MLI receiver has indicated a frame reception withou...

Page 1532: ...shake signal TREADY After TVALID has been asserted to 1 the transmitter checks the receiver s acknowledge TREADY becoming 0 A Non Acknowledge error condition is detected by the transmitter when at the end of a frame transmission the TREADY signal is still at high level TREADY 1 when TVALID becomes 0 Figure 23 19 shows the Non Acknowledge error case In this case the transmitter automatically sends ...

Page 1533: ...e different prediction values can be handled in parallel for the different pipes The MLI transmitter can compare the offset of each Transfer Window read or write access with the offset of the previous access to the same Transfer Window Between the accesses to a specific window other windows can be accessed without disturbing the prediction Bigger offset differences than 512 bytes are not supported...

Page 1534: ... MLI service request structure see Page 23 55 The MLI transmitter events see Page 23 57 The MLI receiver events see Page 23 60 The baud rate generation see Page 23 65 23 2 1 Frame Handling The frame handling is based on receiver and transmitter registers and the Transfer Windows Depending on the type of access to the Transfer Windows different actions take place inside the MLI module Please refer ...

Page 1535: ...the following actions for pipe x Bit field TPxBAR BS 4 bit coded buffer size is loaded into bit field TPxSTATR BS MCA05888_mod Transmitting MLI Controller Receiving MLI Controller MLI Transmitter Ready TPxBAR is written TPxSTATR BS TPxBAR BS TCBAR ADDR TPxBAR ADDR TRSTATR PN x TRSTATR BAV 1 Send Copy Base Address Frame of pipe x RPxBAR ADDR Base address 28 bit RPxSTATR BS Buffer size 4 bit RCR TF ...

Page 1536: ...ll be suppressed automatically by hardware for the next two data frames This ensures a correct offset prediction afterwards Receiving Controller When a Copy Base Address Frame for pipe x has been received correctly and acknowledged the following actions are executed in the MLI receiver The received 28 most significant address bits are written into the receiver pipe x base address register bit fiel...

Page 1537: ...ATA Data TPxSTATR DW Width TRSTATR DVx 1 TRSTATR DVx 0 TISR NFSIx 1 Normal Frame Sent x Event TREADY 1 Send Write Offset and Data Frame of pipe x Address Prediction Calculate TPxSTATR AP and TPxSTATR OP TPxSTATR OP 0 TCR NO 1 yes yes no no Send Optimized Write Frame of pipe x MLI Receiver Ready Pipe x initialized RADRR ADDR RPxBAR ADDR RPxBAR modified by Offset RADRR ADDR RPxBAR ADDR RPxBAR ADDR R...

Page 1538: ...mission of a Write Offset and Data Frame is started as soon as the MLI transmitter is idle no higher priority frames are pending and TREADY 1 If the address prediction method is enabled TCR NO 0 a Write Offset and Data Frame is started only if an address prediction is not possible indicated by TPxSTATR OP 0 If TPxSTATR OP 1 an address prediction is possible in the MLI transmitter and the MLI recei...

Page 1539: ...t Offset Address m Bit Offset Address 0 2 12 m 3 1 4 0 2 3 1 4 20 m 0 2 3 1 4 36 m TPxSTATR DW 00B TPxSTATR DW 01B TPxSTATR DW 10B TPxDATAR DATA 7 0 TPxDATAR DATA 15 0 TPxDATAR DATA 31 0 Header Header Header TPxAOFR AOFF TPxAOFR AOFF TPxAOFR AOFF MCA05884 x P 8 Bit Data 1 TPxDATAR DATA 7 0 1 x P 16 Bit Data 1 TPxDATAR DATA 15 0 1 x P 32 Bit Data 1 TPxDATAR DATA 31 0 1 Header Header Header x Pipe N...

Page 1540: ...e Received event is set and an SR output line is activated if enabled by RIER NFRIE 01B or 10B After these actions related to the reception of a Write Frame by the receiving controller the data that has been received from the transmitting controller is ready to be written into the Remote Window related to the receiving pipe This write operation can be executed in two ways RCR MOD 0 Automatic Data ...

Page 1541: ...e If the move engine operation is finished frame execution and reception continue normally If Automatic Data Mode is disabled no blocking mechanism has been implemented The receiving controller software has to take care to deal with the received data before it is overwritten by new incoming frames 23 2 1 3 Read Frames Read Frames transmit read request and optionally the read offset from the Local ...

Page 1542: ... Ready Pipe x initialized TRSTATR DVx 0 TISR NFSIx 1 TREADY 1 Send Discrete Read Frame of pipe x TRSTATR AV 0 TREADY 1 RDATAR DATA Read Data RCR DW Width RCR TF 11B TRSTATR RPx 0 RISR NFRI 1 Address Prediction Calculate TPxSTATR AP and TPxSTATR OP TPxSTATR OP 0 TCR NO 1 yes yes no no Parity check acknowledge frame Parity check acknowledge frame Send Optimized Read Frame of pipe x Normal Frame Rece...

Page 1543: ...address prediction method is enabled TCR NO 0 a Discrete Read Frame is started only if an address prediction is not possible indicated by TPxSTATR OP 0 If TPxSTATR OP 1 an address prediction is possible and an Optimized Read Frame is started Status flag TRSTATR DVx is cleared by hardware and MLI event status flag TISR NFSIx Normal Frame Sent event in pipe x is set and a service request output is a...

Page 1544: ...STATR AP to the actual address stored in RPxBAR ADDR The result of this addition is stored in RADRR ADDR and also in RPxBAR ADDR and represents the destination address in the Remote Controller from where data should be read The transmitted data width DW is written into bit field RCR DW The information about the received frame type 01B for a Read Frame is written into bit field RCR TF MLI event sta...

Page 1545: ...bus master e g CPU or PCP must then take care of the remote window read operation and the data transfer to TDRAR After TDRAR DATA has been updated status flag TRSTATR AV of the Remote Controller is set and the transmission of an Answer Frame is started Figure 23 29 Read Frame Handling on Remote Side Note In Automatic Data Mode Read Frames are leading to a read action executed by the MLI move engin...

Page 1546: ...n detected the Local Controller software has to clear the TRSTATR RPx bit by writing 1 to SCR CDVx and can start a new Read Frame Remote Controller Receiving the read request The Answer Frame is the only frame sent from the Remote Controller back to the Local Controller The transmitter registers of the Remote Controller are used to generate the Answer Frame Every time the transmitter data read ans...

Page 1547: ... enabled by RIER NFRIE 01B or 10B The content of RADRR becomes invalid The data that has been previously requested from the Remote Controller by a Read Frame is now available in RDATAR and can be read by a bus master e g the CPU of the Local Controller If an Answer Frame is received while the corresponding TRSTATR RPx bit is 0 the reception is declared as unintended and a Discarded Read Answer eve...

Page 1548: ...23 31 Command Frame Transaction Flow TREADY 1 MCA05889_mod Transmitting MLI Controller Receiving MLI Controller MLI Transmitter Ready TCMDR CMDPx is written TRSTATR CV 1 Send Command Frame of pipe x x Code Pipe 0 generate interrupt at SR 3 0 RISR IC 1 MLI Receiver Ready TRSTATR CV 0 TISR CFSIx 1 Command Frame Sent in Pipe x Event Interrupt Command Frame Event Pipe x RISR CFRIx 1 Command Frame Rece...

Page 1549: ...s that are transmitted by a Command Frame and that cause a specific control task in the MLI receiver The received PN value is checked and the corresponding control actions are executed according to Table 23 5 Independent of the received Pipe Number event status flag RISR CFRIx Command Frame Received event in pipe x is set and a service request output is activated if enabled by RIER CFRIEx 1 If a C...

Page 1550: ...receiving MLI set RCR MOD 1 0010B Disable Automatic Data Mode in receiving MLI set RCR MOD 0 0100B Clear bit TRSTATR RP0 in receiving MLI 0101B Clear bit TRSTATR RP1 in receiving MLI 0110B Clear bit TRSTATR RP2 in receiving MLI 0111B Clear bit TRSTATR RP3 in receiving MLI 1111B Generate break output signal BRKOUT in receiving MLI if enabled by RCR BEN 1 others no effect reserved for future use 11B...

Page 1551: ...time see Page 23 71 Note There is no protection against frames where more than one bit is corrupted e g shortened frames In such a case an unpredicted behavior of the MLI module may occur Transmitting Controller The MLI transmitter counts the detected parity error conditions and generates a parity error event if a programmable number max 16 of parity error conditions has occurred A parity error co...

Page 1552: ...ty bit of a received frame for even parity A receiver parity error condition is detected if the received parity bit does not match with the internally calculated one If no receiver parity error condition is found after the reception of a frame RREADY is immediately set to 1 otherwise RREADY is kept at 0 until a defined number of RCLK cycles determined by bit field RCR DPE delay for parity error ha...

Page 1553: ... a 1 to bit SCR CRPE The receiver parity error flag RCR PE is cleared by hardware after a correct frame reception It can be cleared by software by writing a 1 to bit SCR CRPE The software can check for accumulated parity error conditions by reading RCR MPE or RISR PEI for the status of the latest received frame it can check RCR PE The delay for parity error bit field RCR DPE is a read only bit fie...

Page 1554: ...method can be enabled to support communication between MLI transmitter and MLI receiver without sending address offset information in the frames to optimize the required MLI bandwidth This feature reduces the required bandwidth for MLI communication Both communication partners MLI transmitter and the MLI receiver are able to detect regular offset differences of consecutive window accesses to the s...

Page 1555: ... of the Remote Window and the number m of offset bits are given by RPxSTATR BS The bit positions RPxBAR 31 m are kept constant whereas the bit positions RPxBAR m 1 0 are replaced 23 2 2 4 Automatic Data Mode The MLI module supports automatic data transfers for read or Write Frames without any CPU load in the receiving controller This features is based on a move engine block providing the data the ...

Page 1556: ...sub ranges to limit accesses to specific parts of bigger memory areas There is a maximum of 32 fixed address ranges available that can be individually enabled disabled by the address range enable bits AER AENx x 0 31 If bit AER AENx is set read write accesses to the associated address range x are supported in automatic mode If bit AENx is cleared read write accesses to the associated address range...

Page 1557: ...he same applies for the base address copy frame Answer Frame only one frame pending allowed at a time Software driven Command Frames CV0 before CV1 before CV2 before CV3 Read or Write Frames DV0 before DV1 before DV2 before DV3 Base Address Copy Frame only one frame pending allowed at a time 23 2 2 7 Transmission Delay A transmission delay can be introduced in the transmitter between the detection...

Page 1558: ...grammed the waveform diagrams have to be interpreted accordingly In order to avoid naming mismatches the signals keep their names although a polarity inversion might have been programmed If desired polarity inversions for the same signal have to be programmed in the transmitter and in the receiver to guaranty signal consistency there has always to be an even number of inversions between an MLI tra...

Page 1559: ... is implementation specific and can be used for example to generate a break condition in the on chip debug support logic or trigger other functions This signal is activated as a pulse by a Command Frame The service request outputs SR 7 0 of the MLI module can be activated as a pulse by transmitter or receiver events for all SRx as well as by Command Frames only for SR 3 0 ...

Page 1560: ...trol Logic 23 2 3 2 Receiver I O Line Control Figure 23 36 shows the MLI receiver I O control logic MCA05886_mod TVALID TDATA TCLK TVALIDB TVEB 1 0 TVPB TDATA 1 0 TRS TREADYA TREADYB TREADYC TREADYD TRP 1 0 TRE TREADY MLI Transmitter MLI Transmitter I O Control Logic Note All control bits shown in this figure are located in register OICR TVALIDA TVEA 1 0 TVPA TVALIDD TVED 1 0 TVPD TVALIDC TVEC 1 0...

Page 1561: ... RREADYB 1 0 RRPB RVS RVALIDA RVALIDB RVALIDC RVALIDD RVP 1 0 01 10 11 00 RVE RVALID MLI Receiver MLI Receiver I O Control Logic Note All control bits shown in this figure are located in register OICR RREADYA 1 0 RRPA RREADYD 1 0 RRPD RREADYC 1 0 RRPC RRS 01 10 11 00 RCS RCLKA RCLKB RCLKC RCLKD RCP 1 0 01 10 11 00 RCE RDS RDATAA RDATAB RDATAC RDATAD RDP 1 0 01 10 11 00 2 2 2 2 ...

Page 1562: ...te Controller is accessed Only one receiver being available in the Local Controller the reception of data can be handled only either from one or the other Remote Controller The software has to ensure that only one Remote Controller sends data back to the Local Controller e g by using Read Frames or by enabling disabling the generation of Write Frames in the Remote Controllers Figure 23 37 Connecti...

Page 1563: ...mote Controller to the Local Controller without using Read Frames In a ring structure the Read Frame handling should be avoided It is possible for the Local Controller to access both Remote Controllers independently For example the Remote Window of pipe x covers the address range of Remote Controller X whereas pipe y targets the Transfer Window y of Remote Controller X In Remote Controller Y the p...

Page 1564: ...t enable registers TIER for transmitter events or RIER for receiver events These two registers also contain the enable control bits that allow each event source to be enabled disabled individually for service request activation Each event can be connected to exactly one of the eight service request outputs SR 7 0 by a 3 bit interrupt node pointer One additional register the Global Interrupt Set Re...

Page 1565: ... inputs are connected to the demultiplexers of the MLI event specific lines Furthermore a service request output SRx can be triggered by software if the corresponding interrupt set bit in register GINTR is written with a 1 Figure 23 38 Service Request Compressor MCA05904_mod Node Pointer TINPR Service Request Output SR0 001 010 011 000 Transmitter Event with own Node Pointer To SR1 OR Gate To SR2 ...

Page 1566: ...ollowing MLI events Table 23 7 MLI Transmitter Events Events Events combined to See Parity Error Parity Time out Error Page 23 58 Time out Error Normal Frame Sent in Pipe 0 Normal Frame Sent in Pipe 0 Page 23 58 Normal Frame Sent in Pipe 1 Normal Frame Sent in Pipe 1 Normal Frame Sent in Pipe 2 Normal Frame Sent in Pipe 2 Normal Frame Sent in Pipe 3 Normal Frame Sent in Pipe 3 Command Frame Sent i...

Page 1567: ...ure 23 39 Parity Time out Error Event Logic 23 2 5 2 Normal Frame Sent x Event A Normal Frame sent in pipe x x 0 3 event is generated when a Normal Frame has been sent and correctly received in pipe x Figure 23 40 Normal Frame Sent in Pipe x Event Logic PEIE TIER PEIR MCA05896_mod Parity Time out Error Event TEIE TIER TEIR Software Clear Software Clear PEI TISR Set TEI TISR Set Parity Error Event ...

Page 1568: ...signed to each pipe All four pipe related Command Frame sent events are concatenated to one common Command Frame sent event Figure 23 41 Command Frame Sent Event Logic CFSI1 Control Logic CFSI1 Control Logic CFSI3 Control Logic CFSIE0 TIER CFSIR0 CFSI0 TISR Software Clear Set MCA05898_mod Command Frame Sent Event CFSI0 Control Logic Command Frame Sent in Pipe 0 Event Command Frame Sent in Pipe 1 E...

Page 1569: ...a Figure 23 42 Discarded Read Answer Event Logic Table 23 8 MLI Receiver Interrupts Events Events combined to See Discarded Read Answer Discarded Read Answer Page 23 60 Memory Access Protection Error Memory Access Protection Parity Error Page 23 61 Parity Error Normal Frame Correctly Received Normal Frame Received Page 23 62 Move Engine Access Terminated Interrupt Command Frame Interrupt Command F...

Page 1570: ...ed or if a programmable maximum number of receiver parity errors is reached Both MLI events have separate status control bits but are concatenated to one common error event Figure 23 43 Memory Access Protection Parity Error Event Logic MCA05900_mod MPEIE RIER MPEIR Software Clear PEIE RIER PEIR Software Clear Memory Protection Parity Error Event MPEI RISR Set PEI RISR Set Memory Protection Error E...

Page 1571: ... Answer Frame but not a Command Frame or if the move engine has terminated its read or write access Both event sources have separate status control bits but are concatenated to one common Normal Frame received event Figure 23 44 Normal Frame Received Event Logic NFRIE RIER NFRIR NFRI RISR Set MCA05901_mod RIER MEIR MEI RISR Set 0 Normal Frame Received Event 2 Software Clear Software Clear Normal F...

Page 1572: ...and Frame is received correctly on pipe 0 with a valid command code for service request output activation CMD 0000B to 0011B The received command code determines which of the service request outputs SR 3 0 should be activated Figure 23 45 Interrupt Command Frame Event Logic Interrupt Command Frame Event Set MCA05903_mod ICE RIER ICER IC RISR Software Clear 2 To SR0 To SR1 To SR2 To SR3 CMD PN 0 ...

Page 1573: ...r pipe related Command Frame received in pipe x events are concatenated to one common Command Frame received event Figure 23 46 Command Frame Received Event Logic Command Frame Received in Pipe 0 Event CFRIE0 RIER CFRIR0 CFRI0 RISR Software Clear Set MCA05902_mod Command Frame Received Event CFRI0 Control Logic 1 Command Frame Received in Pipe 1 Event CFRI1 Control Logic CFRI2 Control Logic CFRI3 ...

Page 1574: ...n the transition from 3FFH to 000H FDR RESULT represents the counter value and FDR STEP defines the reload value In order to achieve fMLI fSYS FDR STEP must be programmed with 3FFH The output frequency in normal divider mode is defined according the following equation 23 1 Fractional Divider Mode If the fractional divider mode is selected FDR DM 10B the clock fMLI is derived from the input clock f...

Page 1575: ...erwrite The value of register OICR and bit RCR RCVRST is overwritten by hardware in the next two clock cycles after a reset first OICR followed by RCR The value applied during reset is given in the register description This automatic overwrite allows adapting the module to different application requirements without changing the module itself For example during reset the receiver is set to a define...

Page 1576: ...pipes from the Local Controller s transmitter to the Remote Controller s receiver and the Remote Controller s receiver have to be initialized 3 The Remote Controller s transmitter has to be initialized by data write actions from the Local Controller via the Remote Controller s receiver to the Remote Controller s transmitter registers 4 The pipes from the Remote Controller s transmitter back to the...

Page 1577: ...he initial setting A can correspond to an inactive setting MLI not used for communication whereas the setting B is used for MLI communication In the case a memory access protection is implemented in the receiver and automatic handling of data is desired the user has to enable the corresponding address range in registers AER and ARR After a reset in most microcontrollers the access protection is ge...

Page 1578: ... be programmed There are two possibilities to get the MLI communication started First easier possibility is to write TCR MDP to 14 and to set RCR DPE to 15 The second possibility could be used to optimize the bandwidth of the MLI connection It is described in Section 23 3 5 on Page 23 71 23 3 3 Remote Receiver Setup The initialization of the Remote Controller s receiver is done by frames sent by t...

Page 1579: ...o be enabled by sending a Command Frame in pipe 2 with CM 0001B to set RCR MOD 1 in the Remote Controller 23 3 4 Remote Transmitter and Local Receiver Setup The initialization of the Remote Controller s transmitter and the Local Controller s receiver can be done by data frames sent by the local transmitter Therefore the Remote Controller s receiver has to be able to receive frames the port structu...

Page 1580: ...easured after the end of the frame is indicated in bit field TSTATR RDC The receiver participates in the control handshake by changing its RREADY output as a reaction to an incoming RVALID signal For the transmitter the TREADY input delivers the information that a receiver is connected and that it is ready for reception transfer only starts if TREADY 1 If a receiver is not able to handle the data ...

Page 1581: ...fter a module reset the transmitter can measure the loop delay and the receiver discards the frame without modification of DPE there is no difference in time between a frame with or without a parity error having been detected The value given by TSTATR RDC indicates how many TCLK cycles are necessary for a control handshake This value should be incremented by a value DELTA value see below and writt...

Page 1582: ...he DMA trigger inputs the Normal Frame sent events have to be enabled for service request activation and directed to the desired SRx outputs It is recommended to use only one type of MLI event per SRx output to trigger a data transfer by DMA If the DMA mechanism needs a start trigger for the first data word transfer register GINTR can be written with the appropriate pattern to activate an SRx outp...

Page 1583: ...y to program different buffer sizes the use of Read Frames or Command Frames In order to simplify the data handling by an SPI module the parity generation could be skipped for frames received by the SPI module and an error detection mechanism on an upper software layer could be implemented For frames sent by an SPI module the parity bit has to be calculated and sent correctly Otherwise the MLI rec...

Page 1584: ... to address locations inside the MLI address range not targeting the indicated registers are not allowed The complete and detailed address map of the of the MLI modules is described in Table 18 30 on Page 18 97 of the TC1796 User s Manual System Units part Volume 1 TPxBAR MCA06320_mod TPxAOFR TCBAR RPxBAR RADRR FDR TSTATR TPxSTATR TCDMR TRSTATR TCR RPxSTATR SCR TIER TISR TINPR RIER RISR RINPR GINT...

Page 1585: ... 4 Page 23 95 TCMDR Transmitter Command Register 28H Page 23 97 TRSTATR Transmitter Receiver Status Register 2CH Page 23 99 TPxAOFR Transmitter Pipe x Address Offset Register 30H x 4 Page 23 103 TPxDATAR Transmitter Pipe x Data Register 40H x 4 Page 23 101 TDRAR Transmitter Data Read Answer Register 50H Page 23 101 TPxBAR Transmitter Pipe x Base Address Register 54H x 4 Page 23 102 TCBAR Transmitt...

Page 1586: ...e Register A4H Page 23 117 RISR Receiver Interrupt Status Register A8H Page 23 120 RINPR Receiver Interrupt Node Pointer Register ACH Page 23 122 GINTR Global Interrupt Set Register B0H Page 23 83 OICR Output Input Control Register B4H Page 23 84 AER Access Enable Register B8H Page 23 88 ARR Access Range Register BCH Page 23 89 Table 23 10 Registers Overview MLI Kernel Registers cont d Register Sh...

Page 1587: ...ification Register 08H Reset Value 0025 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines t...

Page 1588: ...rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in suspend mode DM 15 14 rw Divider Mode This bit field selects norma...

Page 1589: ... on the fractional divider register functionality are described in section Clock Control Register CLC on Page 3 24 of the TC1796 User s Manual System Units part Volume 1 DISCLK 31 rwh Disable Clock Hardware controlled disable for fOUT signal 0 10 27 26 rw Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1590: ... 21 20 19 18 17 16 0 C NAE C TPE C RPE C AV 0 C BAV C MOD w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C CV3 C CV2 C CV1 C CV0 C DV3 C DV2 C DV1 C DV0 0 S MOD S CV3 S CV2 S CV1 S CV0 w w w w w w w w w w w w w w Field Bits Type Description SCVx x 0 3 x w Set Command Valid 0B No effect 1B Bit TRSTATR CVx is set SMOD 4 w Set MOD Flag 0B No effect 1B If CMOD 0 RCR is set If CMOD 1 RCR MOD is ...

Page 1591: ...CAV 24 w Clear AV Flag 0B No effect 1B Bit TRSTATR AV is cleared CRPE 25 w Clear Receiver PE Flag 0B No effect 1B Bit RCR PE is cleared CTPE 26 w Clear Transmitter PE Flag 0B No effect 1B Bit TSTATR PE is cleared CNAE 27 w Clear NAE Flag 0B No effect 1B Bit TSTATR NAE is cleared 0 7 5 23 18 31 28 w Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1592: ...ware control see Page 23 56 GINTR Global Interrupt Set Register B0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SI MLI7 SI MLI6 SI MLI5 SI MLI4 SI MLI3 SI MLI2 SI MLI1 SI MLI0 r w w w w w w w w Field Bits Type Description SIMLIx x 0 7 x w Set MLI Service Request Output Line x 0B No action 1B Service request output SRx is activa...

Page 1593: ...5 4 3 2 1 0 RVE TDP TCP TCE TRE TRP TRS TVP D TVP C TVP B TVP A TVE D TVE C TVE B TVE A rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description TVEA TVEB TVEC TVED 0 1 2 3 rw Transmitter Valid Enable These bits enable the module kernel output signals TVALIDx x A B C D to be driven by MLI transmitter output signal TVALID 0B TVALIDx is disabled and remains at passive level as select...

Page 1594: ...DYx is passive if 1 TREADYx if 0 TRE 11 rw Transmitter Ready Enable This bit enables the MLI transmitter input signal TREADY 0B TREADY signal is disabled always at 0 level 1B TREADY signal is enabled and driven by TREADYx according to the settings of TRS and TRP TCE 12 rw Transmitter Clock Enable This bit enables the module kernel output signal TCLK 0B TCLK is disabled and remains at passive level...

Page 1595: ...put signal RREADYx x A B C D that is driven by the MLI receiver output signal RREADY The RREADYx output signals that are not selected drives a passive level according to the setting of RRPx 00B RREADYA is selected 01B RREADYB is selected 10B RREADYC is selected 11B RREADYD is selected RRPA RRPB RRPC RRPD 18 19 20 21 rw Receiver Ready Polarity These bits determine the polarity of the module kernel ...

Page 1596: ...rted polarity for RCLKx selected RCLKx is at 0 level in passive state 1B Inverted polarity for TCLK selected RCLKx is at 1 level in passive state RCE 28 rw Receiver Clock Enable This bit enables the MLI receiver input clock RCLK 0B RCLK signal is disabled always at 0 level 1B RCLK signal is enabled and driven by RCLKx according to the settings of RCS and RCP RDS 30 29 rw Receiver Data Selector Thi...

Page 1597: ...N 26 AEN 25 AEN 24 AEN 23 AEN 22 AEN 21 AEN 20 AEN 19 AEN 18 AEN 17 AEN 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AEN 15 AEN 14 AEN 13 AEN 12 AEN 11 AEN 10 AEN 9 AEN 8 AEN 7 AEN 6 AEN 5 AEN 4 AEN 3 AEN 2 AEN 1 AEN 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description AENx x 0 31 x rw Address Range x Enable This bit enables the ...

Page 1598: ...ddress Slice 0 SLICE0 selects a specific sub range within address sub range 0 SIZE0 7 5 rw Address Size 0 SIZE0 determines the sub range size within address sub range 0 SLICE1 12 8 rw Address Slice 1 SLICE1 selects a specific sub range within address sub range 1 SIZE1 15 13 rw Address Size 1 SIZE1 determines the sub range size within address sub range 1 SLICE2 20 16 rw Address Slice 2 SLICE2 selec...

Page 1599: ...10H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TP NO MDP MNAE MPE 0 0 DNT MOD rw rw rw rwh rwh r rw rw rw Field Bits Type Description MOD 0 rw Mode of Operation This bit enables the MLI transmitter 0B The MLI transmitter is disabled 1B The MLI transmitter is enabled DNT 1 rw Data in Not Transmission This bit determines the level of the transmitter dat...

Page 1600: ...10B A parity error event is generated if 14 transmitter parity error conditions are detected 1111B A parity error event is generated if 15 transmitter parity error conditions are detected MNAE 9 8 rwh Maximum Non Acknowledge Errors This bit field determines the maximum number of consecutive Non Acknowledge error conditions that can be still detected in the transmitter until a time out event is gen...

Page 1601: ...enables disables the address prediction for Read or Write Frames see Page 23 45 0B Optimized method address prediction enabled 1B Optimized method address prediction disabled TP 15 rw Type of Parity This bit will determines the type of parity used in frame transmissions For correct data transfers TP 0 has to be programmed The value TP 1 can be selected to force parity errors to analyze the propaga...

Page 1602: ... is cleared to zero and starts counting up the TCLK clock periods until a TREADY high level is detected see Page 23 22 APN 6 5 rh Answer Pipe Number This bit field is written by the MLI receiver with the Pipe Number of a received Read Frame APN is used by an Answer Frame that is transmitted as response to the Read Frame 00B Pipe 0 is used in Answer Frame 01B Pipe 1 is used in Answer Frame 10B Pipe...

Page 1603: ...Flag This bit is set when a Non Acknowledge error condition is detected by the MLI transmitter after a frame transmission see Page 23 45 NAE is cleared by hardware if a transmitted frame has been acknowledged correctly Bit NAE can be cleared by software via bit SCR CNAE 0 31 9 r Reserved Read as 0 if read Field Bits Type Description ...

Page 1604: ...S further determines how many address offset bits are transmitted in a Write Offset and Data Frame or in a Discrete Read Frame When register TPxBAR is written for generation of a Copy Base Address Frame BS is updated by the Copy Base Address Frame see Page 23 26 0000B 1 bit offset address of Remote Window 0001B 2 bit offset address of Remote Window 0010B 3 bit offset address of Remote Window B 111...

Page 1605: ...lculation see Page 23 24 and Page 23 45 OP 16 rh Use Optimized Frame When address optimization is enabled with TCR NO 0 this bit indicates if address prediction is possible in the transmitter OP is written with each transmitter address prediction calculation see Page 23 24 and Page 23 45 0B No address prediction is possible A Write Offset and Data Frame or a Discrete Read Frame are used for transm...

Page 1606: ...w r rw r rw Field Bits Type Description CMDP0 3 0 rw Command Code for Pipe 0 This bit field contains the command code related to pipe 0 The pipe 0 command codes allow an activation pulse of one of the service request outputs SR 3 0 in the receiving controller 0001B Activate service request output SR0 0010B Activate service request output SR1 0011B Activate service request output SR2 0100B Activate...

Page 1607: ...ble Automatic Data Mode RCR MOD 0 0100B Clear bit TRSTATR RP0 0101B Clear bit TRSTATR RP1 0110B Clear bit TRSTATR RP2 0111B Clear bit TRSTATR RP3 1111B Activate a pulse at break output BRKOUT Other bit combinations are reserved for future use no further action occurs in the receiver CMDP3 27 24 rw Command Code for Pipe 3 This bit field contains the command code related to pipe 3 The command codes ...

Page 1608: ... 0 3 4 x rh Command Valid Bit is set by hardware when a TCMDR CMDPx bit field is written It is cleared by hardware when the Command Frame has been correctly transmitted CVx can be set or cleared by software via bits SCR SCVx or SCR CCVx AV 8 rh Answer Valid Bit is set by hardware when the TDRAR register in the the MLI transmitter in the Remote Controller is written AV is cleared by hardware when t...

Page 1609: ... Pending Bit is set by hardware when the TPxAOFR register of the MLI transmitter is updated after a read access to a Transfer Window of pipe x RPx is cleared by hardware when the MLI receiver in the Local Controller receives an Answer Frame for pipe x from the Remote Controller RPx can be cleared by software via bit SCR CDVx PN 25 24 rh Pipe Number This bit field indicates the Pipe Number x of the...

Page 1610: ...ter 40H 4H x Reset Value 0000 0000H 31 0 DATA rh Field Bits Type Description DATA 31 0 rh Data Whenever a location within a Transfer Window is written the data is loaded in this bit field TDRAR Transmitter Data Read Answer Register 50H Reset Value 0000 0000H 31 0 DATA rwh Field Bits Type Description DATA 31 0 rwh Data This bit field is loaded with data that is read from the address requested by a ...

Page 1611: ...R BS w w Field Bits Type Description BS 3 0 w Buffer Size This bit field determines the coded buffer size of the pipe x Remote Window in the receiving controller When writing TPxBAR BS is copied into bit field TPxSTATR BS 0000B 1 bit offset address of Remote Window 0001B 2 bit offset address of Remote Window 0010B 3 bit offset address of Remote Window B 1110B 15 bit offset address of Remote Window...

Page 1612: ...x TPxAOFR x 0 3 Transmitter Pipe x Address Offset Register 30H 4H x Reset Value 0000 0000H 31 16 15 0 0 AOFF r rh Field Bits Type Description AOFF 15 0 rh Address Offset Whenever a location within a Transfer Window is accessed read or written AOFF is loaded with the lowest 16 address bits of the access Also in the case of a small Transfer Window access all AOFF bits are loaded but AOFF 15 13 are n...

Page 1613: ... latest write access to TPxBAR ADDR TCBAR Transmitter Copy Base Address Register 64H Reset Value 0000 0000H 31 4 3 0 ADDR 0 rh r Field Bits Type Description ADDR 31 4 rh Address This bit field contains the 28 address bits written to TPxBAR ADDR This value will be transferred to the receiving controller to define the base address of the Remote Window for pipe x 0 3 0 r Reserved Read as 0 should be ...

Page 1614: ...rw rw rw rw rw rw rw rw rw rw Field Bits Type Description NFSIEx x 0 3 x rw Normal Frame Sent in Pipe x Interrupt Enable 0B Normal frame sent in pipe x event is disabled for activation of an SRx line 1B Normal frame sent in pipe x event is enabled for activation of an SRx line CFSIEx x 0 3 4 x rw Command Frame Sent in Pipe x Interrupt Enable 0B Command frame sent in pipe x event is disabled for ac...

Page 1615: ...g Clear 0B No action 1B Clear TISR NFSIx CFSIRx x 0 3 20 x w Command Frame Sent in Pipe x Flag Clear 0B No action 1B Clear TISR CFSIx PEIR 24 w Parity Error Flag Clear 0B No action 1B Clear TISR PEIx TEIR 25 w Time Out Error Flag Clear 0B No action 1B Clear TISR TEIx 0 15 10 31 26 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1616: ...Pipe x Flag 0B A Normal Frame has not yet been sent 1B A Write or Read Frame has been correctly sent and acknowledged for pipe x The service request output that can be activated by NFSIx is defined by TINPR NFSIPx CFSIx x 0 3 4 x rh Command Frame Sent in Pipe x Flag 0B A Command Frame has not yet been sent 1B A Command Frame has been correctly sent and acknowledged for pipe x The service request o...

Page 1617: ... This bit field determines which service request output SRx becomes active when a Normal Frame sent in pipe 0 event occurs if enabled 000B The service request output SR0 is selected 001B The service request output SR1 is selected B 110B The service request output SR6 is selected 111B The service request output SR7 is selected NFSIP1 6 4 rw Normal Frame Sent in Pipe 1 Interrupt Pointer This bit fie...

Page 1618: ... Coding see NFSIP0 CFSIP 18 16 rw Command Frame Sent Interrupt Pointer This bit field determines which service request output SRx becomes active when a Command Frame sent event occurs if enabled Coding see NFSIP0 PTEIP 22 20 rw Parity or Time Out Interrupt Pointer This bit field determines which service request output SRx becomes active when a parity time out event occurs if enabled Coding see NFS...

Page 1619: ...P3 DPE rh rh rh rh rh rh rh Field Bits Type Description DPE 3 0 rh Delay for Parity Error DPE determines the number of RCLK clock periods that the MLI receiver waits before the RREADY signal is raised again when it has detected a parity error see Page 23 22 When a pipe 1 Command Frame is received by the MLI receiver the command code is stored in this bit field see Page 23 39 0000B Zero RCLK clock ...

Page 1620: ...DATAR register DW indicates the relevant data width 00B 8 bit relevant data width in RDATAR 01B 16 bit relevant data width in RDATAR 10B 32 bit relevant data width in RDATAR 11B Reserved TF 12 11 rh Type of Frame This bit field determines the frame type that has most recently been received by the MLI receiver It is updated whenever the MLI receiver updates RDATAR RADDR or RPxBAR The most recently ...

Page 1621: ...d if 1 receiver error condition is detected 0001B A receiver parity event is generated if 1 receiver error condition is detected 0010B A receiver parity event is generated if 2 receiver error conditions are detected B 1110B A receiver parity event is generated if 14 receiver error conditions are detected 1111B A receiver parity event is generated if 15 receiver error conditions are detected BEN 20...

Page 1622: ...s Type Description BS 3 0 rh Buffer Size This bit field indicates the size of pipe x Remote Window in the receiving controller It is updated by hardware when a Copy Base Address Frame has been received see Page 23 26 0000B 1 bit offset address of Remote Window 0001B 2 bit offset address of Remote Window 0010B 3 bit offset address of Remote Window B 1110B 15 bit offset address of Remote Window 1111...

Page 1623: ...e or an Answer Frame RDATAR Receiver Data Register 90H Reset Value 0000 0000H 31 0 DATA rh Field Bits Type Description DATA 31 0 rh Data In the receiving controller DATA contains the data received by a Write Frame or an Answer Frame Bit field RCR DW determines the width of the relevant data that is stored in RDATAR RCR DW 00B RDATAR 7 0 are relevant 8 bit RCR DW 01B RDATAR 15 0 are relevant 16 bit...

Page 1624: ...dress ADDR indicates the complete target address for the pipe x Remote Window When a pipe x Copy Base Address Frame is received ADDR 31 4 becomes loaded with the transmitted 28 bit address and bits 3 0 are cleared When a write or Read Frame with m bits of address offset is received bits ADDR 31 m are held constant and bits ADDR m 1 0 are replaced by the received offset When an optimized read or da...

Page 1625: ...ADDR indicates the complete target address for the most recently or currently targeted Remote Window pipe x When a Copy Base Address Frame is received ADDR is unchanged When a write or Read Frame with m bits of address offset is received bits ADDR 31 m replaced by the bits RPxBAR ADDR 31 m and bitsADDR m 1 0 are replaced by the received offset When an optimized read or data frame is received the a...

Page 1626: ...w rw rw rw rw rw rw rw Field Bits Type Description NFRIE 1 0 rw Normal Frame Received Interrupt Enable This bit field defines if an SRx output is activated if a Normal Frame is correctly received 00B The SRx activation is disabled 01B The selected SRx line is activated each time a Normal Frame is correctly received 10B The selected SRx line is activated each time a Normal Frame is correctly receiv...

Page 1627: ...otection Interrupt Enable This bit determines if an SRx output line is activated if a memory access protection error is detected 0B Memory access protection error event is disabled for activation of an SRx line 1B Memory access protection error event is enabled for activation of an SRx line DRAIE 9 rw Discarded Read Answer Interrupt Enable This bit determines if an SRx output line is activated if ...

Page 1628: ... 1B Clear RISR ICE PEIR 23 w Parity Error Interrupt Flag Clear 0B No action 1B Clear RISR PEI MPEIR 24 w Memory Protection Error Interrupt Flag Clear 0B No action 1B Clear RISR MPEI DRAIR 25 w Discarded Read Answer Interrupt Flag Clear 0B No action 1B Clear RISR DRAI 0 15 10 31 26 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1629: ...eceived Interrupt Flag This flag is set when a Write or a Read Frame has been received The service request output that is activated is defined by RINPR NFRIP MEI 1 rh MLI Move Engine Interrupt Flag This flag is set when the move engine has finished an operation read or write depending on received frame The service request output that is activated is defined by RINPR MPPEIP CFRIx x 0 3 2 x rh Comma...

Page 1630: ...pt Flag This flag is set when a memory protection event has occurred The service request output that is activated is defined by RINPR MPPEIP DRAI 9 rh Discarded Read Answer Interrupt Flag This flag is set when the discarded read answer event has occurred This condition occurs if an Answer Frame is received while none of the TRSTATR RPx bits is set the Answer Frame was not expected The service requ...

Page 1631: ... received event occurs 000B The service request output SR0 is selected 001B The service request output SR1 is selected B 110B The service request output SR6 is selected 111B The service request output SR7 is selected CFRIP 6 4 rw Command Frame Received Interrupt Pointer This bit field determines which service request output SRx becomes active when a Command Frame received event occurs Coding see N...

Page 1632: ...TC1796 Peripheral Units Vol 2 of 2 Micro Link Interface MLI User s Manual 23 123 V2 0 2007 07 MLI V2 0 0 3 7 11 31 15 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1633: ...Four service request outputs of each MLI module are connected as DMA request to the DMA controller The data clock and control lines of each MLI receiver and transmitter are connected to GPIO lines Alternate functions of Port 1 and Port 5 lines are assigned to the MLI0 module I O lines while alternate functions of Port 8 lines are assigned to the MLI1 module I O lines Additionally within one MLI mo...

Page 1634: ... figure above are connected to low level See also Page 23 130 for additional details on I O line control and function selection SR 3 0 fMLI0 Address Decoder Interrupt Control Clock Control To DMA SR 7 4 Port 1 Control P1 5 TREADY0A Port 5 Control TREADYA TCLK TREADYD TVALIDA TVALIDD TDATA Transmitter Receiver RCLKA RCLKD RREADYA RREADYD RVALIDA RVALIDD RDATAA RDATAB TREADYB RREADYB RVALIDB RDATAD ...

Page 1635: ...mitter receiver output lines TVALIDC and RREADYC are reserved for emulation purposes Unused transmitter receiver input lines TREADYC RCLKC RVALIDC and RDATAC are reserved for emulation purposes and should not be selected during normal operation of the TC1796 See also Page 23 130 for additional details on I O line control and function Interrupt Control MCA05907 Port 8 Control SR 1 0 fMLI1 Address D...

Page 1636: ...n the following sections Figure 23 53 MLI0 MLI1 Implementation Specific Special Function Registers 23 5 2 1 Automatic Register Overwrite The following values are applied after reset see Page 23 66 OICR 1000 8000H Setting A is selected RCR RCVRST 0 the receiver is enabled for reception P1_IOCR0 MCA05908_mod DMA_MLI0SRCx Interrupt Registers P1_IOCR4 P1_IOCR8 Port Registers Clock Control Register DMA...

Page 1637: ...actional divider register functionality are described in section Fractional Divider Operation on Page 3 29 of the TC1796 User s Manual System Units part Volume 1 fDMA This is the module clock used inside the MLI kernels for control purposes such as for clocking of control logic and register operations The clock control register DMA_CLC makes it possible to enable disable fDMA under certain conditi...

Page 1638: ...e of the fractional divider FDR DM 01B Equation 23 5 applies to fractional divider mode FDR DM 10B After a reset operation both MLI modules are enabled in normal divider mode According the MLIx_FDR register s reset value of 03FF 43FFH the selected baud rate is fDMA 2 Note that the DMA controller is also enabled after a reset operation with clock fDMA fSYS The receiver baud rate is defined by the f...

Page 1639: ...ntrol registers When the MLI modules are connected to the GPIO port lines the correct settings of the enable polarity control bits and bit fields in the output input control registers MLI0_IOCR and MLI1_IOCR must also be regarded transmitter I O line control see Page 23 51 receiver I O line control see Page 23 51 Note that after a reset operation the MLI0 and MLI1 modules although enabled have no ...

Page 1640: ... PC11 0XXXB 1 MLI1_OICR RDP X2 MLI1_OICR RDS 00B Input P1 13 RCLK0B P1_IOCR12 PC13 0XXXB 1 MLI0_OICR RCE 1 MLI0_OICR RCP X2 MLI0_OICR RCS 01B Input P1 14 RVALID0B P1_IOCR12 PC14 0XXXB 1 MLI0_OICR RVE 1 MLI0_OICR RVP X2 MLI0_OICR RVS 01B Input P1 15 RDATA0B P1_IOCR12 PC15 0XXXB 1 MLI1_OICR RDP X2 MLI1_OICR RDS 01B Input P5 4 RREADY0B P5_IOCR4 PC4 1X10B 1 MLI0_OICR RRS 01B MLI0_OICR RRPB X2 Output P...

Page 1641: ...K1A P8_IOCR4 PC4 0XXXB 1 MLI1_OICR RCE 1 MLI1_OICR RCP X2 MLI1_OICR RCS 00B Input P8 5 RREADY1A P8_IOCR4 PC5 1X11B 1 MLI1_OICR RRS 00B MLI1_OICR RRPA X2 Output P8 6 RVALID1A P8_IOCR4 PC6 0XXXB 1 MLI1_OICR RVE 1 MLI1_OICR RVP X2 MLI1_OICR RVS 00B Input P8 7 RDATA1A P8_IOCR4 PC7 0XXXB 1 MLI1_OICR RDP X2 MLI1_OICR RDS 00B Input 1 Possible PCx bit field combinations see Table 23 12 2 With polarity con...

Page 1642: ...is bit field value is default after reset Pull up device connected 0X11B No pull device connected 1001B Output Push pull Output function ALT1 1101B Open drain Output function ALT1 1010B Push pull Output function ALT2 1110B Open drain Output function ALT2 1011B Push pull Output function ALT3 1111B Open drain Output function ALT3 P1_IOCR0 Port 1 Input Output Control Register 0 10H Reset Value 2020 2...

Page 1643: ... Port input output control for P1 7 TDATA0 1 Coding of bit field see Table 23 12 Shaded bits and bit fields are don t care for MLI I O port control P1_IOCR8 Port 1 Input Output Control Register 8 18H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC11 0 PC10 0 PC9 0 PC8 0 rw r rw r rw r rw r Field Bits Type Description PC8 PC9 PC10 PC11 7 4 15 12 23 20 31 28 rw Port Input Output...

Page 1644: ...ut output control for P1 14 RVALID0B Port input output control for P1 15 RDATA0B 1 Coding of bit field see Table 23 12 Shaded bits and bit fields are don t care for MLI I O port control P5_IOCR4 Port 5 Input Output Control Register 4 14H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC7 0 PC6 0 PC5 0 PC4 0 rw r rw r rw r rw r Field Bits Type Description PC4 PC6 7 4 23 20 rw Por...

Page 1645: ...ID1A Port input output control for P8 3 TDATA1 1 Coding of bit field see Table 23 12 Shaded bits and bit fields are don t care for MLI I O port control P8_IOCR4 Port 8 Input Output Control Register 4 14H Reset Value 2020 2020H 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 PC7 0 PC6 0 PC5 0 PC4 0 rw r rw r rw r rw r Field Bits Type Description PC4 PC5 PC6 PC7 7 4 15 12 23 20 31 28 rw Port Input Output...

Page 1646: ...de Register 40H Reset Value 0000 0000H 31 23 22 20 19 18 16 15 8 7 5 4 3 0 0 PDSYS CLK 0 PD MLI0 0 PD1 0 PD0 r rw r rw r rw rw Field Bits Type Description PDMLI0 18 16 rw Pad Driver Mode for P1 4 TCLK0 P1 6 TVALID0A P1 7 TDATA0 and P1 9 RREADY0A1 1 Coding of bit field see Table 23 13 Shaded bits and bit fields are don t care for MLI I O port control P5_PDR Port 5 Pad Driver Mode Register 40H Reset...

Page 1647: ...ALID1A P8 3 TDATA1 and P8 5 RREADY1A1 1 Coding of bit field see Table 23 13 Shaded bits and bit fields are don t care for MLI I O port control Table 23 13 Pad Driver Mode Mode Selection Class A2 Pads PDx Bit Field Driver Strength Signal Transitions 000B Strong driver Sharp edge1 1 In strong driver mode the output driver characteristics of class A2 pads can be additionally controlled by the tempera...

Page 1648: ...are located inside the DMA address area Therefore all MLI0 MLI1 service request control registers are named as DMA_MLIxSRCy and described in the DMA chapter implementation part see Page 12 107 of the TC1796 System Units User s Manual All MLI service request output connections are listed in Table 23 14 Table 23 14 Service Request Lines and Interconnections of MLI0 MLI1 Module Service Req Output Lin...

Page 1649: ...e Request Node 0 in DMA SR1 DMA_MLI1SRC1 MLI1 Service Request Node 1 in DMA SR2 Not connected SR3 Not connected SR4 CH10_REQI14 DMA Channel 10 Request Input 15 CH14_REQI14 DMA Channel 14 Request Input 15 SR5 CH11_REQI6 DMA Channel 11 Request Input 15 CH15_REQI5 DMA Channel 15 Request Input 15 SR6 CH12_REQI5 DMA Channel 12 Request Input 15 CH16_REQI6 DMA Channel 16 Request Input 15 SR7 CH13_REQI5 D...

Page 1650: ...d Address Range 0 AEN0 F000 0000H to F000 00FFH F010 C200H to F010 C2FFH SCU incl WDT MEMCHK 1 AEN1 F000 0100H to F000 01FFH F010 0000H to F010 00FFH SBCU RBCU 2 AEN2 F000 0200H to F000 02FFH STM 3 AEN3 F000 0400H to F000 04FFH OCDS 4 AEN4 F000 0800H to F000 08FFH F000 0900H to F000 09FFH MSC0 MSC1 5 AEN5 F000 0A00H to F000 0AFFH ASC0 6 AEN6 F000 0B00H to F000 0BFFH ASC1 7 AEN7 F000 0C00H to F000 ...

Page 1651: ...000 0000H to 807F FFFFH A000 0000H to A07F FFFFH Program Flash Space 24 AEN24 8080 0000H to 8FDF FFFFH A080 0000H to AFDF FFFFH External EBU Space 25 AEN25 8FE0 0000H to 8FEF FFFFH AFE0 0000H to AFEF FFFFH Data Flash Space 26 AEN26 8FF0 0000H to 8FFF BFFFH AFF0 0000H to AFFF BFFFH Emulation Device Memory Space 27 AEN27 8FFF C000H to 8FFF FFFFH AFFF C000H to AFFF FFFFH Boot ROM 28 AEN28 D800 0000H ...

Page 1652: ...ange access protection are defined as shown in Table 23 16 Table 23 16 DPRAM Address Protection Sub Range Definitions SIZE0 Sub Ranges SLICE0 Selected Address Range 000B 32 sub ranges of 64 bytes 00000B 00001B 11111B F010 A000H to F010 A03FH F010 A040H to F010 A07FH F010 A7C0H to F010 A7FFH F010 A800H to F010 BFFFH is not selectable 001B 32 sub ranges of 128 bytes 00000B 00001B 11111B F010 A000H t...

Page 1653: ...ted Address Range 000B 32 sub ranges of 512 bytes 00000B 00001B 11111B E800 0000H to E800 01FFH E800 0200H to E800 03FFH E800 3E00H to E800 3FFFH E800 4000H to E800 FFFFH is not selectable 001B 32 sub ranges of 1 Kbyte 00000B 00001B 11111B E800 0000H to E800 03FFH E800 0400H to E800 07FFH E800 7C00H to E800 7FFFH E800 8000H to E800 FFFFH is not selectable 010B 32 sub ranges of 2 Kbytes 00000B 0000...

Page 1654: ...X11B E800 0000H to E800 3FFFH E800 4000H to E800 7FFFH E800 8000H to E800 BFFFH E800 C000H to E800 FFFFH 110B 2 sub ranges of 32 Kbytes XXXX0B XXXX1B E800 0000H to E800 7FFFH E800 8000H to E800 FFFFH 111B 64 Kbytes XXXXXB E800 0000H to E800 FFFFH Table 23 17 SRAM Address Protection Sub Range Definitions cont d SIZE1 Sub Ranges SLICE1 Selected Address Range ...

Page 1655: ...Pipe 0 F01E 0000H to F01E 1FFFH Pipe 1 F01E 2000H to F01E 3FFFH Pipe 2 F01E 4000H to F01E 5FFFH Pipe 3 F01E 6000H to F01E 7FFFH Large Transfer Window Pipe 0 F020 0000H to F020 FFFFH Pipe 1 F021 0000H to F021 FFFFH Pipe 2 F022 0000H to F022 FFFFH Pipe 3 F023 0000H to F023 FFFFH MLI1 Small Transfer Window Pipe 0 F01E 8000H to F01E 9FFFH Pipe 1 F01E A000H to F01E BFFFH Pipe 2 F01E C000H to F01E DFFFH...

Page 1656: ...e for GPTA0 and GPTA1 see Page 24 6 Register descriptions of all GPTA kernel specific registers applicable for GPTA0 and GPTA1 see Page 24 150 Functional description of the LTCA2 kernel see Page 24 217 Register descriptions of all LTCA2 kernel specific registers see Page 24 233 TC1796 implementation specific details and registers of the GPTA module including port connections and control interrupt ...

Page 1657: ...plications Figure 24 1 General Block Diagram of the GPTA Modules in the TC1796 Signal Generation Unit MCB05910 GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GTC01 GTC00 GTC31 Global Timer Cell Array GTC03 GTC30 Clock Bus GPTA0 Clock Generation Unit Signal Generation Unit GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GT...

Page 1658: ...ult of an internal compare operation GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform Local Timer Cells LTC operating in Timer Capture or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform LTCs enabled in Timer Mode or Capture Mode can be clocked or triggered by various external ...

Page 1659: ...clock LTC prescaler clock Signal Generation Unit Global Timers GT Two independent units Two operating modes Free Running Timer and Reload Timer 24 bit data width fGPTA maximum resolution fGPTA 2 maximum input signal frequency Global Timer Cell GTC 32 units related to the Global Timers Two operating modes Capture Compare and Capture after Compare 24 bit data width fGPTA maximum resolution fGPTA 2 m...

Page 1660: ...nterconnecting inputs and outputs from internal clocks FPC GTC LTC ports and MSC interface 24 1 2 Functionality of LTCA2 64 Local Timer Cells LTCs Three basic operating modes Timer Capture and Compare for 63 units Special compare modes for one unit 16 bit data width fGPTA maximum resolution fGPTA 2 maximum input signal frequency ...

Page 1661: ...ut signals and four input signals that can be connected to port pins or other on chip logic units see GPTA Module Implementation on Page 24 247 for the TC1796 specific interconnections Further several clock input and output signals are provided Interrupt Control MCB05911 Clock Control Address Decoder fGPTA SR 37 00 GPTA Module Kernel Clock Generation Unit Filter Prescaler Cells Phase Discriminator...

Page 1662: ...nput clock period The Clock Distribution Unit CDU provides all LTCs and GTs with a variety of different clock signals It is equipped with GPTA module clock prescalers and multiplexers supporting alternate clock sources The original signals and all outputs of the preprocessing units are distributed to the Global Timers and LTCs via the clock bus The Signal Generation Unit see Page 24 37 provides a ...

Page 1663: ...m In the PDL phase encoding can be bypassed The Duty Cycle Measurement Units DCM provide signal measurement capabilities timer plus capture register single and double capture on rising and falling edges or both as well as missing pulse detection reconstruction functions The Digital Phase Locked Loop PLL is intended to generate a higher resolution clock out of the values measured by DCM cells Any a...

Page 1664: ...al Inp Clock SOL1 SOT2 FPC2 Signal Inp Clock SOL2 SOT3 FPC3 Signal Inp Clock SOL3 SOT4 FPC4 Signal Inp Clock SOL4 SOT5 FPC5 Signal Inp Clock SOL5 M U X Control Logic M U X DCM0 DCM1 PDL0 F0 B0 M U X Control Logic M U X DCM2 DCM3 PDL1 F0 B0 PLL CDU GPTA Inputs GPTA Inputs GPTA Inputs GPTA Inputs GPTA Inputs Clock Bus 8 Ext PLL Clock Inputs CLK1 CLK2 CLK3 PDL0 PDL1 PDL2 PDL3 PDL Bus Int PLL Clock Ou...

Page 1665: ...l algorithm description Figure 24 4 Filter and Prescaler Cell Architecture FPC Registers The following registers are assigned to the filter and prescaler cells FPCk k 0 5 FPCSTAT Filter and Prescaler Cell Status Register see Page 24 155 FPCCTRk Filter and Prescaler Cell Control Register k see Page 24 156 FPCTIMk Filter and Prescaler Cell Timer Register k see Page 24 158 MCA05913 IPS FPCCTRk SINk0 ...

Page 1666: ...INk1 Signal input 2 SINk2 Signal input 3 SINk3 GPTA module clock fGPTA SINk4 Preceding FPC level output signal SOLk 1 SIN05 is connected to SOL5 When the preceding FPC level output signal is selected as input two or more FPCs may be concatenated for example to combine a delayed debounce filter and an immediate debounce filter The maximum FPC input signal frequency must be less than or equal to the...

Page 1667: ...er output signal SOTk reporting a falling or rising signal edge on the FPC input by a single fGPTA clock pulse A level output signal SOLk indicating the direction of the detected signal transition This signal splitting scheme pair of trigger and level output provides subsequent PDL and DCM cells with the information about an input signal transition in the same fGPTA clock cycle This feature avoids...

Page 1668: ...l be set to idle state again see Figure 24 7 A rising or falling edge occurring on the signal input line SIN when the timer is greater than zero but less than the compare value sets the corresponding glitch flag FPCSTAT REG on rising edge glitch or FPCSTAT FEG on falling edge glitch When the timer matches the 16 bit compare value stored in FPCCTRk CMP timer threshold the level output signal line S...

Page 1669: ...ds on the programmed compare register value the number of high frequency pulses glitches during the filter operating time and the timer behavior in case of a glitch decrement or reset The FPC Delayed Debounce Filter Mode is selected by FPCCTRk MOD 000B MCT05916 Total Signal Delay Timer Threshold must be cleared by software Signal Input SIN Timer Value FPCCTRk TIM Level Output SOLk FPCSTAT FEGk FPC...

Page 1670: ...CTRk CMP is not zero the timer is enabled to be incremented by the selected clock and the copy mechanism is disabled When the timer value FPCTIMk TIM matches the compare value FPCCTRk CMP the timer is reset and the copy mechanism is enabled again A rising or falling edge occurring on SIN while the timer is greater than zero but less than the compare value sets the corresponding glitch flag FPCSTAT...

Page 1671: ...ue immediately after the timer threshold of the filtered edge is reached without re starting the timer see Figure 24 9 Figure 24 9 FPC Immediate Debounce Filter Algorithm on Rising Edge only The FPC Immediate Debounce Filter Modes are selected by FPCCTRk MOD 001B Immediate Debounce Filter Mode on both edges FPCCTRk MOD 010B Immediate Debounce Filter Mode on rising edge only no filtering on falling...

Page 1672: ...s case see Figure 24 10 demonstrating Delayed Debounce Mode with Timer Decrement on Rising Edge and Immediate Debounce of on Falling Edge Figure 24 10 FPC Mixed Filter Algorithm The FPC Mixed Filter Modes are selected by FPCCTRk MOD 100B Delayed Debounce Filter Mode on rising edge Immediate Debounce Filter Mode on falling edge FPCCTRk MOD 101B Immediate Debounce Filter Mode on rising edge Delayed ...

Page 1673: ...d level output signal SOLk the timer FPCTIMk TIM is reset to 0000H Figure 24 11 shows a divide by 6 operation using the FPC in Prescaler Mode with trigger on rising edge selected Figure 24 11 FPC Prescaler Mode For a divide by n operation the compare value FPCCTRk CMP must be set to n 1 The FPC Prescaler Modes are selected by FPCCTRk MOD 110B Prescaler Mode triggered on rising edge FPCCTRk MOD 111...

Page 1674: ...M3 for PDL1 The PDL processes the output signal of a 2 sensor or 3 sensor positioning system With bit PDLCTR TSEx 1 a 3 sensor system execution is selected providing the DCM1 and or DCM3 cell with information concerning erroneous states in the signal input When PDLCTR TSEx 0 a 2 sensor system is selected and DCM1 and or DCM3 are supplied with the input event and level information from the driving ...

Page 1675: ...or a 3 sensor positioning system To ensure that a transition of any input signal is correctly recognized its level should be held high or low for at least twofGPTA cycles before it changes three fGPTA cycles for a 3 sensor positioning system Figure 24 12 Block Diagram of Phase Discrimination Logic Unit MCB05921 2 FPC0 Phase Discrimation Logic PDL0 F0 B0 DCM0 2 2 2 FPC1 FPC2 DCM1 2 PDL0 PDL1 PDL2 P...

Page 1676: ...e an absolute position with a resolution of 90 No error conditions can be detected Figure 24 13 Interface Signals of a PDL in a 2 Sensor Positioning System Figure 24 14 illustrates how the output signals of a 2 sensor system superimposed with noise are processed by the PDL unit Jitter pulses are completely compensated if they do not occur on both signal lines simultaneously Means not Re Means risi...

Page 1677: ...nputs low or all inputs high cause the following to occur An error signal is generated driving the Duty Cycle Measurement cells DCM1 and or DCM3 The error flag PDLCTR ERRx is set No forward or backward pulses are generated When the error disappears the error signal will be cleared The error flag PDLCTR ERRx must be cleared by software Means not Re Means rising edge Fe Means falling edge Forward Re...

Page 1678: ...5 Interface Signals of a PDL in a 3 Sensor Positioning System Jitter pulses are completely compensated as illustrated in Figure 24 14 MCT05924 1 2 3 4 5 6 1 2 S1 S2 S3 Forward Backward 1 6 5 4 3 2 1 6 S1 S2 S3 Forward Backward S2 S3 S1 Forward_Counter Backward_Counter 1 3 2 4 5 6 1 2 3 4 5 6 00 01 11 10 00 01 11 10 0 1 S3 ...

Page 1679: ...uipped with a 24 bit timer a 24 bit capture register a 24 bit capture compare register a 24 bit comparator and a DCM control unit Figure 24 16 The following registers are assigned to the DCM units DCMCTRk Duty Cycle Measurement Control Register k see Page 24 161 DCMTIMk Duty Cycle Measurement Timer Register k see Page 24 163 DCMCAVk Duty Cycle Measurement Capture Register k see Page 24 163 DCMCOVk...

Page 1680: ...unting from its lower limit 000000H to its upper limit FFFFFFH Capture The current timer value is stored in the capture register DCMCAV on the rising edge DCMCTR RCA 1 or falling edge DCMCTRk RCA 0 of the signal input line The current timer value is stored in the capture compare register DCMCOV on the opposite signal edge as selected by DCMCTRk RCA and if enabled by bit DCMCTRk OCA 1 With DCMCTRk ...

Page 1681: ...ware intends to compensate an input pulse backlog bit DCMCTRk QCK should be set to 1 This immediately triggers a single clock pulse generation on the DCM output signal line DCM Interrupt Control Each DCM unit is able to generate three service request output signals The service request outputs of a DCMk unit are controlled as shown in Figure 24 17 When a service request condition occurs the corresp...

Page 1682: ...DCM0kR DCM0kR DCM0kR SRSS0 read SRSR0 read Set SRSS0 write SRSC0 write Set Clear FRE DCMCTRk DCM0kF DCM0kF DCM0kF SRSS0 read SRSR0 read Set SRSS0 write SRSC0 write Set Clear CRE DCMCTRk DCM0kC DCM0kC DCM0kC SRSS0 read SRSR0 read Set SRSS0 write SRSC0 write Set Clear Rising input signal edge detected Falling input signal edge detected Compare event occurred DCMkRSR DCMkFSR DCMkCSR ...

Page 1683: ...ut signal s period length variation The PLL includes a 4 channel input multiplexer a 16 bit timer a 16 bit step register a 24 bit reload register a 24 bit adder a 24 bit multiplexer a 25 bit delta register extended by one sign bit and a PLL control unit see Figure 24 18 The following registers are assigned to the Phase Locked Loop cell PLLCTR Phase Locked Loop Control Register see Page 24 165 PLLM...

Page 1684: ...gth measured in number of fGPTA clocks An automatic compensation of an input signal acceleration or deceleration is enabled by setting bit PLLCTR AEN to 1 Automatic End Mode After disabling the Automatic End Mode the PLL continuously generates output pulses without synchronization to an input signal edge When the counter for the number of remaining output signal pulses PLLCNT decrements to zero th...

Page 1685: ...e service request condition PLLCNT 0 occurs the service request flag is always set The service request output PLLSR is activated only if it is enabled by the enable bit PLLCTR REN Additional information about service request and interrupt handling are given in section Interrupt Sharing Unit IS on Page 24 112 Figure 24 19 PLL Service Request Generation MCA05928_mod REN PLLCTR PLL PLL PLL SRSS0 read...

Page 1686: ...en loaded with a negative value 2 complement data format When the PLLDTR register has been decremented to a negative value the reload register contents are added to Delta register s current contents A rising edge detected on the selected input signal triggers the counter register PLLCNT to load the number of requested output pulses from PLLMTI When a negative content of the PLLDTR register is dete...

Page 1687: ...ts an input signal s period length variation by comparing the current period length measured in the associated DCM cell with the expected period length used as calculation base for the PLLREV register contents Compensation of input signal deceleration Compensation by PLL Automatic End Mode If Automatic End Mode is enabled PLLCTR AEN 1 the PLL stops at the calculated end of the current input signal...

Page 1688: ...ut Signal Deceleration Compensation of input signal acceleration Compensation by PLL Automatic End Mode The next rising edge of the input signal arrives while the counter has not been decremented to zero The PLL performs all remaining output signal pulses at full speed fGPTA when control register bit AEN is set to 1 Subsequently counter and Delta register are reloaded with their calculated values ...

Page 1689: ... PLL can continue to operate with the old input signal period length estimation but the number of output pulses to be generated during the next input clock period may be increased by the lack of output pulses initiated during the last signal period Figure 24 23 Compensation of Input Signal Acceleration Additionally to the normal output signal the PLL provides an uncompensated output signal This si...

Page 1690: ...mable 2n factor Factor n is defined by bit fields DFA02 DFA04 DFA06 and DFA07 of control register CKBCTR A bit field value of 15 disables the related prescaler and selects alternate sources for clock bus lines 2 4 6 and 7 For clock bus line CLK2 a bit field value of 14 selects an alternate source For clock bus line CLK3 the 2 bit wide bit field DFA03 of control register CKBCTR selects one of the f...

Page 1691: ...gram MCB05933 14 0 13 15 0 14 DFA02 CKBCTR 15 CLK0 DFA04 CKBCTR 15 0 14 DFA06 CKBCTR 15 0 14 DFA07 CKBCTR 1 0 DFA03 CKBCTR 2 3 ext PLLCLK PLLCLK fGPTA PLLCLK uncomp ext PLLCLK uncomp FPC1 SOT1 FPC4 SOT4 DCM0 DCM1 DCM3 DCM2 PLL Clock Bus CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 0 7 DFALTC CKBCTR LTCPRE 2DFA02 2DFA04 2DFA06 2DFA07 2DFALTC 4 2 14 4 15 15 15 8 4 4 3 ...

Page 1692: ...4 bit reload register and a 24 bit greater equal comparator see Figure 24 25 Note Index variable k 0 1 determines the number of the Global Timer Figure 24 25 Block Diagram of Global Timer GT The following registers are assigned to the Global Timers GTk k 0 1 GTCTRk Global Timer Control Register k see Page 24 170 GTREVk Global Timer Reload Value Register k see Page 24 172 GTTIMk Global Timer Regist...

Page 1693: ...ritten by software into the GTTIMk register The 24 bit Global Timer value GTTIMk TIM is incremented by each rising edge of clock input signal TEVk that is selected from the 8 bit clock bus via bit field GTCTRk MUX On a Global Timer overflow transition of FFFFFFH to 000000H the following events occur The 24 bit reload value GTREVk REV is copied into GTTIMk TIM Bit SRSC0 GT0k is set The service requ...

Page 1694: ...obal Timers Both Global Timers GT0 and GT1 can be enabled and disabled individually Each GT has its own run signal GTkRUN that is generated outside the GPTA kernel see also Page 24 6 Signal GTkRUN is generated in a GPTA clock control unit This external control capability makes it possible to control the run signals GTkRUN in a way that all Global Timers of one or more GPTA modules can be enabled d...

Page 1695: ...on a timer is running and a new threshold value T is set The different points Px represent different cases of present time When at P1 or P2 the moment represented by T lies in the future and no action is yet required When at P3 or P4 the moment represented by T lies in the past and an action is required immediately So the problem is to determine if the threshold T has been passed or not Considerin...

Page 1696: ...hold T The Before window refers to a prediction range and the After window refers to the history buffer From a practical point of view once the value T is determined it is necessary to calculate the observation window position and width Before updating the value T the application must ensure that the observation window was entered but has not yet been left The width of the observation window canno...

Page 1697: ...observation window This is illustrated in Figure 24 29 Using a signed compare in order to take into account the timer overflow the comparator window is introduced The comparator window is centered to the point T and its width can be selected by the user Figure 24 29 Unsigned Versus Signed Compare When the timer range is a multiple of 2 and because the comparator is scalable the observation window ...

Page 1698: ...the timer period This will impact the observation window as described in the following paragraph Observation window for reloaded timers period is not a power of 2 In that case the comparator window must exceed the timer period The user must find the comparator window by selecting the scale factor k which fits best the timer period The following equation must apply 2k Period 2 2k 24 1 Figure 24 31 ...

Page 1699: ... High Figure 24 32 Observation Window when Threshold T is Low MCT05940 Observation performed by G E compare Before After T Before Comparator Window 2 2k Observation Window Period Should be After Core Observation Window MCT05941 Observation performed by G E compare Before Comparator Window Observation Window Should be Before Core Observation Window After After T ...

Page 1700: ...centered on T whatever its value is However one particularity exists when using the core observation window the size of the core observation window varies depending on two static values the timer period and the comparator window s sizes In particular the core observation window reduces as the value of the timer period is just after a power of 2 This is shown in Figure 24 34 For any timer period wh...

Page 1701: ...rray GPTA User s Manual 24 46 V2 0 2007 07 GPTA V2 0 Figure 24 34 Core Observation Window Sizes Versus Period Sizes MCT05943 1 2 4 8 16 32 Period Observation Window Core Observation Window Width of Core Observation Window 2 x period 2k Condition 2k period 2 2k ...

Page 1702: ...re Select one of the 15 most significant result bits SCO 00H to 0EH Note On how to choose one of the 15 bits is explained later Figure 24 35 Comparator Implemented by a Subtraction Unit The interpretation of the selected result bit is provided in the following simple example For a 4 bit timer the subtraction of the threshold T from the timer value leads to a 4 bit signed result as illustrated in F...

Page 1703: ...e observation window Figure 24 37 shows the case of a period equal to a multiple of 2 Figure 24 36 Result and Observation for a 4 bit Timer MCA04616 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1...

Page 1704: ...5946 0 15 Evaluation of S Evaluation of R3 S 1 S 0 R3 1 R3 0 T Evaluation of Result Timer T N3 N2 N1 N0 T3 T2 T1 T0 R3R2R1R0 S Timer Value Threshold Value Result Value with Sign Bit S Example for 4 Bit Timer n 4 Unsigned Compare The Bit Evaluated is S Signed Compare on Bit 3 The Bit Evaluated is R3 MCT05947 4 15 Evaluation of R3 R3 1 R3 0 T Evaluation of Result Timer T N3N2N1N0 T3 T2 T1 T0 R3R2R1R...

Page 1705: ...ect for observation R3 corresponds to the comparator window s size k 3 Considering the case in which the period is not a multiple of 2 choose a comparator window whose width is between 1 and 2 times the timer period 2k Period 2 2k 24 2 In no case may the comparator window be equal to or greater than twice the period The letter k represents the Result bit to select ...

Page 1706: ...riod 2 2k 24 4 SCO bit field 0 to 0EH 0 to 14d Thereby the result bit Rk is selected to drive TGE flag This setting is possible for periods greater than 512 Table 24 1 Period Range Depending on Selected k 2k Period 2 2k k SCO Bit Field decimal 0 period 512 Not covered by implementation 512 period 1024 9 0 1024 period 2048 10 1 2048 period 4096 11 2 4096 period 8192 12 3 8192 period 16384 13 4 1638...

Page 1707: ...s indicates the threshold value T The 45 line starting at m m represents the position in time of T The graphic shows the observation performed by the hardware for all cases of T m T M Figure 24 39 illustrates the Unsigned compare A particular case is shown in which for a higher value of T the observation indicates Before at the beginning of the period and until the timer reaches the value T Therea...

Page 1708: ...phical representation of this general case is analogous to the one described in Figure 24 31 If the period is not a multiple of 2 the graphical representation of the Signed compare shows a discontinuity in the Before and After ranges Indeed the widths of the Before and After windows are not constant as they depend on the value T As a consequence the observation window is not centered on T The resu...

Page 1709: ... respect to T It also shows the core observation window that is always centered on T and which has a constant width Figure 24 42 Core Observation Window in the Graphic Before MCT05950 After Before Before Timer M m m Threshold M Value of T T point in time 2 2 k Period Comparator Window Period After After Before Before MCT05951 Timer M m m Threshold M Point T1 Observation Window Core Observation Win...

Page 1710: ...on set reset toggle the output signal Capture after compare match the value of the selected Global Timer or the opposite Global Timer One Shot Mode allows the selected capture or compare mode to be stopped after the first event Flexible mechanism to link pin actions and allow complex combination of cells A cell has the ability to propagate actions over adjacent cells with higher number in order to...

Page 1711: ...puts One data output GTCkOUT that can be connected to External port lines Inputs of an MSC module Outputs and or inputs of Local Timer Cell inputs Two action mode outputs M0O M1O going to the adjacent GTC with higher order number One service request line SQSk triggered by a capture compare event Figure 24 43 Architecture of Global Timer Cells MCA05952 GTCk Control Logic M1O GTCkIN X 24 Bit Value G...

Page 1712: ...ctions Note Cascading of GTCs is limited TC1796 specific details are given on Page 24 272 MCA05953 From GTC29 Global Timer Cell GTC00 M1I M0I M1O M0O GTC00IN GTC00OUT SQS00 GTV1 Bus TGE1 TEV1 GTV0 Bus TGE0 TEV0 Global Timer GT0 Global Timer Cell GTC01 M1I M0I M1O M0O GTC01IN GTC01OUT SQS01 Global Timer Cell GTC30 M1I M0I M1O M0O GTC30IN GTC30OUT SQS30 Global Timer Cell GTC31 M1I M0I GTC31IN GTC31O...

Page 1713: ...the value stored in register GTCXR With GTCCTRk GES 0 an Equal Compare match is selected while GTCCTRk GES 1 selects a Greater Equal Compare match On the requested event the GTC Sets the GTCk service request flag in register SRSS1 SRSC1 Activates service request output SQSk if control register bit GTCCTRk REN 1 Performs a GTCkOUT output signal line manipulation set reset toggle unchanged as define...

Page 1714: ...n is activated when the compare value is reached and released after a read access of register GTCXRk occurred Data Output Line Control The data output GTCkOUT can be controlled by the GTCk itself and by adjacent GTCs with a lower order number For this purpose two communication signals between GTCs are available connecting all GTCs via their M1I M0I inputs and their M1O M0O outputs respectively see...

Page 1715: ...be connected to output ports on chip peripheral inputs and or LTC inputs via the I O Line Sharing Unit see Page 24 90 GTCkOUT can be updated directly by software setting bit GTCCTRk OIA 1 or upon a timer capture or compare event within the local GTCk or a preceding GTC The current state of the data output line can be evaluated by reading status flag GTCCTRk OUT Table 24 2 Selection of GTC Output O...

Page 1716: ...unication link for local events For this purpose the GTCCTRk EOA bit of the following GTC must be set too If bit GTCCTRk OCM2 of the preceding GTC is 1 the enable action will take place at the same time as in the preceding GTC Otherwise the GTC will be enabled later on a capture compare event in the preceding GTC provided OCM0 or OCM1 of this GTC is different from 0 In this way several GTCs can be...

Page 1717: ...r Cell GTCk is controlled as shown in Figure 24 46 When the GTCk service request condition becomes active the service request flag is always set The service request output SQSk is only activated if it is enabled by the enable bit GTCCTRk REN Additional information about service request and interrupt handling is given on Page 24 112 Figure 24 46 GTCk Service Request Generation MCA05955_mod REN GTCC...

Page 1718: ... Capturing and Analyzing In this application example one input signal from a GTC input multiplexer group becomes analyzed from a timing reference point for three consecutive signal transitions This common input signal e g a port line is selected by a GTC input multiplexer group GIMG common for GTC01 GTC02 and GTC03 see also Page 24 100 The GTCs are configured in the following way GT0 operates as f...

Page 1719: ...se it was operating in One Shot Mode When GTC02 detects a falling edge at its data input it captures the current GT0 value into its GTCXR02 register enables GTC03 and becomes disabled afterwards because it was operating in One Shot Mode When GTC03 detects a rising edge at its data input it captures the current GT0 value into its GTCXR03 register and becomes disabled afterwards because it was opera...

Page 1720: ...ed OSM set Furthermore the output GTC03OUT becomes set on a local event OCM X11B GTC01 operates in Compare Mode with timer GT0 with enable on action set EOA set and One Shot Mode enabled OSM set Furthermore the output GTC03OUT becomes reset on a local event OCM 110B GTC02 operates in Compare Mode with timer GT0 with enable on action set EOA set and One Shot Mode enabled OSM set Furthermore the out...

Page 1721: ...mes disabled because it was operating in One Shot Mode When the GTC02 compare event occurs the output signal GTC03OUT is set GTC03 becomes enabled and GTC02 becomes disabled because it was operating in One Shot Mode When the GTC03 compare event occurs the output signal GTC03OUT is reset and GTC02 becomes disabled because it was operating in One Shot Mode The capture event at GTC03 should generate ...

Page 1722: ...uest generation Output signal transition generation set reset toggle the output signal Compare Mode on equal compare of the corresponding Reset Timer LTC with following actions Service request generation Output signal transition generation set reset toggle the output signal Timer Mode incremented on hardware signal with following actions Event generation at overflow Service request generation Outp...

Page 1723: ...ollowing signals sources External port lines GTC00 to GTC31 outputs Clock bus signals PDL0 or PDL1 outputs Internal GPTA kernel input signals INTx x 0 3 Each LTC provides the following output signals One data output line LTCkOUT that can be connected to External port lines Inputs of an MSC module Outputs and or inputs of Global Timer Cell inputs One LTC prescaler clock input LTCPRE for Timer Mode ...

Page 1724: ...y GPTA User s Manual 24 69 V2 0 2007 07 GPTA V2 0 Figure 24 50 Architecture of Local Timer Cells MCA05959 LTCk Control Logic LTCPRE LTCXRk LTCkOUT SQTk From To Previous LTCk 1 MUX EO TI M0I M1I SI EI TO M0O M1O SO YO YI To From Next LTCk 1 X 16 Bit Capcom LTCkIN ...

Page 1725: ...between the LTCs Note Cascading of LTCs is limited TC1796 specific details are given on Page 24 272 From LTC60 Local Timer Cell LTC00 M1I M0I LTC00IN LTC00OUT SQT00 To LTC02 TI EO SI M1O M0O TI EI SO 0000H YI YO Local Timer Cell LTC01 M1I M0I TI EO SI M1O M0O TO EI SO YI YO Local Timer Cell LTC61 M1I M0I TI EO SI M1O M0O TO EI SO YI YO MCA05960 Local Timer Cell LTC62 M1I M0I TI EO SI M1O M0O TO EI...

Page 1726: ...ending on bit field LTCCTRk OCM an action request generated by an LTCk internal event or received on the M1I M0I input lines is transferred via the M1O M0O output lines to the LTC with higher order number LTCk 1 The event output line EO is also activated set to high by a software reset when writing FFFFH to register LTCXRk Reset Timer Mode An LTC that is configured in Reset Timer Mode provides the...

Page 1727: ...nged set reset toggle unchanged depending on bit field LTCCTRk OCM An action request is generated and or passed via the M1O M0O output lines to the LTC with higher order number LTCk 1 The event output EO is set to high level for one fGPTA clock cycle Note To enable the compare function in all cases on every timer or compare register update caused by a software write access a reset event or a compa...

Page 1728: ...ne The external signal operates as gating signal for the cell The active input level can be selected with control register bit AIL Additionally the LTC prescaler mode can be enabled with LTCCTRk PEN to reduce the timer frequency The programmed function of the LTC is performed with the GPTA module clock frequency or with the programmed prescaler clock LTCPRE see Page 24 36 The programmed function o...

Page 1729: ...nal is a high level GTC output The GTC output signal operates as gating signal for the cell The active input level can be selected with bit LTCCTRk AIL Additionally the LTC prescaler clock LTCPRE can be enabled with bit LTCCTRk PEN to reduce the timer frequency The programmed function of the LTC cell is performed on selected edge s Table 24 3 LTC Data Input Line Operation in Timer Mode cont d Inpu...

Page 1730: ...k OCM1 and LTCCTRk OCM0 see Table 24 4 When bit LTCCTRk OCM2 is set the data output LTCkOUT is affected either by the local LTCCTRk OCM1 and LTCCTRk OCM0 bits or by the M1I M0I input lines which are connected to the adjacent LTCk 1 Global Timer output lines M1O M0O An enabled LTCk event superimposes an action request generated simultaneously by the M1I M0I inputs When the bypass bit LTCCTRk BYP is...

Page 1731: ...he LTC can be deactivated by setting it into Compare Mode with no active select line level LTCCTRk SOL LTCCTRk SOH 0 but the communication link remains active In this mode configuration EI will be passed to EO Table 24 4 Selection of LTC Output Operations and Action Transfer Modes Bit Field OCM 2 0 Local Capture Compare or Timer Overflow Event M1O M0O BYP 0 M1O M0O BYP 1 State of Local Data Output...

Page 1732: ...e time as in the preceding cell Otherwise the LTC will be enabled later on a capture compare event in the preceding LTC provided LTCCTRk OCM0 or LTCCTRk OCM1 of this cell is different from 0 In this way several LTCs can be enabled at the same time or one after the other Normally the LTCs will be used in One Shot Mode and a service request will be generated after the last event to evaluate the data...

Page 1733: ...tion becomes active the service request flag becomes always set The service request output SQTk is only activated if it is enabled by the enable bit LTCCTRk REN Additional information about service request and interrupt handling is given on Page 24 112 Figure 24 53 LTCk Service Request Generation MCA05962_mod REN LTCCTRk LTCk LTCk LTCk SRSSn read SRSRn read Set SQTk SRSSn write SRSCn write Set Cle...

Page 1734: ...et toggle the output signal Bit Reversal Mode Timer can be selected to enable a special PWM Mode called pulse count modulation PCM Compare Value Switching can be triggered by a hardware signal This function can generate a service request One Shot Mode makes it possible to stop the function after the first event Architecture LTC63 is locally equipped with a 16 bit compare register a 16 bit shadow r...

Page 1735: ...pare value LTCXR63 X is greater than the timer value provided at YI the comparator output signal is 1 The timer value at YI comes from the LTC62 either in original or in reversed order Bit0 Bit15 Bit1 Bit14 etc The greater comparator output is connected directly to the output line LTC63OUT The 16 bit compare value LTCXR63 X is never greater than the LTC timer value FFFFH coming from YI and which i...

Page 1736: ...n on the fly If the duty cycle is changed at an arbitrary time the actual duty cycle for the current period will reflect the old duty cycle the new one or a mixture of both A duty cycle of 100 will be generated if the compare register is set to FFFFH Pulse Count Modulation Mode PCM With a period of 100 clocks and a duty cycle of 64 standard PWM will produce an output signal that is ON for 64 clock...

Page 1737: ...med via software may be used to reduce the worst case error If the duty cycle is changed at an arbitrary time the actual duty cycle for the entire current period will reflect the old duty cycle the new one or a mixture of both Table 24 5 Implicit PCM Rounding Desired Duty Cycle Expected ON Pulses Actual ON Pulses 0 000 0000 0 0 0 100 199AH 10 11 0 500 8000H 50 50 0 800 CCCDH 80 82 0 900 E666H 90 9...

Page 1738: ...For software access the compare register LTCXR63 X 16 bit low part of LTCXR63 is written directly For compare value switching triggered by hardware the shadow register LTCXR63 XS 16 bit high part of LTCXR63 is pre loaded with the desired duty cycle On an LTC input signal selected via the LTC input multiplexer The shadow register content LTCXR63 XS is copied to the compare register LTCXR63 X The LT...

Page 1739: ...e two service request sources and enables it Output SQT63 becomes active in these two cases With Table 24 6 LTC63 Data Input Line Operation Input Source Level Sensitive Input Line Edge Sensitive Input Line External Signal Port line The external signal operates as gating signal for the cell If the input is high the copy function of the LTC cell is performed with each rising edge of the GPTA module ...

Page 1740: ...activated The LTC63 service request flag SRSS3 LTC63 will be set on a service request independently of LTCCTR63 REN Additional information on service request and interrupt handling is given on Page 24 112 Figure 24 57 LTC63 Service Request Generation MCA05966_mod REN LTCCTR63 Set LTC63 LTC63 Clear LTC63 SRSS3 read SRSR3 read Set SQT63 SRSS3 write SRSC3 write 2 0 0 Copy event occured Compare event ...

Page 1741: ...uent cells with a time base LTC00 is clocked by a clock signal at the LTC00IN which has been selected by the LTC input multiplexer LTC01 and LTC02 are configured in Compare Mode They are enabled if its SI inputs are at low level and responsible for the LTC04OUT signal generation in Phase 1 With the programmed values from Table 24 7 the LTC04OUT signal of Phase 1 has a period of 1000D 3E8H clocks o...

Page 1742: ...re configured in Compare Mode They are enabled if its SI inputs are at high level and are responsible for the LTC04OUT signal generation in Phase 2 With the programmed values from Table 24 7 the LTC04OUT signal of Phase 2 has a period of 2000D 7D0H clocks of the LTC00IN clock signal and a duty cycle of 75 1500D or 5DCH Figure 24 59 Internal Signal States of the PWM Signal Generation with 5 LTCs LT...

Page 1743: ...ate LTC01 Configuration Setup GPTA0_LTCXR01 0000 03E7H Load compare value 3E7H 999D GPTA0_LTCCTR01 0000 5C11H MOD 01B Compare Mode with LTC00 selected OSM 0 LTC01 continuously enabled SOH 0 SOL 1 compare enabled by low level at SI BYP 0 bypass in LTC02 is disabled EOA 0 LTC02 enabled for local events OCM 011B set LTC01OUT by a local event only OIA 1 output action defined by OCM must be performed i...

Page 1744: ...UT by a local event or copy the previous cell action OIA 1 output action defined by OCM must be performed immediately LTC04 Configuration Setup GPTA0_LTCXR04 0000 05DBH Load compare value 5DBH 1499D GPTA0_LTCCTR04 0000 3421H MOD 01B Compare Mode with LTC00 selected OSM 0 LTC04 continuously enabled SOH 1 SOL 0 compare enabled by high level at SI BYP 0 bypass in LTC04 is disabled EOA 0 LTC04 enabled...

Page 1745: ...odule provides a total of 56 input lines and 112 output lines assigned to seven I O groups IOG 6 0 and seven output groups OG 6 0 Figure 24 60 Input Output Line Sharing Unit Overview MCA05969 INT 3 0 Output Multiplexer OUT 55 00 GTC Input Multiplexer PDL 3 0 INT 3 0 CLK 7 0 LTC Input Multiplexer IN 55 00 OUT 111 56 GPTA Module Kernel OG0 Output Groups OG1 OG2 OG3 OG5 OG4 OG6 56 32 32 64 56 8 8 24 ...

Page 1746: ... LTC26 LTC27 LTC28 LTC29 LTC30 LTC31 LTC24OUT LTC25OUT LTC26OUT LTC27OUT LTC28OUT LTC29OUT LTC30OUT LTC31OUT GTC08IN GTC09IN GTC10IN GTC11IN GTC12IN GTC13IN GTC14IN GTC15IN GTC08 GTC09 GTC10 GTC11 GTC12 GTC13 GTC14 GTC15 GTC08OUT GTC09OUT GTC10OUT GTC11OUT GTC12OUT GTC13OUT GTC14OUT GTC15OUT Pin IO40 Pin IO41 Pin IO42 Pin IO43 Pin IO44 Pin IO45 Pin IO46 Pin IO47 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45...

Page 1747: ... clock distribution unit The FPC INT group is a group that combines the six level output signals SOL 5 0 of the FPCs with two external input lines INT 1 0 of the GPTA module The PDL INT group is a group that combines the four PDL output lines of the PDL bus with four external input lines INT 3 0 of the GPTA module Table 24 8 Group to I O Line Cell Assignment Group Module Cell Line Input Output LTC...

Page 1748: ...5 IN 47 40 OUT 47 40 IOG6 IN 55 48 OUT 55 48 Output Groups OG0 OUT 07 00 OG1 OUT 15 08 OG2 OUT 23 16 OG3 OUT 31 24 OG4 OUT 39 32 OG5 OUT 47 40 OG6 OUT 55 48 Clock Group CLK 7 0 FPC INT Groups FPC 5 0 SOT 5 0 External Input 1 0 INT 1 0 PDL INT Groups PDL 1 0 PDL Bus PDL 3 0 External Input 3 0 INT 3 0 Table 24 8 Group to I O Line Cell Assignment cont d Group Module Cell Line Input Output ...

Page 1749: ... from the I O groups are connected not programmable with the FPCk inputs The FPCk input line selection is controlled by the FPCCTRk IPS bit fields Table 24 23 shows the FPC port pin connections Table 24 9 FPC Input Line Assignments FPC Control Register Bit Field IPS Selected Input Pin FPCCTR0 000B IN0 IN12 001B 010B IN24 011B IN36 FPCCTR1 000B IN2 001B IN14 010B IN26 011B IN38 FPCCTR2 000B IN4 001...

Page 1750: ...t LTC groups LTCG 7 0 with 8 cells each In the same way I O groups and output groups are grouped into 14 groups seven I O groups and seven output groups with 8 lines each LTC Groups GTC Groups I O Groups Output Groups MCA05971 IOG0 IOG1 IOG2 IOG3 IOG4 IOG5 IOG6 8 GTCG0 GTC 07 00 GTCG1 GTC 15 08 GTCG2 GTC 23 16 GTCG3 GTC 31 24 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LT...

Page 1751: ... an I O or output group with the lowest index The remaining output lines OUT1 to OUT7 are connected to the I O or Output lines with ascending index Example for OMG13 see Figure 24 62 the outputs OUT0 to OUT7 are wired via OMG03 to input lines 0 to 7 of I O group 3 IOG3 One input of an I O or output group can be connected to the output of only one timer cell This is guaranteed by the OMG control re...

Page 1752: ...ds to the input of an I O or output group For example when looking at Figure 24 62 each of the eight output multiplexer output lines to I O group IOG5 is connected via three OMGn5 n 0 1 2 with the eight outputs of one GTC group GTCG1 and two LTC groups LTCG1 and LTCG5 Figure 24 64 Output Multiplexer Group Programmer s View The 1 level multiplexer is built up by three 8 1 multiplexers that are cont...

Page 1753: ...ntrol Register Assignments I O Group or Output Group Controlled by Multiplexer Control Register Selectable Groups via OMGng IOG0 IOG0 IN 03 00 OUT 03 00 OMCRL0 GTCG0 LTCG0 LTCG4 IN 07 04 OUT 07 04 OMCRH0 IOG1 IOG0 IN 11 08 OUT 11 08 OMCRL1 GTCG1 LTCG1 LTCG5 IN 15 12 OUT 15 12 OMCRH1 IOG2 IOG0 IN 19 16 OUT 19 16 OMCRL2 GTCG2 LTCG2 LTCG6 IN 23 20 OUT 23 20 OMCRH2 IOG3 IOG0 IN 27 24 OUT 27 24 OMCRL3 ...

Page 1754: ...MCRL11 GTCG3 LTCG3 LTCG7 OUT 95 92 OMCRH11 OG5 OUT 99 96 OMCRL12 GTCG0 LTCG0 LTCG4 OUT 103 100 OMCRH12 OG6 OUT 107 104 OMCRL13 GTCG1 LTCG1 LTCG5 OUT 111 108 OMCRH13 Table 24 10 Output Multiplexer Control Register Assignments cont d I O Group or Output Group Controlled by Multiplexer Control Register Selectable Groups via OMGng ...

Page 1755: ...e 32 4 8 LTC input lines organized into eight LTC groups Figure 24 65 GTC Input Multiplexer LTC Input Multiplexer LTC Groups I O Groups MCA05974 GTC Groups 8 IOG0 IOG1 IOG2 IOG3 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 LTCG6 LTC 55 48 LTCG7 LTC 63 56 GIMG 00 GIMG 02 GIMG 03 GIMG 10 GIMG 11 GIMG 12 GIMG 20 GIMG 21 GIMG 22 GIMG 23 LTCG4 LTC 39 32 GIMG 01 GTCG0 ...

Page 1756: ...e remaining lines cells or lines of a group are connected to GIMG input lines IN1 to IN7 with ascending index numbers At the FPC INT group FPC 5 0 is connected to IN 5 0 and INT 1 0 is connected to IN 7 6 Example for GIMG23 see Figure 24 65 the cells LTC24 up to LTC31 are wired to the GIMG23 input lines IN0 to line IN7 Multiplexer output OUT0 is always connected to the input of a GTC group with th...

Page 1757: ...ber 2 Local Timer Cell Groups LTCG 7 4 have group number 3 and the FPC INT group has group number 4 Index g indicates the number of the GTC group g g 0 3 to which the outputs of the input multiplexer group GIMGng are connected The GTC input multiplexer logic as seen for programming is shown in Figure 24 67 With this logic five group signals from an I O group LTC group or FPC INT group are always c...

Page 1758: ...l be held at a low level If one of these bit is not set the corresponding GTC input will be held at a low level Two GTC Input Multiplexer Control Registers GIMCRL and GIMCRH see also Page 24 198 are assigned to each of the GTC groups Therefore a total of eight registers control the connections within the GTC input multiplexer of the GPTA module The GIMCRL registers control the GIMG output lines 0 ...

Page 1759: ...110 Table 24 11 GTC Input Multiplexer Control Register Assignments GTC Group and GTCs Controlled by Multiplexer Control Register Selectable Groups via GIMGng GTCG0 GTC 03 00 GIMCRL0 IOG0 IOG4 LTCG0 LTCG4 FPC INT GTC 07 04 GIMCRH0 GTCG1 GTC 11 08 GIMCRL1 IOG1 IOG5 LTCG1 LTCG5 FPC INT GTC 15 12 GIMCRH1 GTCG2 GTC 19 16 GIMCRL2 IOG2 IOG6 LTCG2 LTCG6 FPC INT GTC 23 20 GIMCRH2 GTCG3 GTC 27 24 GIMCRL3 IO...

Page 1760: ... 68 LTC Input Multiplexer I O Groups GTC Groups MCA05977 LTC Groups 8 IOG0 IOG1 IOG2 IOG3 LIMG 00 LIMG 02 LIMG 03 LIMG 10 LIMG 11 LIMG 12 LIMG 20 LIMG 21 LIMG 22 LIMG 01 8 IOG6 IOG5 IOG4 PDL 3 0 INT 3 0 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 LTCG6 LTC 55 48 LTCG7 LTC 63 56 LTCG4 LTC 39 32 LIMG 04 LIMG 06 LIMG 07 LIMG 05 LIMG 14 LIMG 15 LIMG 16 GTCG0 GTC 07 ...

Page 1761: ...in an I O group or GTC group the line or the output of the cell with the lowest index number is connected to LIMG input line IN0 The remaining lines cells or lines of a group are connected to LIMG input lines IN1 to IN7 with ascending index numbers At the clock group CLK0 is connected to IN0 and the remaining clock lines are connected to LIMG input lines IN1 to IN7 with ascending index numbers At ...

Page 1762: ... variables n and g LIMGng Index n is a group number I O groups IOG 3 0 have group number 0 I O groups IOG 6 4 have group number 1 Global Timer Cell Groups GTCG 3 0 have group number 2 clock bus lines CLK 7 0 have group number 3 and the PDL INT group has group number 4 Index g indicates the number of the LTC group g g 0 7 to which the outputs of the input multiplexer group LIMGng are connected The ...

Page 1763: ...vel Two LTC Input Multiplexer Control Registers LIMCRL and LIMCRH see also Page 24 202 are assigned to each of the LTC groups Therefore a total of sixteen registers control the connections within the LTC input multiplexer of the GPTA module The LIMCRL registers control the LIMG output lines 0 to 3 and the GIMCRH registers control the LIMG output lines 4 to 7 Table 24 12 lists all LTC Input Multipl...

Page 1764: ...7 04 LIMCRH0 LTCG1 LTC 11 08 LIMCRL1 IOG1 IOG5 GTCG1 CLOCK PDL INT LTC 15 12 LIMCRH1 LTCG2 LTC 19 16 LIMCRL2 IOG2 IOG6 GTCG2 CLOCK PDL INT LTC 23 20 LIMCRH2 LTCG3 LTC 27 24 LIMCRL3 IOG3 GTCG3 CLOCK PDL INT LTC 31 28 LIMCRH3 LTCG4 LTC 35 32 LIMCRL4 IOG0 IOG4 GTCG0 CLOCK PDL INT LTC 39 36 LIMCRH4 LTCG5 LTC 43 40 LIMCRL5 IOG1 IOG5 GTCG1 CLOCK PDL INT LTC 47 44 LIMCRH5 LTCG6 LTC 51 48 LIMCRL6 IOG2 IOG...

Page 1765: ... register contents one after the other 52 values into MRADIN starting with the register values for OMCRH13 OMCRL13 up to GIMCRH0 GIMCRL0 see Figure 24 71 After the first MRADIN write operation the content for OMCRH13 is at FIFO position 1 With each following MRADIN write operation it becomes shifted one FIFO position upwards After the 52 MRADIN write operation the OMCRH13 value is at its final pos...

Page 1766: ...MRACTL MAEN 0 all cell inputs and outputs are disconnected from the GPIO lines and are driven with 0 Figure 24 71 GPTA Multiplexer Array Control Register FIFO Structure Multiplexer Register Array FIFO MCA05980 OMCRL13 31 OMCRH13 OMCRL0 OMCRH0 MRADOUT 0 LIMCRL7 LIMCRH7 LIMCRL0 LIMCRH0 Output Multiplexer Control Registers LTC Input Multiplexer Control Registers GIMCRL3 GIMCRH3 GIMCRL0 GIMCRH0 GTC In...

Page 1767: ... SRCy register Figure 24 72 Service Request Groups The bits in the Service Request State Registers SRSSx and SRSCx are service request status flags that are set by hardware type h when the related event occurs Each GPTA service request source has its own service request flag This flag is normally set by hardware but can be set and cleared by software Each service request status flag can be read tw...

Page 1768: ...ive if the corresponding service request is enabled by the related module Finally each service request group y must be enabled by the enable flag that is located in SRC register y Table 24 14 lists all of the service requests groups with its request sources Note that service requests of GTCs with an odd index number k can be individually redirected via register SRNR to a service request group that...

Page 1769: ...LTC24 LTC25 LTC26 LTC27 GTC132 29 LTC28 LTC29 LTC30 LTC31 GTC152 30 LTC32 LTC33 LTC34 LTC35 GTC172 31 LTC36 LTC37 LTC38 LTC39 GTC192 32 LTC40 LTC41 LTC42 LTC43 GTC212 33 LTC44 LTC45 LTC46 LTC47 GTC232 34 LTC48 LTC49 LTC50 LTC51 GTC252 35 LTC52 LTC53 LTC54 LTC55 GTC272 36 LTC56 LTC57 LTC58 LTC59 GTC292 37 LTC60 LTC61 LTC62 LTC63 GTC312 1 Redirection bit SRNR GTCkR 0 k 01 03 05 27 29 31 2 Redirectio...

Page 1770: ...ch FPCk Mode case PRESCALER_RISING if FPCk Rising_Edge then Prescaler endif break case PRESCALER_FALLING if FPCk Falling_Edge then Prescaler endif break case DELAYED_FILTER_BOTH Delayed_Filter break case IMMEDIATE_FILTER_BOTH case IMMEDIATE_FILTER_RISING case IMMEDIATE_FILTER_FALLING Immediate_Filter break case MIXED_FILTER_RISING_DELAYED if FPCk Signal_Filtered 0 then Delayed_Filter else Immediat...

Page 1771: ... Purpose Timer Array GPTA User s Manual 24 116 V2 0 2007 07 GPTA V2 0 Prescaler if FPCk Timer FPCk Compare_Value then generate pulse on FPCk Signal_Output Transition generate pulse on FPCk Signal_Output Level FPCk Timer 0 else FPCk Timer endif ...

Page 1772: ...me is over generate pulse on FPCk Signal_Output Transition FPCk Signal_Output Level FPCk Signal_Output Level FPCk Signal_Filtered FPCk Signal_Output Level endif FPCk Timer 0 else if FPCk Timer 0 then delay time is running if FPCk Rising_Edge is detected then edge detection done at clock input FPCk Rising_Edge_Glitch 1 else if FPCk Falling_Edge is detected then edge detection done at clock input FP...

Page 1773: ...FPCk Compare_Value 0 or FPCk Mode IMMEDIATE_FILTER_RISING and FPCk Signal_Input m or FPCk Mode IMMEDIATE_FILTER_FALLING and FPCk Signal_Input m then by pass FPCk Signal_Filtered FPCk Signal_Output Level else start delay time FPCk Timer endif endif else if FPCk Timer FPCk Compare_Value then delay time is over FPCk Timer 0 FPCk Signal_Filtered FPCk Signal_Output Level else delay time is running FPCk...

Page 1774: ...gnal_Input m SINm I Signal input selected by FPCk Input_Source FPCk Filter_Clock n CINn I Filter Clock selected by FPCk Clock_Source FPCk Rising_Edge RE L Signal coming from the edge detect FPCk Falling_Edge FE L Signal coming from the edge detect FPCk Signal_Filtered SF L Filtered output signal after delay time initialized to 0 at reset FPCk Signal_Output Transition FPCk Signal_Output Level SOTk ...

Page 1775: ..._FALLING MIXED_FILTER_RISING_DELAYED MIXED_FILTER_RISING_IMMEDIATE PRESCALER_RISING PRESCALER_FALLING FPCk Input_Source IPSk 3 Selects input signal FPCk Clock_Source CLKk 2 Selects FPC clock FPCk Rising_Edge_Glitch REGk 1 Bit is set when rising edge glitch occurs during filtering FPCk Falling_Edge_Glitch FEGk 1 Bit is set when falling edge glitch occurs during filtering FPCk Timer TIMk 16 Timer va...

Page 1776: ...Signal_Output Transition else x 1 S1 Level FPC3 Signal_Output Level S1 Transition FPC3 Signal_Output Transition S2 Level FPC4 Signal_Output Level S2 Transition FPC4 Signal_Output Transition S3 Level FPC5 Signal_Output Level S3 Transition FPC5 Signal_Output Transition endif if PDLx Three_Sensors_Enable then Three_Sensors else Two_Sensors endif if PDLx Mux then PDLx Signal_Output1 Level 1 if PDLx Si...

Page 1777: ... S2 Level and S1 Transition or S1 Level and S2 Level and S2 Transition then generate pulse on PDLx Signal_Forward else if S1 Level and S2 Level and S1 Transition or S1 Level and S2 Level and S2 Transition or S1 Level and S2 Level and S1 Transition or S1 Level and S2 Level and S2 Transition then generate pulse on PDLx Signal_Backward endif endif PDLx Signal_Output2 Level S3 Level PDLx Signal_Output...

Page 1778: ...nd S2 Level and S3 Level and S1 Transition or S1 Level and S2 Level and S3 Level and S3 Transition or S1 Level and S2 Level and S3 Level and S2 Transition or S1 Level and S2 Level and S3 Level and S1 Transition or S1 Level and S2 Level and S3 Level and S3 Transition or S1 Level and S2 Level and S3 Level and S2 Transition then generate pulse on PDLx Signal_Backward endif endif if S1 Level S2 Level ...

Page 1779: ... Transition PDLx Signal_Output1 Level SIT0 SIL0 SIT2 SIL2 O Transition Level of Output 1 signal going to DCM0 DCM2 PDLx Signal_Output2 Transition PDLx Signal_Output2 Level SIT1 SIL1 SIT3 SIL3 O Transition Level of Output 2 signal going to DCM1 DCM3 PDLx Signal_Forward F0 F1 O Forward signals to be counted by LTC PDLx Signal_Backward B0 B1 O Backward signals to be counted by LTC Name x 0 1 for PDL ...

Page 1780: ...07 07 GPTA V2 0 24 2 6 3 DCM Algorithm DCMk_Control_Logic to be performed every GPTA clock Compare Add_Clock Compare Add_Clock Check_Input if DCMk Timer DCMk Capcom_Value then trig DCMk Service_Request_Compare endif if DCMk Clock_Request then Generate DCMk Signal_Output DCMk Clock_Request 0 endif ...

Page 1781: ...com_Value DCMk Timer endif endif if DCMk Clear_On_Rising_Edge then DCMk Timer 0 else DCMk Timer endif if DCMk Clock_On_Rising_Edge then Generate pulse on DCMk Signal_Output endif else falling edge trig DCMk Service_Request_Falling if DCMk Capture_On_Rising_Edge then DCMk Capture_Value DCMk Timer else if DCMk Capcom_Opposite then DCMk Capcom_Value DCMk Timer endif endif if DCMk Clear_On_Falling_Edg...

Page 1782: ... 3 for DCM Short Name DCM Size bits Function DCMk Capture_On_Rising_Edge RCAk 1 Capture into Capture_Value on rising edge DCMk Capcom_Opposite OCAk 1 Capture into Capcom_Value on opposite edge defined by RCAk DCMk Clear_On_Rising_Edge RZEk 1 Clear Timer on rising edge DCMk Clear_On_Falling_Edge FZEk 1 Clear Timer on falling edge DCMk Clock_On_Rising_Edge RCKk 1 Generate a single clock pulse on ris...

Page 1783: ...m_End or Pll Automatic_End then compensation finished or no automatic compensation Pll Counter_Mtick Pll Number_Mtick Pll Perfom_End 0 endif if Pll Counter_Mtick 0 and Pll Perform_End or Bit 24 of Pll Delta then output pulse is necessary generate pulse on Pll Signal_Output Pll Counter_Mtick if Pll Counter_Mtick 0 then trig Pll Service_Request_Trigger endif endif if Bit 24 of Pll Delta then delta i...

Page 1784: ...rigger SQT O Service request when Counter reaches zero Name Short Name PLL Size bits Function Pll Mux MUX 2 Selects the signal input for PLL Pll Automatic_End AEN 1 Performs the acceleration deceleration correction Pll Perform_End PEN 1 Makes it possible to decrement the Counter at full speed Pll Request_Enable REN 1 Allows a request when microtick counter reaches zero Pll Number_Mtick MTI 16 Numb...

Page 1785: ...endif endif endif Name m 0 1 for GT p 0 to 7 for Clock Bus Short Name GT Used ILO Comment GTm Clock_In p CINmp I Input coming from clock bus GTm Timer_Greater_Equal_Comp TGEm O Timer is greater or equal GTm Timer_Event TEVm O Signal for timer change GTm Service_Request_Trigger SQTm O Service request line Name m 0 1 for GT Short Name GT Size bits Function GTm Run RUNm 1 Enables timer GTm Scale_Comp...

Page 1786: ...pture m if GTCk Cell_Enable then switch GTCk Mode case CAPTURE_T0 Capture 0 break case CAPTURE_T1 Capture 1 break case COMPARE_T0 Compare 0 break case COMPARE_T1 Compare 1 endswitch if GTCk One_Shot_Mode and GTCk Event then GTCk Cell_Enable 0 endif endif Manage_Mux if GTCk Signal_Input then trig GTCk Service_Request_Trigger GTCk X GTm Timer GTCk Event 1 else GTCk Event 0 endif Ck Event 0 ...

Page 1787: ...m Timer and GTCk X_Write_Access or GTm Timer_Event or GTCk Greater_Equal_Select and GTCk X_Write_Access and GTm Timer_Greater_Equal_Comp then if GTCk Capture_After_Compare then if GTCk Capture_Alternate_Timer then GTCk X GT m Timer else GTCk X GTm Timer endif endif trig GTCk Service_Request_Trigger GTCk Event 1 else GTCk Event 0 endif ...

Page 1788: ...Output_Control_Mode 2 then bypass input link enabled GTCk Output_Mode_Out GTCk Output_Mode_In else bypass input link disabled GTCk Output_Mode_Out 00B endif endif else no local event if GTCk Output_Control_Mode 2 then input link enabled Set_Data_Out GTCk Output_Mode_In GTCk Output_Mode_Out GTCk Output_Mode_In else input link disabled Set_Data_Out 00B GTCk Output_Mode_Out 00B endif endif if GTCk En...

Page 1789: ...PTA User s Manual 24 134 V2 0 2007 07 GPTA V2 0 Set_Data_Out mode switch mode case 00B no change break case 01B toggle GTCk Data_Out GTCk Data_Out break case 10B clear GTCk Data_Out 0 break case 11B set GTCk Data_Out 1 break endswitch GTCk Output_State GTCk Data_Out ...

Page 1790: ...Timer_Event TEVm I Signal for timer change GTm Timer TIMm I Timer value GTCk Data_In DINk I Data input from input multiplexer GTCk Output_Mode_In M1Ik M0Ik I Link signals from preceding cell GTCk X_Write_Access XWA L Indicates that GTCk X was modified GTCk Event EVE L Local event GTCk Signal_Input INS L Qualified input signal GTCk Service_Request_Trigger SQSk O Service request line GTCk Data_Out D...

Page 1791: ...g edge of input pin Selects Compare Mode GTCk Input_Falling_Edge_Select Capture Mode GTCk Capture_After_Compare Compare Mode FEDk CACk 1 1 Selects falling edge of input pin Selects capture after compare GTCk Capture_Alternate_Timer Compare Mode CATk 1 Capture alternate global timer after compare GTCk Bypass BYPk 1 Local events bypassed for output link GTCk Enable_Of_Action EOAk 1 Enables cell on a...

Page 1792: ...l_Logic to be performed every GPTA clock if LTCk Cell_Enable then switch LTCk Mode case TIMER_FREE_RUN LTCk Reset_Timer_Bit 0 Timer break case TIMER_RESET if LTCk Event_In then LTCk Reset_Timer_Bit 1 endif Timer break case CAPTURE Capture break case COMPARE Compare break endswitch if LTCk One_Shot_Mode and LTCk Event then LTCk Cell_Enable 0 endif endif Manage_Mux ...

Page 1793: ...mer overflow or software reset trig LTCk Service_Request_Trigger LTCk Event 1 else LTCk Event 0 endif if LTCk Signal_Input then if LTCk Reset_Timer_Bit then timer must be reset LTCk Reset_Timer_Bit 0 LTCk X 0xFFFF if LTCk Coherent_Update_Enable then LTCk Select_Line_Value LTCk Select_Line_Value LTCk Coherent_Update_Enable 0 endif else timer runs normally LTCk X endif endif LTCk Event_Out LTCk Even...

Page 1794: ...TCk Event 1 else LTCk Event 0 endif LTCk Event_Out LTCk Event if LTCk Select_In and LTCk Select_On_High_Level or LTCk Select_In and LTCk Select_On_Low_Level then cell is active if LTCk X LTCk Y_In and LTCk X_Write_Access or LTCk Timer_Event_In then event trig LTCk Service_Request_Trigger LTCk Event 1 else LTCk Event 0 endif LTCk Event_Out LTCk Event else cell is inactive LTCk Event_Out LTCk Event_...

Page 1795: ...LTCk Select_In endif if LTCk Event then local event Set_Data_Out LTCk Output_Control_Mode 1 0 if LTCk Bypass then no bypass LTCk Output_Mode_Out LTCk Output_Control_Mode 1 0 else if LTCk Output_Control_Mode 2 then bypass input link enabled LTCk Output_Mode_Out LTCk Output_Mode_In else bypass input link disabled LTCk Output_Mode_Out 00B endif endif else no local event if LTCk Output_Control_Mode 2 ...

Page 1796: ...PTA User s Manual 24 141 V2 0 2007 07 GPTA V2 0 Set_Data_Out mode switch mode case 00B no change break case 01B toggle LTCk Data_Out LTCk Data_Out break case 10B clear LTCk Data_Out 0 break case 11B set LTCk Data_Out 1 break endswitch LTCk Output_State LTCk Data_Out ...

Page 1797: ... Select signal from preceding cell LTCk X_Write_Access XWA L Indicates that LTCk X was modified LTCk Select_Line_Value SLV L Internal value for select line reset value 0 LTCk Signal_Input INS L Qualified input signal for Timer Mode and Capture Mode LTCk Reset_Timer_Bit RTM L Flipflop to reset timer on next clock LTCk Event EVE L Local event LTCk Data_Out DOUk O Data output for output multiplexer L...

Page 1798: ...Capture Mode LTCk Select_On_High_Level Compare Mode FEDk SOHk 1 1 Selects falling edge of input pin Enables compare on high level of select line LTCk Bypass Capture Mode Compare Mode BYPk 1 Local events bypassed for output link LTCk Enable_Of_Action Capture Mode Compare Mode EOAk 1 Enables cell on action communicated via link LTCk Input_Line_Mode ILMk 1 Selects edge input line mode LTCk Coherent_U...

Page 1799: ...07 07 GPTA V2 0 24 2 6 8 LTC Algorithm for Cell 63 LTC63_Control_Logic to be performed every GPTA clock Copy Copy Compare if LTC63 Cell_Enable then if LTC63 Signal_Input then LTC63 X LTC63 X_Shadow trig LTC63 Service_Request_Trigger if LTC63 One_Shot_Mode then LTC63 Cell_Enable 0 endif endif endif ...

Page 1800: ..._Rev_Mode then LTC63 Y_Comp LTC63 Y_Rev else LTC63 Y_Comp LTC63 Y_In endif if LTC63 X LTC63 Y_Comp or LTC63 X FFFFH then output must be 1 LTC63 Data_Out 1 LTC63 Event_Out 0 else output must be 0 if LTC63 Data_Out 1 then falling edge on output trig LTC63 Service_Request_Trigger LTC63 Event_Out 1 else LTC63 Event_Out 0 endif LTC63 Data_Out 0 endif LTC63 Output_State LTC63 Data_Out endif ...

Page 1801: ...ing from preceding cell LTC63 Timer_Event_In TI63 I Signal for timer change from preceding cell LTC63 Y_Rev YR L Timer coming from preceding cell bit reversed LTC63 Y_Comp YC L Timer actually used for compare LTC63 X_Write_Access XWA L Indicates that LTC63 X was modified LTC63 Signal_Input INS L Qualified input signal LTC63 Data_Out DOU63 O Data output for output multiplexer LTC63 Service_Request_...

Page 1802: ...for copy LTC63 Request_Enable REN63 2 Allows a request on compare or copy LTC63 Input_Rising_Edge_Select RED63 1 Selects rising edge of input pin LTC63 Input_Falling_Edge_Select FED63 1 Selects falling edge of input pin LTC63 Input_Line_Mode ILM63 1 Selects edge input line mode LTC63 Cell_Enable CEN63 1 Cell enable state for copy LTC63 Output_State OUT63 1 Read value of Data_Out LTC63 X X63 16 Com...

Page 1803: ... tasks to be implemented for getting a GPTA unit into operation Table 24 15 Software Tasks Controlling a GPTA Unit GPTA Shell Initialization GPTA Module Clock Enable Fractional Divider Setting Module Enable Configuration of Interrupt Handling GPTA Kernel Initialization FPC PDL Selection of Operating Mode Prescaler Filter or Feed Through Selection of Operating Mode Phase Discriminator or Feed Throu...

Page 1804: ...Event Start Global Timer s Configuration of Data Output triggered by a GTC Event LTC IOLS Selection of Operating Mode Timer Capture or Compare Configuration of the Multiplexer Array to link GTC and LTC data outputs inputs to external Port Pins or other cells by writing the Multiplexer Register Array FIFO Selection of Trigger Source for Timer Capture or Compare Mode Configuration of Port Output Sou...

Page 1805: ... are located in the following address ranges Table 24 16 Registers Address Space Module Base Address End Address Note GPTA0 F000 1800H F000 1FFFH GPTA1 F000 2000H F000 27FFH LTCA2 F000 2800H F000 2FFFH 1 k 0 5 2 k 0 3 3 k 0 2 4 k 00 31 5 k 00 63 6 n 0 3 7 g 0 13 8 g 0 7 9 g 0 3 MCA05982_mod FPCTIMk Control Registers Interrupt IOLS Registers Data Registers DCMTIMk DCMCAVk SRSCn DCMCOVk PLLMTI PLLST...

Page 1806: ...3 02CH Page 24 214 SRNR Service Request Node Redirection Register 030H Page 24 215 MRACTL Multiplexer Register Array Control Register 038H Page 24 191 MRADIN Multiplexer Register Array Data In Register 03CH Page 24 193 MRADOUT Multiplexer Register Array Data Out Register 040H Page 24 193 FPCSTAT Filter and Prescaler Cell Status Register 044H Page 24 155 FPCCTRk Filter and Prescaler Cell Control Re...

Page 1807: ... 170 GTREVk Global Timer Reload Value Register k k 0 1 0E0H k 16 4 Page 24 172 GTTIMk Global Timer Register k k 0 1 0E0H k 16 8 Page 24 171 GTCCTRk Global Timer Cell Control Register k k 00 31 100H k 8 Page 24 175 Page 24 177 GTCXRk Global Timer Cell X Register k k 00 31 100H k 8 4 Page 24 179 LTCCTRk Local Timer Cell Control Register k k 00 62 200H k 8 Page 24 180 Page 24 183 Page 24 185 LTCXRk L...

Page 1808: ... marked in the corresponding bit descriptions OMCRLg Output Multiplexer Control Register for Lower Half of Group g g 0 13 not directly addressable see Page 24 110 Page 24 194 OMCRLg Output Multiplexer Control Register for Upper Half of Group g g 0 13 Page 24 196 GIMCRLg Input Multiplexer Control Register for Lower Half of GTC Group g g 3 0 Page 24 198 GIMCRLg Input Multiplexer Control Register for...

Page 1809: ...et Value 0029 C0XXH GPTA1_ID GPTA1 Module Identification Register 008H Reset Value 0029 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 1...

Page 1810: ...EG 4 FEG 3 FEG 2 FEG 1 FEG 0 0 REG 5 REG 4 REG 3 REG 2 REG 1 REG 0 r rwh rwh rwh rwh rwh rwh r rwh rwh rwh rwh rwh rwh Field Bits Type Description REGk k 0 5 k rwh Rising Edge Glitch Flag for FPCk 0B No rising edge of glitch detected during filtering 1B Rising edge of glitch detected during filtering Bits REGk are bit protected see Section 24 3 2 FEGk k 0 5 k 8 rwh Falling Edge Glitch Flag for FPC...

Page 1811: ...ld Value of Filter and Prescaler Cell k CMP is the 16 bit threshold value that is compared with the 16 bit timer value FPCTIMk TIM MOD 18 16 rw Operation Mode Selection for FPCk 000B Delayed Debounce Filter Mode on both edges 001B Immediate Debounce Filter Mode on both edges 010B Rising edge Immediate Debounce Filter Mode falling edge no filtering 011B Rising edge no filtering falling edge Immedia...

Page 1812: ... CLK 23 22 rw Clock Selection for FPCk CLK selects the clock signal used for edge detection 00B CIock input line 0 selected GPTA module clock fGPTA 01B Clock bus line 1 selected local PLL clock 10B Clock bus line 2 selected prescaled GPTA module clock fGPTA or PLL clock from other unit or DCM 3 clock 11B Clock bus line 3 selected DCM 2 clock or PLL clock of other unit or uncompensated PLL clock or...

Page 1813: ...lter and Prescaler Cell Timer Register k 048H k 8H 4H Reset Value 0000 0000H GPTA1_FPCTIMk k 0 5 GPTA1 Filter and Prescaler Cell Timer Register k 048H k 8H 4H Reset Value 0000 0000H 31 16 15 0 0 TIM r rwh Field Bits Type Description TIM 15 0 rwh Timer Value of Filter and Prescaler Cell k 0 31 16 r Reserved Read as 0 should be written with 0 ...

Page 1814: ...h rw rw r rwh rw rw Field Bits Type Description MUX0 0 rw Output Signal Source Selection for PDL0 0B DCM0 cell input is driven by fed through FPC0 output lines 1B DCM0 cell input is provided with PDL0 Forward and Backward pulses TSE0 1 rw 3 Sensor Mode Enable for PDL0 0B PDL0 operates in 2 Sensor Mode and DCM1 cell input is driven by fed through FPC2 output lines 1B PDL0 operates in 3 Sensor Mode ...

Page 1815: ...ensor Mode Enable for PDL1 0B PDL1 operates in 2 Sensor Mode and DCM3 cell input is driven by fed through FPC5 output lines 1B PDL1 operates in 3 Sensor Mode and DCM3 cell input is provided with PDL1 error information ERR1 6 rwh Error Flag for PDL1 0B No error has occurred 1B Error detected in 3 Sensor Mode all PDL1 input signals are simultaneously provided with high or low level Bit ERR1 is bit p...

Page 1816: ...w rw rw rw rw rw rw Field Bits Type Description RCA 0 rw Trigger Source Selection for Capture Event 0B Timer contents are copied to DCMCAVk capture register on a falling input signal edge 1B Timer contents are copied to capture register on a rising input signal edge OCA 1 rw Trigger Source for Capture Compare Register Update 0B Capture Compare register DCMCOVk is not affected 1B Timer contents are...

Page 1817: ... Output Pulse Generation 0B DCM output line is not affected 1B DCM output line is immediately provided with a single clock pulse QCK is always read as 0 RRE 7 rw Interrupt Request on Rising Edge 0B Interrupt request is not affected 1B Interrupt request is set on rising input signal edge FRE 8 rw Interrupt Request on Falling Edge 0B Interrupt request is not affected 1B Interrupt request is set on f...

Page 1818: ...t Value 0000 0000H 31 24 23 0 0 TIM r rwh Field Bits Type Description TIM 23 0 rwh Timer Value of DCMk 0 31 24 r Reserved Read as 0 should be written with 0 GPTA0_DCMCAVk k 0 3 GPTA0 Duty Cycle Measurement Capture Register k 088H k 10H Reset Value 0000 0000H GPTA1_DCMCAVk k 0 3 GPTA1 Duty Cycle Measurement Capture Register k 088H k 10H Reset Value 0000 0000H 31 24 23 0 0 CAV r rwh Field Bits Type ...

Page 1819: ...Cycle Measurement Capture Compare Register k 08CH k 10H Reset Value 0000 0000H GPTA1_DCMCOVk k 0 3 GPTA1 Duty Cycle Measurement Capture Compare Register k 08CH k 10H Reset Value 0000 0000H 31 24 23 0 0 COV r rwh Field Bits Type Description COV 23 0 rwh Capture Compare Register Value of DCMk 0 31 24 r Reserved Read as 0 should be written with 0 ...

Page 1820: ...selected as PLL input 01B DCM1 output is selected as PLL input 10B DCM2 output is selected as PLL input 11B DCM3 output is selected as PLL input AEN 2 rw Compensation of Input Period Length Variation 0B Compensation of input signal s period length variation is disabled 1B Compensation of input signal s period length variation acceleration deceleration is requested PEN 3 rwh Unexpected Period End B...

Page 1821: ...erated reaches zero 0 31 5 r Reserved Read as 0 should be written with 0 GPTA0_PLLMTI GPTA0 Phase Locked Loop Microtick Register 0C4H Reset Value 0000 0000H GPTA1_PLLMTI GPTA1 Phase Locked Loop Microtick Register 0C4H Reset Value 0000 0000H 31 16 15 0 0 MTI r rw Field Bits Type Description MTI 15 0 rw Microtick Value Number of output pulses to be generated within one input signal period 0 31 16 r ...

Page 1822: ... 0 rw Step Value Number of output pulses to be generated within one input signal period 2 complement data format 0 31 16 r Reserved Read as 0 should be written with 0 GPTA0_PLLCNT GPTA0 Phase Locked Loop Counter Register 0C8H Reset Value 0000 0000H GPTA1_PLLCNT GPTA1 Phase Locked Loop Counter Register 0C8H Reset Value 0000 0000H 31 16 15 0 0 CNT r rwh Field Bits Type Description CNT 15 0 rwh Pulse...

Page 1823: ...n of the number of output pulses to be generated within one input signal period from the input signal s period length measured in number of GPTA module clocks 0 31 24 r Reserved Read as 0 should be written with 0 GPTA0_PLLDTR GPTA0 Phase Locked Loop Delta Register 0D4H Reset Value 0000 0000H GPTA1_PLLDTR GPTA1 Phase Locked Loop Delta Register 0D4H Reset Value 0000 0000H 31 25 24 0 0 DTR r rwh Fiel...

Page 1824: ...TC1796 Peripheral Units Vol 2 of 2 General Purpose Timer Array GPTA User s Manual 24 169 V2 0 2007 07 GPTA V2 0 0 31 25 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1825: ...O 3 0 rw TGE Flag Source Selection This bit field determines the bit of the operation result GTk timer value data bus value which is used as TGE flag 0000B 10th bit is used as TGE flag 0001B 11th bit is used as TGE flag B 1110B 24th bit is used as TGE flag 1111B 25th bit is used as TGE flag MUX 6 4 rw Timer Clock Selection One of eight available clock bus lines is selected as the timer GTk clock 0...

Page 1826: ... when timer GTk overflows 0 31 8 r Reserved Read as 0 should be written with 0 GPTA0_GTTIMk k 0 1 GPTA0 Global Timer Register k 0E8H k 10H Reset Value 0000 0000H GPTA1_GTTIMk k 0 1 GPTA1 Global Timer Register k 0E8H k 10H Reset Value 0000 0000H 31 24 23 0 0 TIM r rwh Field Bits Type Description TIM 23 0 rwh Timer Value of Global Timer k 0 31 24 r Reserved Read as 0 should be written with 0 Field B...

Page 1827: ...er Reload Value Register k 0E4H k 10H Reset Value 0000 0000H GPTA1_GTREVk k 0 1 GPTA1 Global Timer Reload Value Register k 0E4H k 10H Reset Value 0000 0000H 31 24 23 0 0 REV r rwh Field Bits Type Description REV 23 0 rw Reload Value of Global Timer k Reload value for timer GTk after an overflow 0 31 24 r Reserved Read as 0 should be written with 0 ...

Page 1828: ... 1D CLK2 is provided with fGPTA divided by 21 D 12D CLK2 is provided with fGPTA divided by 212 13D CLK2 is provided with fGPTA divided by 213 14D CLK2 is driven by PLL clock of other GPTA unit 15D CLK2 is driven by DCM3 output DFA04 7 4 rw Clock Line 4 Driving Source Selection 0D CLK4 is provided with fGPTA 1D CLK4 is provided with fGPTA divided by 21 D 13D CLK4 is provided with fGPTA divided by 2...

Page 1829: ...ine 3 Driving Source Selection 0D CLK3 is driven by DCM2 output 1D CLK3 is driven by PLL clock of other GPTA unit 2D CLK3 is driven by uncompensated PLL clock 3D CLK3 is driven by uncompensated PLL clock of other GPTA unit DFALTC 20 18 rw Dividing Factor for LTC Prescaler Clock Selection The LTCPRE clock is provided with the GPTA module clock fGPTA divided by 2DFALTC 0D LTCPRE clock is fGPTA 1D LT...

Page 1830: ...0 rw Mode Control Bits 00B GTCk operates in Capture Mode hooked to GT0 01B GTCk operates in Capture Mode hooked to GT1 10B GTCk operates in Compare Mode hooked to GT0 11B GTCk operates in Compare Mode hooked to GT1 OSM 2 rw One Shot Mode Enable 0B GTCk is continuously enabled 1B GTCk is enabled for one event only REN 3 rw Interrupt Request Enable 0B Service request is disabled 1B Service request l...

Page 1831: ... 10 rh Cell Enable 0B GTCk is currently disabled for local events 1B GTCk is currently enabled for local events OCM 13 11 rw Output Control Mode Select X00B Current state of GTCkOUT output line is hold X01B Current state of GTCkOUT output line is toggled X10B GTCkOUT output line is forced to 0 X11B GTCkOUT output line is forced to 1 0XXB GTCkOUT output line state is set by an internal GTCk event o...

Page 1832: ...EOA BYP CAT CAC GES REN OSM MOD rh rw rw rh r rwh rw rw rw rw rw rw rw Field Bits Type Description MOD 1 0 rw Mode Control Bits 00B GTCk operates in Capture Mode hooked to GT0 01B GTCk operates in Capture Mode hooked to GT1 10B GTCk operates in Compare Mode hooked to GT0 11B GTCk operates in Compare Mode hooked to GT1 OSM 2 rw One Shot Mode Enable 0B GTCk is continuously enabled 1B GTCk is enabled...

Page 1833: ... enable reaction on M0I M1I changes EOA 8 rwh Enable On Action 0B GTCk is enabled for local events 1B GTCk is disabled for local events On an event on the communication link via M0I M1I lines EOA will be cleared and local events will be enabled This bit is protected during read modify write operations hardware will win CEN 10 rh Cell Enable 0B GTCk is currently disabled for local events 1B GTCk is...

Page 1834: ...utput Immediate Action 0B No immediate action required 1B Action defined by OCM must be performed immediately Reading bit OIA always returns 0 OUT 15 rh Output State 0B GTCkOUT output line is 0 1B GTCkOUT output line is 1 0 9 31 16 r Reserved Read as 0 should be written with 0 GPTA0_GTCXRk k 00 31 GPTA0 Global Timer Cell X Register k 104H k 8H Reset Value 0000 0000H GPTA1_GTCXRk k 00 31 GPTA1 Glob...

Page 1835: ...tion MOD 1 0 rw Mode Control Bits 00B LTCk operates in Capture Mode 01B LTCk operates in Compare Mode 10B LTCk operates in Free Running Timer Mode 11B LTCk operates in Reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event ha...

Page 1836: ...B No effect 1B Coherent update disabled bit CUD is cleared If bits CUD and CUDCLR are both written with 1 bit CUD will be set CUDCLR is always read as 0 ILM 8 rw Input Line Mode 0B Input line is operating in Edge Sensitive Mode 1B Input line is operating in Level Sensitive Mode In case of full speed GPTA module clock selection as input clock Level Sensitive Mode must be selected In this case the E...

Page 1837: ... forced to 0 X11B LTCkOUT output line is forced to 1 0XXB LTCkOUT output line state is set by an internal LTCk event only 1XXB LTCkOUT output line state is affected by an internal LTCk event and or by an operation occurred in an adjacent LTCk cell reported by M1I M0I interface lines OIA 14 rw Output Immediate Action 0B No immediate action required 1B Action defined by bit field OCM must be perform...

Page 1838: ...perates in Free Running Timer Mode 11B LTCk operates in Reset Timer Mode OSM 2 rw One Shot Mode Enable 0B LTCk is continuously enabled 1B LTCk is enabled for one event only REN 3 rw Request Enable 0B Service request is disabled 1B Service request SQSk is activated when a capture event has occurred compare event has occurred timer overflow has happened depending on the operation mode selected by bi...

Page 1839: ...de 1B Input line is operating in Level Sensitive Mode In case of full speed GPTA module clock selection as input clock Level Sensitive Mode must be selected In this case the Edge Sensitive Mode will not produce any event SLL 9 rh Capture Compare Mode Select Line Level 0B Current state of select input SI is 0 1B Current state of select input SI is 1 CEN 10 rh Cell Enable 0B LTCk is currently disabl...

Page 1840: ... k 00 62 Local Timer Cell Control Register k Compare Mode 200H k 8H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUT OIA OCM CEN SLL ILM EOA BYP SOH SOL REN OSM MOD rh rw rw rh rh rw rwh rw rw rw rw rw rw Field Bits Type Description MOD 1 0 rw Mode Control Bits 00B LTCk operates in Capture Mode 01B LTCk operates in Compare Mode 10...

Page 1841: ...ss 0B M0O M1O lines are affected either by M0I M1I lines or by OCM0 OCM1 bits 1B M0O M1O lines are affected only by M0I M1I lines This bit is cleared if mode is switched to Timer Mode OCM2 must be set in any case to enable reaction on M0I M1I change EOA 7 rwh Enable On Action 0B LTCk is enabled for local events 1B LTCk is disabled for local events On an event on the communication link via M0I M1I ...

Page 1842: ...OUT output line is forced to 0 X11B LTCkOUT output line is forced to 1 0XXB LTCkOUT output line state is set by an internal LTCk event only 1XXB LTCkOUT output line state is affected by an internal LTCk event and or by an operation occurred in an adjacent LTCk cell reported by M1I M0I interface lines OIA 14 rw Output Immediate Action 0B No immediate action required 1B Action defined by bit field O...

Page 1843: ...ster Copy 0B Shadow register copy is continuously enabled 1B Shadow register copy is enabled for one event only REN 3 2 rw Request Enable 00B Service request SQT63 is disabled 01B Service request SQT63 is generated when a compare event has occurred 10B Service request SQT63 is generated when a shadow register copy event has occurred 11B Reserved RED 4 rw Rising Edge Select for Shadow Register Copy...

Page 1844: ...ng in Edge Sensitive Mode 1B LTC63IN is operating in Level Sensitive Mode CEN 10 rh Enable for Shadow Register Copy 0B Shadow register copy is currently disabled 1B Shadow register copy is currently enabled OUT 15 rh Output State 0B LTC63OUT output line is 0 1B LTC63OUT output line is 1 0 7 6 9 14 11 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1845: ...H k 8H Reset Value 0000 0000H 31 16 15 0 0 X r rwh Field Bits Type Description X 15 0 rwh Local Timer Data Register Value 0 31 16 r Reserved Read as 0 should be written with 0 LTCXR63 Local Timer Cell X Register 63 3FCH Reset Value 0000 0000H 31 16 15 0 XS X rw rwh Field Bits Type Description X 15 0 rwh Compare Register Value XS 31 16 rw Shadow Register Value ...

Page 1846: ...0 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FIFOFILLCNT 0 FIFO FUL L WCR ES MA EN r r r r w rw Field Bits Type Description MAEN 0 rw Multiplexer Array Enable Bit field MAEN enables disables the programming and the interconnections of the multiplexer array 0B Multiplexer array is disabled all cell inputs are driven with 0 GPTA I O lines pins a...

Page 1847: ...pletely written write access to MRADIN allowed 1B FIFO completely written write access to MRADIN ignored Must be re enabled by WCRES 0 before array can be re initialized FIFOFILLCNT 13 8 r FIFO Fill Count This bit field shows the current contents of the write cycle counter 0 7 3 31 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1848: ...any bus error MRADIN Multiplexer Register Array Data In Register 03CH Reset Value 0000 0000H 31 0 DATAIN w Field Bits Type Description DATAIN 31 0 w FIFO Write Data This register contains the FIFO write data as defined for the Output Multiplexer Control Registers the GTC Input Multiplexer Control Registers or the LTC Input Multiplexer Control Registers MRADOUT Multiplexer Register Array Data Out R...

Page 1849: ... 3 OMCRH controls the connections of group pins 4 to 7 OMCRLg g 0 13 Output Multiplexer Control Register for Lower Half of Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 OMG3 0 OML3 0 OMG2 0 OML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OMG1 0 OML1 0 OMG0 0 OML0 r rw r rw r rw r rw Field Bits Type Description OML0 OML1 OML2 OML3 2 0 10 8 18 16 2...

Page 1850: ...d to input n of I O Group g or Output group g 7 X00B OMG0g selected X01B OMG1g selected X10B OMG2g selected All other combinations are reserved If a reserved combination of OMGn value is selected the corresponding OMG output is forced to 0 level For compatibility reasons OMGn 2 0 should be used as value for X for OMGn bit field programming 0 3 7 11 15 19 23 27 31 r Reserved Read as 0 should be wri...

Page 1851: ...that can be selected by bit field OMGn for OMG output n 000B OMG input IN0 selected 001B OMG input IN1 selected 010B OMG input IN2 selected 011B OMG input IN3 selected 100B OMG input IN4 selected 101B OMG input IN5 selected 110B OMG input IN6 selected 111B OMG input IN7 selected OMG4 OMG5 OMG6 OMG7 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the OMGng which is co...

Page 1852: ...96 Peripheral Units Vol 2 of 2 General Purpose Timer Array GPTA User s Manual 24 197 V2 0 2007 07 GPTA V2 0 0 3 7 11 15 19 23 27 31 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1853: ...ol Register for Lower Half of GTC Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GIM EN3 GIMG3 0 GIML3 GIM EN2 GIMG2 0 GIML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIM EN1 GIMG1 0 GIML1 GIM EN0 GIMG0 0 GIML0 rw rw r rw rw rw r rw Field Bits Type Description GIML0 GIML1 GIML2 GIML3 2 0 10 8 18 16 26 24 rw Multiplexer Line Selection This bit field s...

Page 1854: ... to input n of GTC group g 000B GIMG0g selected 001B GIMG1g selected reserved for g 3 010B GIMG2g selected 011B GIMG3g selected 100B GIMG4g selected All other combinations are reserved GIMEN0 GIMEN1 GIMEN2 GIMEN3 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by GIMLn and GIMGn 0 3 11 19 27 r Reserved Read as 0 should...

Page 1855: ...16 26 24 rw Multiplexer Line Selection This bit field selects the input line of a GIMG that can be selected by bit field GIMGn for GIMG output n 000B LIMG input IN0 selected 001B LIMG input IN1 selected 010B LIMG input IN2 selected 011B LIMG input IN3 selected 100B LIMG input IN4 selected 101B LIMG input IN5 selected 110B LIMG input IN6 selected 111B LIMG input IN7 selected GIMG4 GIMG5 GIMG6 GIMG7...

Page 1856: ...01 V2 0 2007 07 GPTA V2 0 GIMEN4 GIMEN5 GIMEN6 GIMEN7 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by GIMLn and GIMGn 0 3 11 19 27 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1857: ...er Control Register for Lower Half of LTC Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LIM EN3 LIMG3 0 LIML3 LIM EN2 LIMG2 0 LIML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIM EN1 LIMG1 0 LIML1 LIM EN0 LIMG0 0 LIML0 r rw r rw r rw r rw Field Bits Type Description LIML0 LIML1 LIML2 LIML3 2 0 10 8 18 16 26 24 rw Multiplexer Line Selection This bit f...

Page 1858: ...to input n of LTC group g 000B LIMG0g selected 001B LIMG1g selected reserved for g 3 7 010B LIMG2g selected 011B LIMG3g selected 100B LIMG4g selected All other combinations are reserved LIMEN0 LIMEN1 LIMEN2 LIMEN3 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by LIMLn and LIMGn 0 3 11 19 27 r Reserved Read as 0 shoul...

Page 1859: ...6 26 24 rw Multiplexer Line Selection This bit field selects the input line of a LIMG that can be selected by bit field LIMGn for LIMG output n 000B LIMG input IN0 selected 001B LIMG input IN1 selected 010B LIMG input IN2 selected 011B LIMG input IN3 selected 100B LIMG input IN4 selected 101B LIMG input IN5 selected 110B LIMG input IN6 selected 111B LIMG input IN7 selected LIMG4 LIMG5 LIMG6 LIMG7 ...

Page 1860: ...05 V2 0 2007 07 GPTA V2 0 LIMEN4 LIMEN5 LIMEN6 LIMEN7 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by LIMLn and LIMGn 0 3 11 19 27 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1861: ...ding bit location in the SRSSx registers Writing a 0 has no effect GPTA0_SRSC0 GPTA0 Service Request State Clear Register 0 010H Reset Value 0000 0000H GPTA1_SRSC0 GPTA1 Service Request State Clear Register 0 010H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 GT 01 GT 00 PLL DCM 03C DCM 03F DCM 03R DCM 02C DCM 02F DCM 02R DCM 01C...

Page 1862: ...vice is requested because the counter for the number remaining output pulses decremented to 0 GT00 13 rwh GT0 Timer Service Request State 0B No service is requested 1B Service is requested due to a GT0 timer overflow GT01 14 rwh GT1 Timer Service Request State 0B No service is requested 1B Service is requested due to a GT1 timer overflow 0 31 15 r Reserved Read as 0 should be written with 0 1 k 0 ...

Page 1863: ...Rising Edge Event Service Request State 0B No service is requested 1B Service is requested due to a rising edge detected on DCMk input signal line DCM00F DCM01F DCM02F DCM03F 1 4 7 10 rwh DCMk1 Falling Edge Event Service Request State 0B No service is requested 1B Service is requested due to a falling edge detected on DCMk input signal line DCM00C DCM01C DCM02C DCM03C 2 5 8 11 rwh DCMk1 Compare Ev...

Page 1864: ...A1_SRSC1 GPTA1 Service Request State Clear Register 1 018H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GTC 31 GTC 30 GTC 29 GTC 28 GTC 27 GTC 26 GTC 25 GTC 24 GTC 23 GTC 22 GTC 21 GTC 20 GTC 19 GTC 18 GTC 17 GTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTC 15 GTC 14 GTC 13 GTC 12 GTC 11 GTC 10 GTC 09 GTC 08 ...

Page 1865: ...TC 21 GTC 20 GTC 19 GTC 18 GTC 17 GTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTC 15 GTC 14 GTC 13 GTC 12 GTC 11 GTC 10 GTC 09 GTC 08 GTC 07 GTC 06 GTC 05 GTC 04 GTC 03 GTC 02 GTC 01 GTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description GTCk k 00 31 k rwh1 1 Writing a one to a cleared bit ...

Page 1866: ...C 19 LTC 18 LTC 17 LTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 15 LTC 14 LTC 13 LTC 12 LTC 11 LTC 10 LTC 09 LTC 08 LTC 07 LTC 06 LTC 05 LTC 04 LTC 03 LTC 02 LTC 01 LTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 00 31 k rwh LTCk Timer Capture Compare Service Request State ...

Page 1867: ... 19 LTC 18 LTC 17 LTC 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 15 LTC 14 LTC 13 LTC 12 LTC 11 LTC 10 LTC 09 LTC 08 LTC 07 LTC 06 LTC 05 LTC 04 LTC 03 LTC 02 LTC 01 LTC 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 00 31 k rwh LTCk Timer Capture Compare Service Request State 0...

Page 1868: ...51 LTC 50 LTC 49 LTC 48 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 47 LTC 46 LTC 45 LTC 44 LTC 43 LTC 42 LTC 41 LTC 40 LTC 39 LTC 38 LTC 37 LTC 36 LTC 35 LTC 34 LTC 33 LTC 32 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 32 63 k 32 rwh LTCk Timer Capture Compare Service Request State...

Page 1869: ...1 LTC 50 LTC 49 LTC 48 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTC 47 LTC 46 LTC 45 LTC 44 LTC 43 LTC 42 LTC 41 LTC 40 LTC 39 LTC 38 LTC 37 LTC 36 LTC 35 LTC 34 LTC 33 LTC 32 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description LTCk k 32 63 k 32 rwh LTCk Timer Capture Compare Service Request State ...

Page 1870: ...H GPTA1_SRNR GPTA1 Service Request Node Redirection Register 030H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTC 31R GTC 29R GTC 27R GTC 25R GTC 23R GTC 21R GTC 19R GTC 17R GTC 15R GTC 13R GTC 11R GTC 09R GTC 07R GTC 05R GTC 03R GTC 01R rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description GTC01R GTC03R GTC...

Page 1871: ...TC1796 Peripheral Units Vol 2 of 2 General Purpose Timer Array GPTA User s Manual 24 216 V2 0 2007 07 GPTA V2 0 0 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1872: ...mer Cells including an I O Line Sharing Unit that controls the LTC connections to the I O lines and output lines I O lines are supposed to be connected to I O port lines while the output lines are typically connected to a MSC interface that is especially able to control external power devices via a serial connection The LTCs can be further connected to input signals of an external clock bus and in...

Page 1873: ...e LTCA2 module provides a total of 40 input lines and 96 output lines that are connected to five I O groups IOG 4 0 and seven output groups OG 6 0 Figure 24 75 Input Output Line Sharing Unit Overview The LTCA2 I O Line Sharing Unit makes the following two selections LTC output multiplexer selection LTC input multiplexer selection To choose these selection the input and output lines of the related ...

Page 1874: ...A2 module inputs PDL 3 0 together with the inputs INT 3 0 The clock group is a logical group that combines the eight LTCA2 module clock inputs CLK 7 0 MCA05985 PDL0 PDL1 PDL2 PDL3 INT0 INT1 INT2 INT3 PDL INT Group INT2 INT3 INT0 INT1 PDL2 PDL3 PDL0 PDL1 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 Clock Group CLK6 CLK7 CLK4 CLK5 CLK2 CLK3 CLK0 CLK1 LTC24IN LTC25IN LTC26IN LTC27IN LTC28IN LTC29IN LTC30I...

Page 1875: ...TC 31 24 IN LTC 31 24 OUT LTCG4 LTC 39 32 LTC 39 32 IN LTC 39 32 OUT LTCG5 LTC 47 40 LTC 47 40 IN LTC 47 40 OUT LTCG6 LTC 55 48 LTC 55 48 IN LTC 55 48 OUT LTCG7 LTC 63 56 LTC 63 56 IN LTC 63 56 OUT I O Groups IOG0 IN 07 00 OUT 07 00 IOG1 IN 15 08 OUT 15 08 IOG2 IN 23 16 OUT 23 16 IOG3 IN 31 24 OUT 31 24 IOG4 IN 39 32 OUT 39 32 Output Groups OG0 OUT 63 56 OG1 OUT 71 64 OG2 OUT 79 72 OG3 OUT 87 80 O...

Page 1876: ...ut lines of the I O groups and output groups The LTCs are grouped into eight LTC groups LTCG 7 0 with 8 cells each In the same way I O groups and output groups are grouped into 12 groups five I O groups and seven output groups with 8 lines each Output Multiplexer LTC Groups MCA05986 I O Groups IOG0 IOG1 IOG2 IOG3 IOG4 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 ...

Page 1877: ...ior would occur On the other hand it is permitted that for the output of an LTC cell to be connected to more than one input of an I O or output group The output multiplexer group configuration is based on the following principles Each OMG is referenced with two index variables n and g OMGng Index n is a group number Local timer cell groups LTCG 3 0 have the group number 1 and Local Timer Cell Grou...

Page 1878: ... 2 level multiplexer is only connected only to the input of an I O group or output group if bit MRACTL MAEN multiplexer array enabled is set If MRACTL MAEN 0 the corresponding OMG output will be held at a low level Two Output Multiplexer Control Registers OMCRL and OMCRH see also Page 24 239 are assigned to each of the I O or output groups Therefore in total 24 registers control the connections wi...

Page 1879: ...RL2 GTCG2 LTCG2 LTCG6 IN 23 20 OUT 23 20 OMCRH2 IOG3 IN 27 24 OUT 27 24 OMCRL3 GTCG3 LTCG3 LTCG7 IN 31 28 OUT 31 28 OMCRH3 IOG4 IN 35 32 OUT 35 32 OMCRL4 GTCG0 LTCG0 LTCG4 IN 39 36 OUT 39 36 OMCRH4 OG0 OUT 59 56 1 1 OUT 55 40 is not available OMCRL7 GTCG3 LTCG3 LTCG7 OUT 63 60 OMCRH7 OG1 OUT 67 64 OMCRL8 GTCG0 LTCG0 LTCG4 OUT 71 68 OMCRH8 OG2 OUT 75 72 OMCRL9 GTCG1 LTCG1 LTCG5 OUT 79 76 OMCRH9 OG3...

Page 1880: ...T 3 0 with the 64 8 8 LTC inputs organized in eight LTC groups Figure 24 80 LTC Input Multiplexer of LTCA2 LTC Input Multiplexer I O Groups MCA05989 LTC Groups 8 IOG0 IOG1 IOG2 IOG3 LIMG 00 LIMG 02 LIMG 03 LIMG 10 LIMG 01 IOG4 PDL 3 0 INT 3 0 LTCG0 LTC 07 00 LTCG1 LTC 15 08 LTCG2 LTC 23 16 LTCG3 LTC 31 24 LTCG5 LTC 47 40 LTCG6 LTC 55 48 LTCG7 LTC 63 56 LTCG4 LTC 39 32 LIMG 04 LIMG 06 LIMG 07 LIMG ...

Page 1881: ...o LIMG input line IN0 The remaining lines cells or lines of a group are connected to LIMG input lines IN1 to IN7 with ascending index numbers At the clock group CLK0 is connected to IN0 and the remaining clock lines are connected to LIMG input lines IN1 to IN7 with ascending index numbers At the PDL INT group PDL 3 0 see Page 24 20 are connected to IN 3 0 and INT 3 0 are connected to IN 7 4 Exampl...

Page 1882: ...e PDL INT group has group number 4 Index g indicates the number of the LTC group g g 0 7 to which the outputs of the input multiplexer group LIMGng are connected The LTC input multiplexer logic as seen for programming is shown in Figure 24 82 With this logic four group signals from I O groups clock group or PDL INT group are always combined to one output line that leads to an LTC input of LTC grou...

Page 1883: ... within the LTC input multiplexer of the LTCA2 module The LIMCRL registers control the LIMG output lines 0 to 3 and the GIMCRH registers control the LIMG output lines 4 to 7 Table 24 20 lists all LTC Input Multiplexer Control Registers with its control functions Please note that all LTC Input Multiplexer Control Registers are not directly accessible but must be written or read using a FIFO array s...

Page 1884: ...gister contents one after the other 40 values into MRADIN starting with the register values for OMCRH13 OMCRL13 up to LIMCRH0 LIMCRL0 see Figure 24 83 After the first MRADIN write operation the contents for OMCRH13 is at FIFO position 1 With each following MRADIN write operation it becomes shifted one FIFO position upwards After the 40 MRADIN write operation the OMCRH13 value is at its final posit...

Page 1885: ... 0 When the array is disabled MRACTL MAEN 0 all cell inputs and outputs are disconnected from the GPIO lines and are driven with 0 Figure 24 83 LTCA2 Multiplexer Array Control Register FIFO Structure Multiplexer Register Array FIFO MCA05992 OMCRL13 39 40 31 OMCRH13 OMCRL0 17 18 OMCRH0 MRADOUT 0 Output Multiplexer Control Registers LIMCRL7 15 16 LIMCRH7 LIMCRL0 1 2 LIMCRH0 LTC Input Multiplexer Con...

Page 1886: ...ource has its own service request flag This flag is normally set by hardware but can be set and cleared by software Each service request status flag can be read twice at the same bit location in SRSCx register and in SRSSx register and cleared or set by software when writing to the corresponding request bit in SRSCx or SRSSx When writing to SRSCx or SRSSx several flags can be cleared at once by on...

Page 1887: ...e 2 Source 3 Source 4 00 LTC00 LTC01 LTC02 LTC03 01 LTC04 LTC05 LTC06 LTC07 02 LTC08 LTC09 LTC10 LTC11 03 LTC12 LTC13 LTC14 LTC15 04 LTC16 LTC17 LTC18 LTC19 05 LTC20 LTC21 LTC22 LTC23 06 LTC24 LTC25 LTC26 LTC27 07 LTC28 LTC29 LTC30 LTC31 08 LTC32 LTC33 LTC34 LTC35 09 LTC36 LTC37 LTC38 LTC39 10 LTC40 LTC41 LTC42 LTC43 11 LTC44 LTC45 LTC46 LTC47 12 LTC48 LTC49 LTC50 LTC51 13 LTC52 LTC53 LTC54 LTC55 ...

Page 1888: ...ge 24 211 SRSC2 Service Request State Clear Register 2 020H Page 24 211 SRSS2 Service Request State Set Register 2 024H Page 24 212 SRSC3 Service Request State Clear Register 3 028H Page 24 213 SRSS3 Service Request State Set Register 3 02CH Page 24 214 MRACTL Multiplexer Register Array Control Register 038H Page 24 236 MRADIN Multiplexer Register Array Data In Register 03CH Page 24 238 MRADOUT Mu...

Page 1889: ... Page 24 211 24 5 3 Local Timer Cell Registers See LTCCTRk k 00 62 on Page 24 180 LTCXRk Local Timer Cell X Register k k 00 62 200H k 8 4 Page 24 190 LTCCTR63 Local Timer Cell Control Register 63 3F8H Page 24 188 LTCXR63 Local Timer Cell X Register 63 3FCH Page 24 190 OMCRLg Output Multiplexer Control Register for Lower Half of Group g g 0 4 7 13 not directly addressable see Page 24 229 Page 24 23...

Page 1890: ...02A C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines the module identification number for ...

Page 1891: ... Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FIFOFILLCNT 0 FIFO FUL L WCR ES MA EN r r r r w rw Field Bits Type Description MAEN 0 rw Multiplexer Array Enable Bit field MAEN enables disables the programming and the interconnections of the multiplexer array 0B Multiplexer array is disabled all cell inputs are driven with 0 LTCA2...

Page 1892: ...pletely written write access to MRADIN allowed 1B FIFO completely written write access to MRADIN ignored Must be re enabled via WCRES before array can be re initialized FIFOFILLCNT 13 8 r FIFO Fill Count This bit field shows the current contents of the write cycle counter 0 7 3 31 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1893: ... bit accesses are ignored without any bus error MRADIN Multiplexer Register Array Data In Register 03CH Reset Value 0000 0000H 31 0 DATAIN w Field Bits Type Description DATAIN 31 0 w FIFO Write Data This register contains the FIFO write data as defined for the Output Multiplexer Control Registers and the LTC Input Multiplexer Control Registers MRADOUT Multiplexer Register Array Data Out Register 0...

Page 1894: ...H controls the connections of group pins 4 to 7 OMCRLg g 0 4 7 13 Output Multiplexer Control Register for Lower Half of Pin Group g Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 OMG3 0 OML3 0 OMG2 0 OML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OMG1 0 OML1 0 OMG0 0 OML0 r rw r rw r rw r rw Field Bits Type Description OML0 OML1 OML2 OML3 2 0 10 8 18 16 ...

Page 1895: ...ed to input n of I O Group g or Output group g 7 XX1B OMG1g selected XX0B OMG2g selected All other combinations are reserved If a reserved combination of OMGn value is selected the corresponding OMG output is forced to 0 level For compatibility reasons the values 001B for XX1B and 010B for XX0B should be used for OMGn bit field programming 0 3 7 11 15 19 23 27 31 r Reserved Read as 0 should be wri...

Page 1896: ...hat can be selected by bit field OMGn for OMG output n 000B OMG input IN0 selected 001B OMG input IN1 selected 010B OMG input IN2 selected 011B OMG input IN3 selected 100B OMG input IN4 selected 101B OMG input IN5 selected 110B OMG input IN6 selected 111B OMG input IN7 selected OMG4 OMG5 OMG6 OMG7 6 4 14 12 22 20 30 28 rw Multiplexer Group Selection This bit field determines the OMGng which is con...

Page 1897: ...Array GPTA User s Manual 24 242 V2 0 2007 07 GPTA V2 0 Note In the LTCA2 module registers OMCRL5 OMCRH5 OMCRL6 and OMCRH6 are not available see also Figure 24 83 0 3 7 11 15 19 23 27 31 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1898: ...0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LIM EN3 LIMG3 0 LIML3 LIM EN2 LIMG2 0 LIML2 r rw r rw r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIM EN1 LIMG1 0 LIML1 LIM EN0 LIMG0 0 LIML0 r rw r rw r rw r rw Field Bits Type Description LIML0 LIML1 LIML2 LIML3 2 0 10 8 18 16 26 24 rw Multiplexer Line Selection This bit field selects the input line of a LIMG that can be selected by bit f...

Page 1899: ... selected 001B LIMG1g selected 011B LIMG3g selected 100B LIMG4g selected All other combinations are reserved If a reserved combination of LIMGn is selected or if LIMENn 0 the corresponding LIMG output is forced to 0 level LIMEN0 LIMEN1 LIMEN2 LIMEN3 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by LIMLn and LIMGn 0 3...

Page 1900: ...n This bit field selects the input line of a LIMG that can be selected by bit field LIMGn for LIMG output n 000B LIMG input IN0 selected 001B LIMG input IN1 selected 010B LIMG input IN2 selected 011B LIMG input IN3 selected 100B LIMG input IN4 selected 101B LIMG input IN5 selected 110B LIMG input IN6 selected 111B LIMG input IN7 selected LIMG4 LIMG5 LIMG6 LIMG7 6 4 14 12 22 20 30 28 rw Multiplexer...

Page 1901: ...46 V2 0 2007 07 GPTA V2 0 LIMEN4 LIMEN5 LIMEN6 LIMEN7 7 15 23 31 rw Enable Multiplexer Connection 0B Input n is not connected to any line 1B Input n is connected to the line defined by LIMLn and LIMGn 0 3 11 19 27 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1902: ...nnections MultiCAN SCU and DMA connections SCU connections ADC DMA Module clock generation Interrupt registers GPTA address map Figure 24 86 shows the TC1796 specific implementation details and interconnections of the modules GPTA0 GPTA1 and LTCA2 The modules are supplied by clock control and address decoding logic Each GPTA0 1 module has 56 input signals and 112 output signals which can be connec...

Page 1903: ...rupt Control Clock Control Address Decoder fGPTA0 MCB05995 fCLC SCU Ext Request Unit P2 8 P2 15 P3 0 P3 15 P4 0 P4 15 P8 0 P8 7 P9 0 P9 7 MSC0 MSC1 FADC MultiCAN ADC0 ADC1 DMA IN 55 0 OUT 55 0 SR 37 00 IN 55 0 OUT 111 56 56 IN 39 0 OUT 39 0 OUT 111 56 SR 37 00 SR 15 00 GT0xRUN fGPTA1 GT1xRUN fLTCA2 OUT 111 56 INT 3 0 INT 3 0 INT 3 0 INT 3 1 INT0 OUT5 OUT 55 0 2 GPTA1 8 CLK 7 0 PLL Clocks SR15 2 2 ...

Page 1904: ...detail in the following sub sections Figure 24 87 GPTA Implementation Specific Special Function Registers 1 k 8 12 2 k 0 4 8 12 3 k 0 4 4 k 00 37 5 k 00 15 MCA05996 GPTA0_CLC Clock Control Registers GPTA0_FDR GPTA0_EDCTR GPTA0_DBGCTR P2_IOCRk Port Control Registers P3_IOCRk P4_IOCRk P8_IOCRk P9_IOCRk P2_PDR P3_PDR P4_PDR P8_PDR P9_PDR P2_ESR P3_ESR P4_ESR P8_ESR P9_ESR MSC Multiplexer Control Regi...

Page 1905: ...umber is assigned to the port line with the lowest index number The remaining lines are assigned linearly with increasing index numbers For example P3 5 is assigned to IN13 OUT13 In the LTCA2 only 40 input output lines are available Therefore the LTCA2 does not have IOG5 and IOG6 and therefore it has no connections to Port 8 or Port 9 pins Figure 24 88 I O Group to Port Assignment MCA05997 8 IOG0 ...

Page 1906: ...e input output control registers controls four port lines using a 4 bit wide bit field PCx definitions see Table 24 25 Table 24 24 shows which of the input output control register bit field is related to a specific GPTA0 GPTA1 LTCA2 module I O line Note that input P2 9 IN1 has special connections see Page 24 263 Table 24 24 IOCR Assignment for GPTA Port Lines Port Port Lines for GPTA GPTA I O Line...

Page 1907: ...ination of an OMGn value is selected Therefore no glitches and spikes can occur during the programming of the related multiplexer array Table 24 25 PCx Coding PCx 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function Comment 0X00B Input No pull device connected 0X01B Pull down device connected 0X10B 1 1 This bit field value is default after reset Pull up device connect...

Page 1908: ...TCA2 module I O line group PDx Selection Table Table 24 26 PDR Assignment for GPTA Port Lines Port Pad Class PDR Register PDx Bit Field Controlled Port Lines Related GPTA Output Lines Port 2 A1 P2_PDR PD1 P2 15 8 OUT 7 0 Port 3 A1 P3_PDR PD0 P3 7 0 OUT 15 8 P3_PDR PD1 P3 15 8 OUT 23 16 Port 4 A2 P4_PDR PD0 P4 7 0 OUT 31 24 A1 P4_PDR PD1 P4 15 8 OUT 39 32 Port 8 A1 P8_PDR PD0 P8 1 P8 4 P8 6 P8 7 OU...

Page 1909: ...t edge1 011B Weak driver 100B Medium driver Sharp edge 101B Medium edge 110B Soft edge 111B Weak driver 1 In strong driver mode the output driver characteristics of class A2 pads can be additionally controlled by the temperature compensation logic Table 24 27 Pad Driver Mode Mode Selection Class A1 A2 Pads cont d Pad Class PDx Bit Field Driver Strength Signal Transitions ...

Page 1910: ...System Units User s Manual The emergency stop signal always controls 8 bit groups of port lines The enable function is controlled for each pin by bits ENy y number of port line which are located in the Px_ESR x port number registers When the emergency stop signal generated in the SCU becomes active and bit Px_ESR ENy set output line Px y is set to the value of register Px_OUT Py emergency enabled ...

Page 1911: ... as shown in Figure 24 89 The GPTA0 clock bus drives Global Timers GTs Global Timer Cells GTCs and Local Timer Cells LTCs of the GPTA0 module only The GPTA1 clock bus drives its GTs GTCs and LTCs and the LTCs of the LTCA2 module Each GPTA0 and GPTA1 clock distribution unit has two pairs for PLL clock inputs an input pair for the local PLL clocks and an input pair for module external PLL clocks The...

Page 1912: ...INH MSC input buses can be selected via a multiplexer connected either to GPTA0 output x GPTA1 output x or LTCA2 output OUTx x 56 111 Figure 24 90 GPTA to MSC Multiplexer OG0 of GPTA0 MCA05999 MSC0 OG0 of GPTA1 OG0 of LTCA2 ALTINL 7 0 MUX ALTINL 15 8 MUX ALTINH 7 0 MUX ALTINH 15 8 MUX ALTINL 7 0 MUX ALTINL 15 8 MUX ALTINH 7 0 MUX MSC1 MMXCTR10 OUT 63 56 OUT 63 56 OUT 63 56 OG1 of GPTA0 OG1 of GPTA...

Page 1913: ... OUT88 OG4 0 ALTINL 1 OUT57 OG0 1 ALTINL 1 OUT89 OG4 1 ALTINL 2 OUT58 OG0 2 ALTINL 2 OUT90 OG4 2 ALTINL 3 OUT59 OG7 3 ALTINL 3 OUT91 OG4 3 ALTINL 4 OUT60 OG0 4 ALTINL 4 OUT92 OG4 4 ALTINL 5 OUT61 OG0 5 ALTINL 5 OUT93 OG4 5 ALTINL 6 OUT62 OG0 6 ALTINL 6 OUT94 OG4 6 ALTINL 7 OUT63 OG0 7 ALTINL 7 OUT95 OG4 7 ALTINL 8 OUT64 OG1 0 ALTINL 8 OUT96 OG5 0 ALTINL 9 OUT65 OG1 1 ALTINL 9 OUT97 OG5 1 ALTINL 10...

Page 1914: ...A2 to the MSC1 ALTINL 15 0 inputs GPTA0_MMXCTR11 controls the interconnections of GPTA0 GPTA1 and LTCA2 to the MSC1 ALTINH 7 0 inputs For each of the ALTINL ALTINH inputs of MSC0 and MSC1 the 2 bit bit fields in these registers determine which module GPTA0 GPTA1 or LTCA2 output is selected ALTINH 7 OUT79 OG2 7 ALTINH 7 OUT111 OG6 7 ALTINH 8 OUT80 OG3 0 ALTINH 9 OUT81 OG3 1 ALTINH 10 OUT82 OG3 2 AL...

Page 1915: ...connected to ALTINL n 01B GPTA1 output OUT 56 n selected and connected to ALTINL n 10B LTCA2 output OUT 56 n selected and connected to ALTINL n 11B Reserved GPTA0_MMXCTR01 GPTA to MSC Multiplexer Control Register 01 704H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MUX 15 MUX 14 MUX 13 MUX 12 MUX 11 MUX 10 MUX 9 MUX 8 MUX 7 MUX 6 MUX ...

Page 1916: ...1 Inputs ALTINL n 00B GPTA0 output OUT 88 n selected and connected to ALTINL n 01B GPTA1 output OUT 88 n selected and connected to ALTINL n 10B LTCA2 output OUT 88 n selected and connected to ALTINL n 11B Reserved GPTA0_MMXCTR11 GPTA to MSC Multiplexer Control Register 11 70CH Reset Value 0000 0000H 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MUX 7 MUX 6 MUX 5 MUX 4 MUX 3 MUX 2 MUX 1 MUX 0 r rw ...

Page 1917: ...TC1796 Peripheral Units Vol 2 of 2 General Purpose Timer Array GPTA User s Manual 24 262 V2 0 2007 07 GPTA V2 0 0 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1918: ...ections Figure 24 91 Connections of GPTA with On Chip Modules GPTA0 GPTA1 MCA06000_mod External Request Unit in SCU ROUT0 ROUT1 ROUT2 LTCA2 DMA IOUT0 Interrupt Node Interrupt Node ADC0 ADC1 MultiCAN SR15 ECTT3 Clock Generation FADC GIN1S P2 9 IN1 P5 0 RXD0A P6 8 RXD0B P6 10 RXD1B M U X IN1 SCU_CON OUT0 OUT8 OUT16 OUT17 OUT24 OUT25 OUT3 OUT11 OUT28 INT1 INT2 INT3 INT1 INT2 INT3 INT1 INT2 INT3 INT0 ...

Page 1919: ...output signals are connected to the GPTA0 GPTA1 LTCA2 internal inputs INT 3 1 These connections allow for example GTC or LTC events in the GPTA modules to be triggered by a request coming from a port pin or from the MSC clock FADC Connections As shown in Figure 24 91 eight GPTA0 output lines are connected as trigger input signals or gating input signals to the channel trigger logic of the FADC Thu...

Page 1920: ...24 268 responsible for the frequency control of the module timer clock fGPTA Clock Enable Disable Control Register GPTA0_EDCTR see Page 24 270 responsible for the enable disable control of the three module timer clocksfGPTA0 fGPTA1 and fLTCA2 and for the run control for the Global Timers in GPTA0 and GPTA1 Debug Clock Control Register GPTA0_DBGCTR see Page 24 271 responsible for the module timer c...

Page 1921: ..._FDR DM 01B The lower formula applies to fractional divider mode GPTA0_FDR DM 10B The debug clock control register additionally makes it possible to control the timer clocks fGPTA0 fGPTA1 and fLTCA2 for debug purposes on basis of a clock counter If the debug clock feature is enabled GPTA0_DBGCTR DBGCEN 1 and bit GPTA0_DBGCTR DBGCST is set the timer clocks fGPTA0 fGPTA1 and fLTCA2 will be activated...

Page 1922: ...H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the current status of the module SPEN 2 rw Module Suspend Enable for ...

Page 1923: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS CLK EN HW SUS REQ SUS ACK 0 RESULT rwh rw rh rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines the behavior...

Page 1924: ...onality are described in section Fractional Divider Operation on Page 3 29 of the TC1796 User s Manual System Units part Volume 1 ENHW 30 rw Enable Hardware Clock Control Controls operation of ECEN input and DISCLK bit DISCLK 31 rwh Disable Clock Hardware controlled disable for fOUT signal 0 10 27 26 rw Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 1925: ...rw rw rw rw Field Bits Type Description GT00RUN 0 rw GPTA0 Global Timer 0 Run Control 0B GPTA0 Global Timer 0 clock is stopped 1B GPTA0 Global Timer 0 clock is started running GT01RUN 1 rw GPTA0 Global Timer 1 Run Control 0B GPTA0 Global Timer 1 clock is stopped 1B GPTA0 Global Timer 1 clock is started running GT10RUN 2 rw GPTA1 Global Timer 0 Run Control 0B GPTA1 Global Timer 0 clock is stopped 1...

Page 1926: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG CEN 0 rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCNT rwh Field Bits Type Description CLKCNT 15 0 rwh Debug Clock Count This bit field determines the number of clock pulses to be issued when the debug clock feature is enabled DBGCEN 1 CLKCNT counts down to 0000H and stops when the debug clock feature is enabled DBGCEN 31 rw Debug Clock Enable 0...

Page 1927: ... MHz a maximum of 20 GTCs and 20 LTCs can be connected together If the module timer clock fGPTA is reduced the number of LTCs that can be cascaded increases accordingly Only the integer part of the divider ratio as selected by the GPTA0_FDR fractional divider register determines the maximum number of cascaded GTCs and LTCs Table 24 31 Limits of Cascading GTCs and LTCs fSYS Selected Clock Divider R...

Page 1928: ...rrupt Service Request Control Register k 7FCH k 4H Reset Value 0000 0000H GPTA1_SRCk k 00 37 GPTA1 Interrupt Service Request Control Register k 7FCH k 4H Reset Value 0000 0000H LTCA2_SRCk k 00 15 LTCA2 Interrupt Service Request Control Register k 7FCH k 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SR...

Page 1929: ...2 0 Note Additional details on service request nodes and the service request control registers are described on Page 14 3 of the TC1796 User s Manual System Units part Volume 1 24 6 8 GPTA Register Address Map The GPTA0 and GPTA1 register map shown in Figure 24 93 The LTCA2 register map shown in Figure 24 94 ...

Page 1930: ...rs are not available in GPTA1 700H 7BAH 400H General Module Control Input Output Line Sharing Unit Interrupt Control Global Timer Reserved Clock Generation Unit Local Timer Cells Interrupt Service Request Control Registers Global Timer Cells Reserved GPTA to MSC Multiplexer Control General Module Control MRADOUT MRADIN MRACTL GTCTRk GTREVk GTTIMk GTCXRk GTCCTRk LTCXRk LTCCTRk SRCk EDCTR DBGCTR FDR...

Page 1931: ...A V2 0 Figure 24 94 LTCA2 Register Map Reserved Reserved MCA06003 020H 000H k 00 63 038H 044H 200H 7FFH 7C0H Reserved MRADOUT MRADIN MRACTL LTCXRk LTCCTRk SRCk SRNRn SRSSn SRSCn k 00 15 n 2 3 3FFH Local Timer Cells Interrupt Service Request Control Registers Input Output Line Sharing Unit Interrupt Control ...

Page 1932: ...entation specific details and registers of the ADC0 ADC1 modules including port connections and control service request control address decoding and clock control see Page 25 100 Note The ADC Kernel register names described in Section 25 2 are referenced in the TC1796 User s Manual with the module name prefix ADC0_ for the ADC0 interface and ADC1_ for the ADC1 interface 25 1 ADC Kernel Description...

Page 1933: ...DC1 has 16 analog input channels An analog multiplexer selects the input line for the analog input channels from among 32 analog inputs Additionally an external analog multiplexer can be used for analog input extension External Clock control address decoding and service request interrupt control are managed outside the ADC module kernel A synchronization bridge is used for synchronization of two A...

Page 1934: ...rigger control TTR TGT Figure 25 2 provides a more detailed block diagram of the ADC kernel with its main functional units Figure 25 2 Functional Units of the ADC Kernel MCA06005 AIN0 AIN31 AIN15 AIN16 EMUX0 EMUX1 MUX MUX VAGND A D Converter 8 10 12 Bit Synchroni zation Control External Multiplexer Control Control Unit Synchronization Bridge Status Unit Interrupt Control SR 7 0 Trigger and Gating ...

Page 1935: ...plexer Configuration Each ADC channel n n 0 15 can be connected to two analog inputs AIN n and AIN n 16 The selection is made for ADC channel n by the channel control register group select bit CHCONn GRPS With CHCONn GRPS 0 an analog input of analog input group 0 is selected With CHCONn GRPS 1 an analog input of analog input group 1 is selected MCA06006 AIN0 AIN1 AIN14 AIN15 AIN16 AIN17 AIN30 AIN3...

Page 1936: ...an arbitration participation flag and the source arbitration level Each parallel conversion control register contains 16 bits defining whether a conversion request is activated for a specific channel The contents of the parallel conversion control register are loaded into the conversion request pending register on request source specific trigger events If at least one bit is set in the conversion ...

Page 1937: ... bit causes the arbitration participation flag to be set This informs the arbiter to include the sequential conversion request source into arbitration If this sequential source is the arbitration winner a conversion is started for the analog channel specified within the request register The settings of the external multiplexer and the resolution of the ADC are also derived from this conversion req...

Page 1938: ...rmed after the request in the back up register has been served The request bit in the control register and in the back up register can be cancelled under software control Clearing the arbitration participation bit clears either the request bit in the request register if the back up register contains no request or the request bit in the back up register if the back up register contains a valid requ...

Page 1939: ... run bit TCON TR becomes set the timer bit field TSTAT TIMER is loaded with the timer reload value TCON TRLD With each clock cycle of fTIMER the timer register is decremented and compared to the arbitration lock boundary value TCON ALB If the value of the timer register is equal to the value of the arbitration lock boundary the arbitration lock bit STAT AL is set see Section 25 6 This arbitration ...

Page 1940: ...This triggers conversion requests for the selected channel s if the gating input line TGT 1 When the timer gating line TGT 0 the pending conversion requests do not take part in the arbitration cycle The timer can also be started by a pulse on the timer trigger input line TTR The TTR and TGT input connections depend on the product specific implementation of the ADC module They are described on Page...

Page 1941: ...learing the timer arbitration participation flag AP TP The arbitration lock mechanism provides the means to start timer triggered conversion requests without being delayed by a currently running conversion Figure 25 6 shows this method in detail Figure 25 6 Arbitration Lock Mechanism The arbitration must be locked before the timer is 0 in order to ensure that the running conversion has been finish...

Page 1942: ...K for which the arbitration is locked Running in Arbitration Lock Mode the current value of the timer register is compared to the arbitration lock boundary Note that the arbitration will always be locked if the reload value is selected to be equal to or less than the arbitration lock boundary On a compare match the arbitration logic is locked STAT AL 1 while timer 0 removes the arbitration lock Bi...

Page 1943: ...quests do not take part in the arbitration cycle If an external event is detected input ETR 1 the contents of the external trigger control register EXTC are loaded into the external conversion request pending register Load means that the contents of EXTC and the contents of external conversion request pending register EXCRP are bit wise OR ed as shown in Figure 25 7 The ETR and EGT input connectio...

Page 1944: ...ated conversion is cancelled the arbiter sets the corresponding conversion request bit in register EXCRP for this channel If all pending conversion requests are processed the arbitration participation flag AP EXP is cleared The contents of register EXCRP can be reset globally under software control by clearing the External Event arbitration participation flag Note that conversion requests caused b...

Page 1945: ...This informs the arbiter to include the conversion request source Software in the arbitration If Software is the arbitration winner a conversion is started for the conversion request within register SW0CRP with the highest channel number Starting a conversion causes the conversion request bit in register SW0CRP to be cleared by the arbiter If a currently running Software initiated conversion is ca...

Page 1946: ...nnel request flags SRQn in the auto scan conversion request register SCN The auto scan sequence is started by programming an auto scan mode in the A D Converter control register bit field CON SCNM Selecting an auto scan mode loads the contents of the auto scan conversion request register SCN into the auto scan conversion request pending register ASCRP If at least one bit is set in the auto scan co...

Page 1947: ...s will be overwritten Continuous auto scan sequence is performed until auto scan is stopped under software control If a currently running Auto scan initiated conversion is cancelled the arbiter sets the corresponding conversion request bit in register ASCRP for this channel After the conversion of the last channel within an auto scan sequence has been finished the source service request flag MSS1 ...

Page 1948: ...ister ASCRP set bit AP ASP and start continuous auto scan sequence if at least one channel is specified in register SCN to participate in auto scan mode otherwise clear bit field CON SCNM 11B Clear bit field CON SCNM 01B 00B Finish currently performed auto scan sequence and generate a service request if enabled at the end of the sequence 01B Continue to perform auto scan sequence and generate a se...

Page 1949: ...of the sequence Load SCN contents into register ASCRP and start single auto scan sequence 10B Continue to perform continuous auto scan sequence and generate a service request if enabled at the end of the sequence Load SCN contents into register ASCRP and start continuous auto scan sequence 11B Clear bit field CON SCNM and finish auto scan sequence Generate a service request if enabled at the end o...

Page 1950: ...scan mode Finish currently performed auto scan sequence and generate a service request if enabled if this was the last channel of the sequence No new auto scan sequence is started 0 In case of CON SCNM 00B 01B or 11B Clear bit field CON SCNM Finish currently performed auto scan sequence and generate a service request if enabled if this was the last channel of the sequence No new auto scan sequence...

Page 1951: ...ue of ASP Write to ASP Action 0 0 No action 1 No action 1 0 In case of bit field CON SCNM 00B 01B or 11B Bit field SCNM is cleared Finish currently performed auto scan conversion Generate a service request if enabled if this was the last channel of auto scan sequence In case of bit field CON SCNM 10B Finish currently performed auto scan conversion and generate a service request if enabled if this ...

Page 1952: ...INREQ causes the arbitration participation flag AP CHP to be set This informs the arbiter to include the conversion request source Channel Injection into arbitration If Channel Injection is the arbitration winner a conversion is started for the analog channel specified in the channel injection control register CHIN The settings of the external multiplexer and the resolution of the ADC are also tak...

Page 1953: ...nnel Injection with Inject Wait provides the means to wait until the current conversion with higher priority is finished before the requested conversion is injected Channel Injection with Cancel Inject Repeat Cancels a currently performed conversion Injects the requested conversion and finally Repeats the previously cancelled conversion The Cancel Inject Repeat feature is enabled if bit CHIN CIREN...

Page 1954: ...on in order to restart this cancelled conversion later This new request participates in arbitration and will be selected for repetition due to its priority level The second injection request with a source arbitration level of L4 is delayed even if the Cancel Inject Repeat feature is enabled Figure 25 12 Channel Injection with Cancel Inject Repeat Feature Src n Level L1 CHIN L3 MCT06014 CHIN L3 Con...

Page 1955: ... timer Second a conversion is requested by Channel Injection with a source arbitration level of L1 with the Cancel Inject Repeat feature selected during which the arbitration is locked by the timer In this case the arbitration lock is not taken into account because the timer was programmed on source arbitration level L2 Even a currently running timer triggered conversion would have been cancelled ...

Page 1956: ...queue control logic includes the queue load logic a queue level pointer a queue warning limit pointer the queue based service request control block as well as control and status flags to monitor and control the queue state The queue register the queue status register and each of the sixteen queue elements contain a valid bit V an analog input group selection bit GRPS external multiplexer control b...

Page 1957: ...of the queue warning limit pointer must be programmed with a value n in order to focus on a state change from valid to invalid of queue element n A queue based service request can be triggered in this case thus requesting the next transfer of data to the queue If the queue element specified by CON QWLP 1 becomes invalid after a conversion the module service request flag MSS1 MSRQR is automatically...

Page 1958: ...he settings of the A D Converter s resolution If the back up register contains valid conversion information the arbiter reads from the back up register instead of the queue status register Thus the previously cancelled conversion participates in arbitration once again A conversion requested via the queue storage block register QUEUE0 will be performed after the request in the back up register is s...

Page 1959: ... conversion The enable bit CON QEN can be set by hardware if the queue trigger request line QTR 1 The QTR and QGT input connections depend on the product specific implementation of the ADC module They are described in Section 25 3 6 2 Figure 25 16 Modification of Bit CON QEN MCA06019_mod Set Queue Trigger Request QTR CON QEN Set Write 1 to SCON QENS Write 1 to SCON QENC Clear ...

Page 1960: ...hm Source arbitration is the first stage in the arbitration algorithm Starting with the conversion request source Auto Scan up to Channel Injection each source is checked if its arbitration participation flag is set If the participation flag is set and its priority is higher than the priority of the other selected sources that source is the winner of the arbitration MCA06020 Channel Injection CHIN...

Page 1961: ...esponding bit fields of the source arbitration level register SAL The priority of a source is named as source arbitration level and it determines the order in which pending conversion requests from different sources are performed A low number of the source arbitration level represents a high priority and vice versa After initialization an individual source arbitration level is assigned to each sou...

Page 1962: ...n request pending register If a conversion initiated by a sequential source is cancelled the control information such as resolution external multiplexer information etc of the cancelled conversion is rescued into the backup register for example queue based conversion is cancelled so the queue backup register receives the control information of the cancelled conversion Afterwards the request partic...

Page 1963: ... boundary the arbitration lock bit STAT AL is set Setting the arbitration lock bit also sets the timer participation flag In this way the timer source can participate in the arbitration cycle without any pending request Such an arbitration participation by the timer without a pending request denies all currently pending sources that have a source arbitration level below the timer source as arbitra...

Page 1964: ...sive approximation and the calibration time Table 25 6 shows the conversion time tC based on the sample time tS basic operating clock frequency fBC and the module timing clock fADC tBC 1 fBC tADC 1 fADC Note The TC1796 basic operating clock frequency fBC influences the maximum allowable internal resistance of the used reference voltage supply Table 25 6 Conversion Time tC A D Converter Resolution ...

Page 1965: ...The conversion and calibration phase is indicated by the busy signal STAT BUSY which goes inactive at the end of the calibration phase Note During the power up calibration no conversion should be started 25 1 4 2 Conversion Timing Control CTC and CPS The module clock fADC is generated in the ADC Clock Generation unit see Page 25 103 The A D Converter s basic operating clock frequency fBC is derive...

Page 1966: ...d the programmable value of bit field CHCONn STC The sample time tS is selected in periods of tBC 1 fBC within the range from 8 tBC up to 1028 tBC The sample time tS is calculated according to the following equation tS 4 STC 2 tBC 25 4 Table 25 8 shows the selectable values of CON STC and the resulting ADC basic operating clock fBC and sample time tS Note The duration of the sample phase influence...

Page 1967: ...nd becomes enabled when registers ADC0_CLC and ADC0_FDR are written with appropriate values Power up calibration starts when the analog part of the A D Converter is clocked after a reset operation The following example shows the setup for the fastest achievable best case power up calibration time at fSYS 75 MHz Note that the maximum frequency of fANA must not exceed 10 MHz See also Page 25 103 for...

Page 1968: ...he following specifications VAREF 3 0 VDDM 0 05 V VDDM 3 3 V 25 6 A conversion with low reference voltage affects the accuracy of the A D Converter The TUE of an A D Converter that is operated at a reduced positive reference voltage can be evaluated according to the following equations TUE A TUE B K TUE A K 1 25 7 with factor K as VAREF A VAREF B 1 K VAREF A 25 8 where VAREF A minimum positive ref...

Page 1969: ...el D by an additional error AEL based on the additional sampled voltage VAEL Analog Error Leakage VAEL D 1 RAIN D IOV D kA 25 9 The coupling factor kA determines the physical relation of two adjacent analog inputs The resulting error AEL is given by 25 10 where VAREF reference voltage for conversion RAIN D resistance of the analog input channel D IOV D overload current of the analog input D AEL ad...

Page 1970: ...conversion result meets the specified range Two out of four boundaries can be selected and programmed per limit check The boundaries are selected for each analog channel via the bit fields CHCONn BSELA and CHCONn BSELB n 0 15 Four boundaries can be set individually in the limit check control register LCCON0 1 2 3 The limit check control bit field specifies if a limit check is performed for the cur...

Page 1971: ...undary B selected by CHCONn BSELB is fixed in its assignment as a lower or upper one The boundary s value specifies whether it is assumed to be the upper or lower one In this example channel number 5 is configured for limit checking CHCON5 BSELA is set to 10B and selects the boundary stored in LCCON2 BOUNDARY CHCON5 BSELB is configured to 01B and selects the boundary stored in LCCON1 BOUNDARY Sinc...

Page 1972: ...l input pins Note The characteristics of the external multiplexers influence the accuracy of the A D Converters An accuracy of 2 LSB 10 bit resolution is no longer guaranteed Two control lines are provided to drive external multiplexers as shown in Figure 25 21 Figure 25 21 External Expansion of Analog Channels External analog multiplexers receive the select information CHCONn EMUX 1 0 and optiona...

Page 1973: ... add an RC filter before the external multiplexer to each additional external analog inputs For example each of the external analog inputs AN 0 to AN 3 in Figure 25 21 is adapted by an RC filter In this case the resistance of the external multiplexer reduces the efficiency of the external capacitors of the RC filter An additional blocking capacitor between the external multiplexer and the analog i...

Page 1974: ...the implementation of the A D Converter Module in a specific microcontroller the service request output signals SR 7 0 can be connected either to an interrupt node service request control register or can be used as DMA request input of a DMA controller unit The TC1796 specific service request output configuration is described in Figure 25 30 and on Page 25 119 The control logic for each of the ser...

Page 1975: ... status flags bits Table 25 9 Service Request Control Status Bits Flags Service Request Source Source Selection Status Flag Enable Bit Service Request Node Pointer Channel n1 1 n 0 15 CHCONn LCC 1 MSS0 MSRCHn 1 CHCONn ENCH 1 CHCONn INP 1 Timer MSS1 MSRT SRNP ENPT SRNP PT Queue MSS1 MSRQR SRNP ENPQR SRNP PQR Auto scan MSS1 MSRAS SRNP ENPAS SRNP PAS Synchronous Channel Injection MSS1 MSRSY SRNP ENPS...

Page 1976: ... n request status flag MSS0 MSRCHn is set and the channel n service request event is reported to the service request compressor logic if enabled by CHCONn ENCH The service request flag MSS0 MSRCHn can only be cleared by software For test purposes CON SRTEST 1 the service request flag can be additionally set by hardware Additional details on MSS0 MSRCHn software control are described on Page 25 48 ...

Page 1977: ...parallel serial service request event As defined in Table 25 9 each of the four serial parallel request source Timer Queue Auto Scan Synchronized Injection has its own request status flag and request enable bit The service request flags that are located in register MSS1 can also be set or cleared by software Figure 25 24 Parallel Serial Request Source Logic MCA06027_mod Flag MSS1 Set Service Reque...

Page 1978: ... pointer This node pointer assigns a request event to one of the service request outputs Channel n request events are controlled by a node pointer that is located in each channel n control register CHCONn INP The node pointers for the four parallel serial request events are located in register SRPN see Table 25 9 The open inputs of the OR gates are connected to the remaining 18 service request eve...

Page 1979: ...g is set when CON SRTEST 1 is set and a 1 is written to the corresponding bit position in the MSS0 MSS1 register After this MSS0 MSS1 write action is executed bit CON SRTEST becomes automatically cleared again Table 25 10 summarizes the actions that are performed when a write action on a MSS0 MSS1 register service request status flag occurs Table 25 10 Service Request Status Flag Set Clear Operati...

Page 1980: ...as master Because the master transfers all control information necessary for the synchronized conversion in the slave the channel number the A D Converter resolution the external multiplexer information and the cancel synchronize repeat information are identical in both modules The timing information as well as the service request generation can be different in the two modules for instance a synch...

Page 1981: ...gured for Synchronized Injection Mode with sync wait feature selected then each time this channel is triggered and wins the arbitration a synchronized conversion is requested Thus ADC module 0 is assumed to be the master and the control information needed for a synchronized conversion is transferred to ADC Module 1 the slave Note A Channel Injection request with an active cancel inject repeat feat...

Page 1982: ...ve ADC module during a synchronized conversion It is set at the start of the synchronized conversion and is cleared after this synchronized conversion is finished Master Slave Status Bit STAT SYMS is set in both ADC modules to indicate that both ADC modules requested a synchronized conversion at the same time with identical channel number Bit STAT SYMS is automatically cleared at the generation of...

Page 1983: ...nished its synchronized conversion STAT IENPAR Status bit is driven by slave to indicate that the slave finished its synchronized conversion Slave SYSTAT SYREQ Status bit is driven by master to request the slave for a synchronized conversion SYSTAT CHNRSY Status bit field is driven by master to indicate the channel to be converted for a synchronized conversion SYSTAT RES Status bit field is driven...

Page 1984: ... setting bit MSS1 MSRSY both bits STAT IENREQ and STAT IENPAR are automatically cleared Slave Functionality On reception of the synchronized request bit SYSTAT SYREQ is set the channel number SYSTAT CHNRSY the resolution SYSTAT RES the external multiplexer information SYSTAT EMUX the analog input multiplexer group select state SYSTAT GRPS as well as the cancel sync repeat information SYSTAT CSREN ...

Page 1985: ...is disabled This means that the synchronized conversion is started next in the slave From this point the behavior is similar to the one of a master until the synchronized conversion is finished At the end of the synchronized conversion bit STAT SYMS is cleared and bit MSS1 MSRSY is set for each ADC module 25 1 10 4 Conversion Timing during Synchronized Conversion The settings for the conversion an...

Page 1986: ... with sync wait functionality CHCON5 SYM 01B Thus a synchronized request is transferred to the slave causing the slave s bit SYSTAT SYREQ to be set This immediately locks the slaves s arbiter until the synchronized conversion is started Any pending conversion requests in the slave in this case the request by source i are served after the synchronized conversion is finished Figure 25 27 Synchronize...

Page 1987: ...running synchronized conversion is finished In this example channel 5 is the arbitration winner Its CHCON5 SYM bit field is configured for Synchronized Injection with cancel sync repeat functionality CHCON5 SYM 10B Thus a synchronized request is transferred to the slave and the currently performed conversion is immediately cancelled Figure 25 28 Synchronized Conversions with Cancel Sync Repeat Fun...

Page 1988: ...on Page 18 87 of the TC1796 User s Manual System Units part Volume 1 Note For documentation automation purposes the CHCON and CHSTAT registers use index m while LCCON registers use index x in the ADC module kernel register description These indexes are represented by n for CHCON and CHSTAT registers and m for LCCON register in other sections of the chapter Table 25 12 Registers Address Space ADC K...

Page 1989: ...100H m 4H Page 25 80 TCON Timer Control Register 114H Page 25 66 CHIN Channel Injection Control Register 118H Page 25 90 QR Queue Register 11CH Page 25 71 CON Converter Control Register 120H Page 25 82 SCN Auto Scan Control Register 124H Page 25 75 REQ0 Conversion Request Register SW0 128H Page 25 92 CHSTATm Channel Status Register m m 0 15 130H n 4H Page 25 63 QUEUE0 Queue Status Register 170H Pa...

Page 1990: ...ication Register 008H Reset Value 0030 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field defines th...

Page 1991: ...8 rw Analog Reference Voltage Control This bit determines the reference voltage for channel n 00B VAREF 0 is selected as reference voltage 01B VAREF 1 is selected as reference voltage 10B VAREF 2 is selected as reference voltage 11B VAREF 3 is selected as reference voltage See Page 25 113 for TC1796 specific implementation RES 11 10 rw Conversion Resolution Control RES determines the resolution of...

Page 1992: ... 01B LCCON1 BOUNDARY1 is selected 10B LCCON2 BOUNDARY2 is selected 11B LCCON3 BOUNDARY3 is selected LCC 22 20 rw Limit Check Control 000B Neither limit check is performed nor a service request is generated on write of the conversion result to bit field STAT RESULT 001B Generate a service request if conversion result is in not area I 010B Generate a service request if conversion result is not in ar...

Page 1993: ...e SR1 selected 010B Service request line SR2 selected 011B Service request line SR3 selected 100B Service request line SR4 selected 101B Service request line SR5 selected 110B Service request line SR6 selected 111B Service request line SR7 selected SYM 29 28 rw Synchronized Injection Mode This bit field determines whether channel n can trigger a synchronized conversion as master If enabled a synch...

Page 1994: ... last conversion of channel n 8 bit Conversion result is stored in RESULT 11 4 10 bit Conversion result is stored in RESULT 11 2 12 bit Conversion result is stored in RESULT 11 0 Unused bits of RESULT are 0 EMUX 17 16 rh Status of External Multiplexer This bit field indicates the setting of the external multiplexer control of DMA channel n This information is either derived from CHCONn EMUX parall...

Page 1995: ... 22 20 rh Conversion Request Source This bit field indicates for channel n the origin of the conversion result stored in bit field RESULT 000B Channel injection 001B Timer 010B Synchronized injection 011B External event 100B Software SW0 101B Reserved 110B Queue 111B Auto Scan CHNR 27 24 rh Channel Number This bit field holds the channel number n 0 15 12 19 23 31 28 r Reserved Read as 0 Field Bits...

Page 1996: ...H 13 TTC CH 12 TTC CH 11 TTC CH 10 TTC CH 9 TTC CH 8 TTC CH 7 TTC CH 6 TTC CH 5 TTC CH 4 TTC CH 3 TTC CH 2 TTC CH 1 TTC CH 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description TTCCHn n 0 15 n rw Timer Trigger Control for Channel n TTCCHn determines whether a conversion request is triggered for channel n on timer underflow or not 0B No conversion request is triggered for ch...

Page 1997: ...greater than zero is written to ALB Note The arbitration is locked if the value of ALB is above TRLD TRLD 29 16 rw Timer Reload Value TRLD is loaded into the timer register TSTAT TIMER when TSTAT TIMER 0 or each time when SCON TRS is set Note If TRLD is zero timer lock is always active and a service request can be generated for each timer clock TSEN 30 rw Timer Stop Enable 0B TSTAT TIMER 0 has no ...

Page 1998: ... be written with 0 TSTAT Timer Status Register 1B0H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TIMER r rh Field Bits Type Description TIMER 13 0 rh Timer Register This bit field contains the current value of the timer 0 31 14 r Reserved Read as 0 Field Bits Type Description ...

Page 1999: ... rh rh rh rh rh rh rh Field Bits Type Description TRPn n 0 15 n rh Timer Conversion Request Pending Flag for Channel n A pending flag TRPn is set each time a conversion request is generated for channel n on timer underflow that could not be serviced immediately A start of conversion of the pending request leads automatically to a cleared of the pending flag All pending request flags can also be cl...

Page 2000: ...s the resolution of the A D Converter for the conversion of the analog channel determined by CHNR Any modification of this bit field is taken into account after the currently running conversion is finished 00B 10 bit resolution 01B 12 bit resolution 10B 8 bit resolution 11B Reserved EMUX 9 8 rh External Multiplexer Control Line Status This bit field indicates the external multiplexer control line ...

Page 2001: ...7 07 ADC V2 0 V 15 rh Valid Status This bit field indicates whether the information of register QR is valid or invalid 0B CHNR RES EMUX and GRPS are invalid 1B CHNR RES EMUX and GRPS are valid a queue conversion request is pending 0 5 4 14 11 31 16 r Reserved Read as 0 Field Bits Type Description ...

Page 2002: ...n of the analog channel as programmed for CHNR Any modification of this bit field is taken into account after the currently running conversion is finished 00B 10 bit resolution 01B 12 bit resolution 10B 8 bit resolution 11B Reserved EMUX 9 8 rw External Multiplexer Control This bit field determines the settings of the external multiplexer control lines for the conversion of the analog channel as p...

Page 2003: ...ntrol This bit indicates whether the information of register QR is valid or invalid Bit V is cleared by hardware when the QR contents are transferred to the queue 0B CHNR RES EMUX and GRPS are invalid 1B CHNR RES EMUX and GRPS are valid 0 5 4 14 11 31 16 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2004: ...ETC CH 12 ETC CH 11 ETC CH 10 ETC CH 9 ETC CH 8 ETC CH 7 ETC CH 6 ETC CH 5 ETC CH 4 ETC CH 3 ETC CH 2 ETC CH 1 ETC CH 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description ETCHn n 0 15 n rw External Trigger Control for Channel n ETCHn specifies if a conversion request is triggered on an event on the selected input line including gating for channel n 0B No conversion request...

Page 2005: ...rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description EXCRPn n 0 15 n rh External Event Conversion Request Pending Flag for Channel n EXCRPn is set each time a conversion request is generated for channel n by an external event that could not be serviced immediately A start of conversion of the pending request leads automatically to a clear of the pending flag All pending request flags...

Page 2006: ... SRQ 14 SRQ 13 SRQ 12 SRQ 11 SRQ 10 SRQ 9 SRQ 8 SRQ 7 SRQ 6 SRQ 5 SRQ 4 SRQ 3 SRQ 2 SRQ 1 SRQ 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description SRQn n 0 15 n rw Auto Scan Request for Channel n SRQn determines whether or not channel n participates in an auto scan sequence 0B Channel n does not participate in an auto scan sequence 1B Channel n participates in an auto scan...

Page 2007: ...0 01B Bit ASCRP GRPS is set to 0 and it is taken into account for all conversions triggered by auto scan only group 0 is covered by the auto scan 10B Bit ASCRP GRPS is set to 1 and it is taken into account for all conversions triggered by auto scan only group 1 is covered by the auto scan 11B Bit ASCRP GRPS is toggled at the end of each auto scan sequence It is taken into account for all conversio...

Page 2008: ...g flag ASCRPn is set each time a conversion request is generated for channel n by auto scan that could not be serviced immediately A start of conversion of the pending request leads automatically to a clear of the pending flag All pending request flags can also be cleared under software control if bit AP ASP is cleared 0B No auto scan based conversion request is pending for channel n 1B An auto sc...

Page 2009: ...rwh Queue Arbitration Participation 0B Source does not participate in arbitration 1B Source participates in arbitration SW0P 3 rwh Software SW0 Arbitration Participation Flag 0B Source does not participate in arbitration 1B Source participates in arbitration EXP 4 rwh External Event Arbitration Participation Flag 0B Source does not participate in arbitration 1B Source participates in arbitration T...

Page 2010: ...evel 000B Highest priority for arbitration selected 111B Lowest priority for arbitration selected SALSW0 14 12 rw Software Source Arbitration Level 000B Highest priority for arbitration selected 111B Lowest priority for arbitration selected SALEXT 18 16 rw External Event Source Arbitration Level 000B Highest priority for arbitration selected 111B Lowest priority for arbitration selected SALT 26 24...

Page 2011: ...8 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BOUNDARY r rw Field Bits Type Description BOUNDARY 11 0 rw Boundary for Limit Checks This bit field contains the boundary value used for limit checking The relevant bits of this bit field for the different resolutions are 8 bit BOUNDARY 11 4 10 bit BOUNDARY 11 2 12 bit BOUNDARY 11 0 Unused bits should be written with 0 0 31 12 r Reserved Read as ...

Page 2012: ...escription QENC 0 w Queue Enable Clear Writing a 1 to this bit clears bit CON QEN also if QENS has been set simultaneously QENS 1 w Queue Enable Set Writing a 1 to this bit and a 0 to QENC sets bit CON QEN TRC 2 w Timer Run Bit Clear Writing a 1 to this bit clears bit TCON TR also if TRS has been set simultaneously TRS 3 w Timer Run Bit Set Writing a 1 to this bit and a 0 to TRC sets bit TCON TR Q...

Page 2013: ...ny modification of this bit field is taken into account after the currently performed conversion is finished SCNM 9 8 rw Auto Scan Mode This bit enables the auto scan mode 00B Auto scan mode disabled 01B Auto scan single sequence mode enabled 10B Auto scan continuous sequence mode enabled 11B Reserved QEN 15 rh Queue Enable This bit specifies if queue controlled conversions are enabled disabled an...

Page 2014: ...ts in Parallel Sources by Arbiter Bit CPR determines whether or not all pending conversion requests for an A D channel indicated by STAT CHNRCC are cancelled by the arbiter when the conversion for this channel has been started 0B The individual clear by arbiter is enabled Only the conversion request of channel n of the winning source is cleared when a conversion of channel n is started 1B The glob...

Page 2015: ...ronized mode RES 7 6 rh Conversion Resolution Status This bit field indicates the resolution of the A D Converter for the conversion of the analog channel determined by CHNRSY 00B 10 bit resolution 1B 012 bit resolution 10B 8 bit resolution 11B Reserved EMUX 9 8 rh External Multiplexer Status This bit indicates the settings of the external multiplexer control lines that is used during an A D conve...

Page 2016: ...led for the analog channel determined by CHNRSY 0B Cancel Synchronize and Repeat is disabled 1B Cancel Synchronize and Repeat is enabled SYREQ 31 rh Synchronized Injection Request State This bit indicates whether a synchronized conversion is requested for the analog channel determined by CHNRSY 0B No synchronized conversion is requested 1B A synchronized conversion is requested 0 5 4 14 11 30 16 r...

Page 2017: ...f the channel that is currently converted 0000B Channel 0 is currently converted 0001B Channel 1 is currently converted B 1110B Channel 14 is currently converted 1111B Channel 15 is currently converted CHTSCC 10 8 rh Trigger Source of Channel Currently Converted This bit field indicates the origin of a conversion request that triggered the channel currently converted 000B Channel Injection 001B Ti...

Page 2018: ...es whether the ADC is in a sample phase or not 0B The ADC is currently not in the sample phase 1B The ADC currently samples the analog input voltage sample phase BUSY 15 rh Busy Status This bit indicates whether the ADC performs a conversion or not 0B The ADC is currently idle 1B The ADC currently performs a conversion QLP 19 16 rh Queue Level Pointer This bit field points to the empty queue eleme...

Page 2019: ...synchronized conversion is performed or this ADC module provides no slave functionality in the synchronized conversion 1B A synchronized conversion is performed and this ADC module provides slave functionality IENREQ 26 rh Interrupt Enable by Requestor This bit is set in the master ADC module after the master finished its synchronized conversion 0B The master does not finish the synchronized conve...

Page 2020: ...This bit is set if this ADC module enters the master slave mode It is cleared after the service request of synchronization mode is generated 0B This synchronized conversion has not been triggered by both modules 1B This synchronized conversion has been triggered by both modules at the same time 0 7 4 23 21 31 29 r Reserved Read as 0 Field Bits Type Description ...

Page 2021: ...n Control This bit field controls the resolution of the A D Converter for the conversion of the analog channel determined by CHNRIN Any modification of this bit field is taken into account after the currently running conversion is finished 00B 10 bit resolution 01B 12 bit resolution 10B 8 bit resolution 11B Reserved EMUX 9 8 rw External Multiplexer Control This bit indicates the settings of the ex...

Page 2022: ...ure is disabled 1B Cancel Inject and Repeat feature is enabled CINREQ 31 rw Channel Injection Request This bit is the request bit for Channel Injection It is automatically cleared after the requested conversion is injected 0B No Channel Injection requested 1B Channel Injection requested Note Clearing bit AP CHP causes bit CHIN CINREQ to be cleared 0 5 4 14 11 30 16 r Reserved Read as 0 should be w...

Page 2023: ... 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REQ 0 15 REQ 0 14 REQ 0 13 REQ 0 12 REQ 0 11 REQ 0 10 REQ 0 9 REQ 0 8 REQ 0 7 REQ 0 6 REQ 0 5 REQ 0 4 REQ 0 3 REQ 0 2 REQ 0 1 REQ 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description REQ0n n 0 15 n rw Software SW0 Conversion Request for Channel n 0B No conversion is requested for channel n 1B A conversion is requeste...

Page 2024: ...SW0 CRP 0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description SW0CRPn n 0 15 n rh Software SW0 Conversion Request Pending Flag for Channel n A SW0CRPn pending flag is set each time a conversion request is generated for channel n by SW0 that could not be serviced immediately A start of the conversion for a pending request leads automatically to a clear of the pending flag Al...

Page 2025: ... MSR CH 7 MSR CH 6 MSR CH 5 MSR CH 4 MSR CH 3 MSR CH 2 MSR CH 1 MSR CH 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description MSRCHn n 0 15 n rwh Module Service Request Status for Channel n A MSRCHn pending flag determines if a channel service request has been generated by A D Converter channel n 0B No channel service request has been generated by channel n 1...

Page 2026: ...rce service request has been generated This bit is cleared by writing a 1 to its bit position MSRSY 1 rwh Module Service Request Status for Source Synchronized Injection This bit specifies if a synchronized injection source service request has been generated 0B No Synchronized Injection source service request has been generated 1B A Synchronized Injection source service request has been generated ...

Page 2027: ...us for Source Auto Scan This bit specifies if a auto scan source service request has been generated 0B No auto scan source service request has been generated 1B A auto scan source service request has been generated This bit is cleared by writing a 1 to its bit position 0 31 4 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2028: ... 3 1 rw Timer Service Request Node Pointer These bit fields selects which service request output line will be activated when a timer service request event occurs and ENPT 1 000B Service request output SR0 is selected 001B 0Service request output SR1 is selected 010B Service request output SR2 is selected 011B Service request output SR3 is selected 100B Service request output SR4 is selected 101B S...

Page 2029: ...vice request when a queue service request event occurs 0B Queue service request generation is disabled 1B Queue service request generation is enabled PQR 11 9 rw Queue Service Request Node Pointer This bit fields selects which service request output line will be activated if the queue service request becomes active and ENPQR 1 000B Service request output SR0 is selected 001B Service request output...

Page 2030: ...quest becomes active and ENPAS 1 000B Service request output SR0 is selected 001B Service request output SR1 is selected 010B Service request output SR2 is selected 011B Service request output SR3 is selected 100B Service request output SR4 is selected 101B Service request output SR5 is selected 110B Service request output SR6 is selected 111B Service request output SR7 is selected 0 31 16 r Reser...

Page 2031: ...ules are supplied by a common separate clock control address decoding and interrupt control logic Four of the eight module s service request outputs are connected to interrupt nodes and four are connected to the DMA controller The 44 analog inputs are wired to the analog inputs of the two ADC modules with a fixed scheme One analog input of ADC1 is connected to an on chip temperature measurement un...

Page 2032: ...X1 ADC1 Module Kernel Analog Multiplexer Address Decoder AIN16 Analog Input Sharing Crossbar AN0 AN1 AN2 AN41 AN42 AN43 Die Temp Sensor AIN30 AIN31 P7 6 AD1EMUX0 P7 7 AD1EMUX1 VAGND1 VDD VSS VDDM VAREF1 VSSM Not Used fCLC Port 7 Control Port 7 Control AIN0 AIN15 Group 0 AIN0 AIN15 Group 0 ASGT SW0TR SW0GT ETR EGT QTR QGT TTR TGT External Request Unit SCU AIN31 ASGT SW0TR SW0GT ETR EGT QTR QGT TTR ...

Page 2033: ... ADC V2 0 25 3 2 ADC0 ADC1 Module Related External Registers Figure 25 31 ADC0 ADC1 Implementation Specific Special Function Registers MCA06034 ADC0_CLC ADC0_SRCn P7_IOCR0 ADC1_SRCn System Registers Interrupt Registers Port Register ADC0_FDR P7_IOCR4 P7_PDR n 0 3 TGADC0 TGADC1 Trigger Gating Register ...

Page 2034: ...part The fractional divider registers ADC0_FDR controls the frequency of fADC and makes it possible to enable disable it independently of fCLC The fractional divider s external clock enable feature is not used Signal RST_EXT_DIV of the fractional divider which is controlled by bit fields SC and DM of the ADC0_FDR register makes it possible to put the analog parts of the ADCs in its reset state Whe...

Page 2035: ...04 V2 0 2007 07 ADC V2 0 The following formulas define the frequency of fADC 25 11 25 12 Equation 25 11 is valid for ADC0_FDR DM 01B normal divider mode Equation 25 12 is valid for ADC0_FDR DM 10B fractional divider mode fADC fSYS 1 n with n 1024 FDR STEP fADC fSYS n 1024 with n 0 1023 ...

Page 2036: ...stem Units part Volume 1 ADC0_CLC ADC Clock Control Register 000H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indicates the c...

Page 2037: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM SC SM 0 STEP rw rw rw r rw Field Bits Type Description STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in suspend mode DM 15 14 rw Divider Mode This bit field selects normal divider mod...

Page 2038: ...s on the fractional divider register functionality are described in section Fractional Divider Operation on Page 3 29 of the TC1796 User s Manual System Units part Volume 1 DISCLK 31 rwh Disable Clock Hardware controlled disable for fOUT signal 0 10 27 26 rw Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2039: ...sh pull open drain capabilities and alternate output selections The output lines for the ADC modules are controlled by the port input output control registers P7_IOCR0 and P7_IOCR4 Table 25 14 shows how bits and bit fields must be programmed for the required I O functionality of the ADC0 ADC1 I O lines Table 25 14 ADC0 ADC1 I O Control Selection and Setup Module Port Lines Input Output Control Reg...

Page 2040: ... AD0EMUX2 Port input output control for P7 2 AD0EMUX0 Port input output control for P7 3 AD0EMUX1 1 Coding of bit field see Table 25 15 Shaded bits and bit fields are don t care for ADC I O port control P7_IOCR4 Port 7 Input Output Control Register 4 14H Reset Value 2020 2020H 31 28 23 20 15 12 7 4 0 PC7 0 PC6 0 PC5 0 PC4 0 rw r rw r rw r rw r Field Bits Type Description PC6 PC7 23 20 31 28 rw Por...

Page 2041: ...l outputs class A1 outputs Table 25 15 PCx Coding for ADC Outputs PCx 3 0 I O Output Characteristics Selected Pull up Pull down Selected Output Function 1011B Output Push pull Output function ALT1 1111B Open drain Output function ALT1 P7_PDR Port 6 Pad Driver Mode Register 40H Reset Value 0000 0000H 31 3 2 0 0 PD0 r rw Field Bits Type Description PD0 2 0 rw Pad Driver Mode for P7 7 0 XX0B Medium d...

Page 2042: ...RPS group select located in several kernel registers determines the analog input multiplexer group number that is used for channel selection Table 25 16 AN 43 0 to ADC0 ADC1 Analog Input Connections Analog Input Pin of TC1796 ADC0 Module ADC1 Module Connected to Analog Input of Module GRPS Connected to Analog Input of Module GRPS AN0 AIN0 0 AN1 AIN1 AN2 AIN2 AN3 AIN3 AN4 AIN4 AIN0 0 AN5 AIN5 AIN1 ...

Page 2043: ...N10 AN39 AIN11 AN40 AIN12 AN41 AIN13 AN42 AIN14 AN43 AIN15 On chip Die Temperature Sensor AIN31 12 1 These analog input pins of the are also used as analog inputs of the Fast Analog Digital Converter FADC 2 Additionally ADC1_CHCON15 EMUX must be set to 01B and SCU_CON DTSON must be set to 1 Table 25 16 AN 43 0 to ADC0 ADC1 Analog Input Connections cont d Analog Input Pin of TC1796 ADC0 Module ADC1...

Page 2044: ...CHCONn REF bit field In the TC1796 only ADC0 is able to select among three analog reference voltages VAREF0 AIN0 and AIN1 see Figure 25 33 In ADC1 always VAREF1 is selected as analog reference voltage source Note The selections ADC0_CHCONn REF 11B must not be used The settings of bit fields ADC1_CHCONn REF are don t care Figure 25 33 ADC0 ADC1 Reference Voltage Selections MCA06036 AIN0 AIN31 AIN1 ...

Page 2045: ... located in the System Control Unit SCU of the TC1796 Three output signals of GPTA0 are able to directly trigger A D Converter channels Figure 25 34 Request Gating Input Signal Connections ADC0 ADC1 The signal source for trigger and gating signals of each A D Converter ADC0 and ADC1 is selected via register TGADC0 and TGADC1 ERU MCA06037 ADCx EGT TGADCx ETR ETRSEL SW0GT TGADCx SW0TR SW0TRSEL TGT T...

Page 2046: ...to the figures in which the functionality of trigger gating signals are shown Table 25 17 Trigger Gating Source Input Selection Trigger Source Trigger Gating Input Selected Trigger Gating Source Timer see Figure 25 5 TTR ERU trigger outputs TROUT 3 0 or three GPTA0 channels direct trigger outputs selected by TGADCx TTRSEL TGT TGT 1 timer gating always enabled External Event see Figure 25 7 ETR ERU...

Page 2047: ...6 25 24 23 22 21 20 19 18 17 16 0 SW0GTSEL 0 EGTSEL r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TTRSEL 0 QTRSEL 0 SW0TRSEL 0 ETRSEL r rw r rw r rw r rw Field Bits Type Description ETRSEL 2 0 rw External Trigger Request Selection This bit determines which trigger source will be used for the ADCx external trigger request input ETR 000B ETR 0 no trigger function of ETR 001B ETR is connected to ...

Page 2048: ...ines which trigger source will be used for the ADCx queue trigger request input QTR 000B QTR 0 no trigger function of QTR 001B QTR is connected to GPTA0_OUT3 010B QTR is connected to GPTA0_OUT11 011B QTR is connected to GPTA0_OUT28 100B QTR is connected to TOUT0 101B QTR is connected to TOUT1 110B QTR is connected to TOUT2 111B QTR is connected to TOUT3 TTRSEL 14 12 rw Timer Trigger Request Select...

Page 2049: ...ly enabled 101B EGT is connected to PDOUT1 110B EGT is connected to PDOUT2 111B EGT is connected to PDOUT3 SW0GTSEL 22 20 rw SW0 Gating Selection This bit determines which trigger source will be used for the ADCx software gating input SW0GT 000B SW0GT 0 conversion request source Software is permanently disabled 001B SW0GT is connected to PDOUT0 010B SW0GT is connected to PDOUT2 011B SW0GT is conne...

Page 2050: ...e Request Node 3 SR4 CH02_REQI2 CH12_REQI3 DMA Channel 02 Request Input 2 DMA Channel 12 Request Input 3 SR5 CH03_REQI2 CH13_REQI3 DMA Channel 03 Request Input 2 DMA Channel 13 Request Input 3 SR6 CH10_REQI3 CH14_REQI3 DMA Channel 10 Request Input 3 DMA Channel 14 Request Input 3 SR7 CH11_REQI3 CH15_REQI3 DMA Channel 11 Request Input 3 DMA Channel 15 Request Input 3 ADC1 SR0 ADC1_SRC0 ADC1 Service...

Page 2051: ... die temperature measurement sensor see also Page 25 101 Detailed information about this die temperature sensor is provided in the section Die Temperature Sensor on Page 5 48 of the TC1796 User s Manual System Unit Volume 1 SRCm m 0 3 Service Request Control Register m 1FCH m 4 Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CL...

Page 2052: ...equency signals For slow and mid range frequency signals heavy over sampling can be performed to avoid the use of expensive filters ADC0 and ADC1 are described in Chapter 25 This chapter describes in detail the FADC and contains the following sections Functional description of the FADC Kernel see Page 26 2 FADC kernel registers description see Page 26 27 TC1796 implementation specific details and ...

Page 2053: ... and gain calibration support for each channel Differential input amplifier with programmable gain of 1 2 4 and 8 for each channel Free running Channel Timers or triggered conversion modes Trigger and gating control for external signals Built in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable programmable antialiasing and da...

Page 2054: ...ogrammable antialiasing and data reduction filters The Channel Trigger Control block determines the trigger and gating conditions for the four FADC channels The Channel Timers can independently trigger the conversion of each FADC channel The A D Control block is responsible for the overall FADC functionality The FADC module is supplied by the following power supply and reference voltage lines VDDM...

Page 2055: ...e gain of the common amplifier used during an A D conversion is selected individually for each of the four channels depending on the currently active channel x Figure 26 2 Analog Input Stage In Multiplexer Test Mode GCR MUXTM 1 the channel amplifiers are disconnected from the common amplifier The measured conversion result in multiplexer test mode should be 10 0000 0000B 200H plus minus the offset...

Page 2056: ...measurement mode for VVAREF 2 FAINxN The positive analog input FAINxP is disconnected is in a high impedance state The negative analog input FAINxN is connected to the channel amplifier input impedance is determined by Rn The positive input of the channel amplifier is connected to VFAREF 2 1 65 V with VFAREF 3 3 V If the voltage at the negative input FAINxN varies the FADC will deliver conversion ...

Page 2057: ...channel amplifier is connected to VFAREF 2 1 65 V with VFAREF 3 3 V If the voltage at the positive input FAINxP varies the FADC will deliver conversion results as follows gain 1 selected by ACRx GAIN 00B FAINxP 0 V FADC conversion result is 256 FAINxP 3 3 V FADC conversion result is 768 To cover the full range of the measurement result in this single ended measurement mode a gain of 2 must be sele...

Page 2058: ...ected to the same pin at the same time the input impedances of the analog inputs must be taken into account in order to minimize signal distortions and measurement errors Table 26 1 Conversion Results in the Different Measurement Modes Measurements Modes ACRx ENP ACRx ENN FAINxP FAINxN ACRx GAIN Conv Results Single ended Measurement Mode Configuration 1 0 1 don t care 0 00B 768 3 3 256 0 01B 1023 ...

Page 2059: ...nt if ENPx 0 then VFAINxP VFAREFM if ENNx 0 then VFAINxN VFAREFM 26 1 2 Conversion Timing The conversion time of the FADC is determined by the frequency of clock fFADC The conversion time defined below includes sampling converting and storing of the conversion result 26 2 Clock fFADC is generated outside the FADC kernel in a product specific clock control unit see Page 26 58 VMx VFAREF leads to RC...

Page 2060: ...put and gating mode selection logic generate an enable signal for channel x timer that determines whether any of the three conversion trigger signal sources is allowed to set the channel x conversion request flag CRFx This control logic does the following control tasks Gating source input selection CFGRx GSEL Gating mode selection CFGRx GM Trigger source input selection CFGRx TSEL Trigger mode sel...

Page 2061: ...el Timer is stopped CRFx never becomes set by hardware 01B Conversion requests and Channel Timer are always enabled CRFx becomes set by hardware with each active trigger signal 10B When gating source input GSn 1 as selected by CFGRx GSEL the Channel Timer is enabled and the conversion request flag CRFx becomes set by hardware with each active trigger signal 11B When gating source input GSn 0 as se...

Page 2062: ...mer clock fCTx is enabled and if enabled the frequency of channel x timer input clock fCTx While the Channel Timer is disabled CFGRx CTM 00B or if the gating condition is not met gating line ECHTIMx delivers 0 the channel x timer value is set to 04H Figure 26 5 Channel Timer Block Diagram Due to the common divider the first event at the trigger output of CHTIMx after the start has a maximum jitter...

Page 2063: ...e channels are converted according to a priority scheme as defined by the bit field GCR CRPRIO without respecting the status of the current filter sequences 26 1 5 3 Dynamic Priority Assignment If dynamic priority assignment is enabled GCR DPAEN 1 a channel that has the only active gate signal signal ECHTIMx in Figure 26 4 among the four channels gets the highest priority GCR CRPRIO is set to the ...

Page 2064: ...or example by using the Channel Timers as request sources with fast conversion data request rates it can be sometimes difficult or even impossible for a CPU or another bus master to collect all conversion results without the risk of losing conversion data Therefore a Data Reduction Unit is implemented in the FADC that operates as a kind of antialiasing filter This unit allows the number of convers...

Page 2065: ... Analog to Digital Converter FADC User s Manual 26 14 V2 0 2007 07 FADC V2 0 Figure 26 6 FADC Filter Blocks MCA06043 RCH0 Conversion Result Registers RCH1 RCH2 RCH3 A D Converter Filter Block 1 Filter Block 0 FRR0 FRR1 Final Result Registers ...

Page 2066: ...t Register IRR1n The three intermediate result registers operate as a kind of pipeline Before IRR1n is overwritten IRR2n is transferred to IRR3n and IRR1n is transferred to IRR2n The Final Result Register FRRn stores the sum that is built by the contents of the current result register and the intermediate result registers All result registers of the filter block are fully transparent and can be re...

Page 2067: ...V 7 CV 8 CV 9 CV 10 CV 11 CV 12 CV 13 CV 14 CV 15 CV 16 CV 17 CV 18 CV 19 CV 20 CV 21 CV 22 CV 23 Initial Start of Filter Algorithm Time 0 IRR1 0 IRR2 0 IRR3 IR1 0 0 IR2 IR1 0 IR3 IR2 IR1 0 0 0 0 FRR 0 0 0 IR1 0 0 IR1 IR2 C 0 IR1 IR2 IR3 C C C IR1 IR2 IR3 IR4 IR2 IR3 IR4 IR5 0 CRR CV0 CV0 CV1 CV0 CV1 CV2 CV4 CV4 CV5 CV4 CV5 CV6 CV8 CV8 CV9 CV8 CV9 CV10 CV12 CV12 CV13 CV12 CV13 CV14 IR4 IR3 IR2 CV1...

Page 2068: ...used for the final result calculation After a final result calculation the old contents of IRR20 are transferred into IRR30 and IRR10 are transferred into IRR20 for filter block 0 In filter block 1 the contents of CRR1 are stored in IRR11 The old contents of IRR30 or IRR11 are lost Finally the value of CRRn is transferred as intermediate result into the intermediate result register IRR1n Thereafte...

Page 2069: ... This parameter determines the number of intermediate result registers that are used for a final result calculation FCRn MAVL is loaded into CRRn MAVS at the start of a filter sequence Values for none up to three intermediate result registers can be selected for FCRn MAVL Initial State In order to start a filter algorithm for filter block n the following actions must be executed 1 Program bit fiel...

Page 2070: ...mple Filter 0 operates with the same parameters as in the example shown in Figure 26 8 A Filter 1 input value is given by each final result of filter 0 Filter 1 can store only one intermediate result in its IRR11 register MCT06046 Time FR0 Filter 0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 v FR12 v FR13 v FR14 FRR1 0 IR1 0 0 IR1 IR2 IR2 IR3 IR3 IR4 Filter 1 Initial Start of Filter Algorithm IR...

Page 2071: ...when the filter 1 result register width is calculated Filter 1 also allows eight input values filter 0 final results to be added in its current result register for an intermediate result This results in 15 3 18 bits width for the current result register and for the intermediate result registers of filter 1 The final result is built in filter 1 by the addition of maximum two current intermediate re...

Page 2072: ...if the gating condition gating mode selection output at high level in Figure 26 4 in the corresponding neighbor channel is valid All neighbor channel trigger enable bits ENxy are all located in the Neighbor Channel Trigger Register NCTR Index x indicates the number of the channel that starts a neighbor channel trigger Index y is the number of the neighbor channel to be triggered Figure 26 10 Neigh...

Page 2073: ...mal conversion mode without restrictions Figure 26 11 Analog Input and Channel Amplifier Configuration at Calibration Figure 26 11 shows the channel amplifier configuration as well as the analog input pin configurations that are selected during offset and gain calibration Note that in the calibration modes the impedance of the analog inputs depends on the settings of the ENN and ENP bits of the co...

Page 2074: ... offset is equal to 512 If the conversion result exceeds the tolerated range bit field ACRx CALOFF with x specifying the calibrated channel can be adjusted and a new conversion can be started The calibration process is finished when the conversion result is in the tolerated offset range After switching back to normal mode for channel x a delay of minimum 5 µs must be respected before starting a ne...

Page 2075: ...ontrolled by an identical control logic This control logic as shown in Figure 26 13 provides the following functionality Service Request Flag Set Clear Request Flag Control Bits Service Request Enable Bit Service Request Node Pointer Figure 26 13 Service Request Control Logic MCA06049 Service Request Compressor Filter Block 0 calculation finished Channel 0 conversion finished SR0 SR1 SR2 SR3 Chann...

Page 2076: ...compressor logic shown in Figure 26 14 the inputs of one SRx OR gate are connected to all demultiplexer outputs with identical INP node pointer value Therefore one service request event can only be assigned to one of the four service request outputs but one service request output can be used by multiple service request events Figure 26 14 Service Request Compressor Logic Table 26 6 Service Request...

Page 2077: ...tion of the FADC Module in a specific microcontroller the service request output signals SR 3 0 can either be connected to an interrupt node controlled by a service request control register or can be used as DMA request input of a DMA controller unit The TC1796 specific request output connections are described in Figure 26 16 and on Page 26 65 ...

Page 2078: ...gister names described in this section are referenced in other parts of the TC1796 User s Manual by the module name prefix FADC_ FADC Kernel Register Overview Figure 26 15 FADC Kernel Registers In the TC1796 the registers of the FADC module are located in the following address range Table 26 7 Registers Address Space FADC Module Module Base Address End Address Note FADC F010 0300H F010 03FFH MCA06...

Page 2079: ...CR Global Control Register 1CH Page 26 37 Channel Registers CFGRx Channel x Configuration Register x 0 1 20H x 4 Page 26 41 ACRx Channel x Analog Control Register x 0 1 30H x 4 Page 26 45 RCHx Channel x Conversion Result Register x 0 1 40H x 4 Page 26 47 Filter Registers FCRn Filter n Control Register n 0 1 60H n 20H Page 26 48 CRRn Filter n Current Result Register n 0 1 64H n 20H Page 26 51 Page ...

Page 2080: ... Identification Register 08H Reset Value 0027 C0XXH 31 16 15 8 7 0 MODNUM MODTYPE MODREV r r r Field Bits Type Description MODREV 7 0 r Module Revision Number MODREV defines the module revision number The value of a module revision starts with 01H first revision MODTYPE 15 8 r Module Type This bit field defines the module as a 32 bit module C0H MODNUM 31 16 r Module Number Value This bit field def...

Page 2081: ... Type Description CRFx x 0 3 x rh Conversion Request Flag This bit monitors whether a conversion request is pending for channel x CRFx is set by hardware when a trigger event is detected while the gating condition delivers 1 CRFx is automatically cleared by hardware when a conversion of the channel x is started 0B A conversion of channel x has not been requested 1B A conversion of channel x has be...

Page 2082: ...IRQx can be set cleared by software via bits FMR SIRQx and FMR RIRQx see Page 26 32 IRQFn n 0 1 20 n rh Interrupt Request Flag for Filter n This bit indicates that a filter sequence of filter n has been finished new final result is available since it has been cleared by software Interrupt requests can also be generated while IRQ is still set An interrupt can only be generated when FCRn IEN 1 0B A ...

Page 2083: ... S CRF 1 S CRF 0 0 R CRF 3 R CRF 2 R CRF 1 R CRF 0 r w w w w r w w w w Field Bits Type Description RCRFx x 0 3 x w Reset Conversion Request Flag This bit allows bit CRSR CRFx to be cleared by software 0B No operation 1B Bit CRSR CRFx is cleared also if bit SCRFx is written simultaneously with 1 SCRFx x 0 3 8 x w Set Conversion Request Flag This bit allows bit CRSR CRFx to be set by software 0B No ...

Page 2084: ...imultaneously with 0 0B No operation 1B Bit CRSR IRQx is set An interrupt is generated if CFGRx IEN 1 SIRQFn n 0 1 28 n w Set Interrupt Request Flag for Filter n This bit allows bit CRSR IRQFn to be set by software if bit RIRQFn is written simultaneously with 0 0B No operation 1B Bit CRSR IRQFn is set An interrupt is generated if FCRn IEN 1 0 7 4 15 12 23 22 31 30 r Reserved Read as 0 should be wr...

Page 2085: ...tion EN01 1 rw Enable Neighbor Channel Trigger 01 This bit enables the neighbor channel trigger for channel 1 when a conversion of channel 0 is started 0B No action 1B A trigger will be generated EN02 2 rw Enable Neighbor Channel Trigger 02 This bit enables the neighbor channel trigger for channel 2 when a conversion of channel 0 is started 0B No action 1B A trigger will be generated EN03 3 rw Ena...

Page 2086: ...rted 0B No action 1B A trigger will be generated EN21 17 rw Enable Neighbor Channel Trigger 21 This bit enables the neighbor channel trigger for channel 1 when a conversion of channel 2 is started 0B No action 1B A trigger will be generated EN23 19 rw Enable Neighbor Channel Trigger 23 This bit enables the neighbor channel trigger for channel 3 when a conversion of channel 2 is started 0B No actio...

Page 2087: ...quests e g 0 triggers 2 2 triggers 3 and 3 triggers 0 etc It is in the responsibility of the user to set these bits in an appropriate way EN32 26 rw Enable Neighbor Channel Trigger 32 This bit enables the neighbor channel trigger for channel 2 when a conversion of channel 3 is started 0B No action 1B A trigger will be generated 0 0 7 4 9 15 12 18 23 20 31 27 r Reserved Read as 0 should be written ...

Page 2088: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RST F1 RST F0 RCD 0 RCT 3 RCT 2 RCT 1 RCT 0 r w w w r w w w w Field Bits Type Description RCTx x 0 3 x w Reload Channel Timer 0B Channel x Timer will not be changed 1B Channel x Timer will be loaded with its reload value RCD 8 w Reset Common Divider 0B The common divider will not be changed 1B The common divider will be cleared RSTFn n 0 1 9 n w Reset Filter...

Page 2089: ... 18 rw Dynamic Priority Assignment Enable If the dynamic priority assignment is enabled the priority bit field CRPRIO is automatically changed as a function of the gating input signals In this case the channel that is active while the other three channels are not active gets the highest priority 0B The dynamic priority assignment is disabled 1B The dynamic priority assignment is enabled RESWEN 19 ...

Page 2090: ...t must be set to convert the analog input signal to a digital value 0B The complete analog part is in power down mode the amplifiers and comparators are switched off Conversions are not possible default 1B The analog part is enabled CALMODE 25 24 rw Calibration Mode This bit field enables the calibration for offset and gain for the channel selected by CALCH 00B No calibration process is running Al...

Page 2091: ... of CALCH is only taken into account while a calibration process is running 00B The analog input channel 0 is selected for a calibration process 01B The analog input channel 1 is selected for a calibration process 10B The analog input channel 2 is selected for a calibration process 11B The analog input channel 3 is selected for a calibration process 0 7 4 15 11 23 22 31 28 r Reserved Read as 0 sho...

Page 2092: ...ignal for channel x 000B Gating source input signal GS0 selected 001B Gating source input signal GS1 selected 010B Gating source input signal GS2 selected 011B Gating source input signal GS3 selected 100B Gating source input signal GS4 selected 101B Gating source input signal GS5 selected 110B Gating source input signal GS6 selected 111B Gating source input signal GS7 selected TSEL 5 3 rw Trigger ...

Page 2093: ...put as selected by CFGRx GSEL is at high level 11B Conversion requests and the Channel Timer are enabled only if the gating source input as selected by CFGRx GSEL is at low level TM 9 8 rw Trigger Mode This bit field enables the triggering and determines the edge of the trigger source input signal that generates a conversion trigger signal 00B No conversion trigger signals are generated Edge detec...

Page 2094: ...C 010B fCTx is enabled with frequency fFADC 4 011B fCTx is enabled with frequency fFADC 16 100B fCTx is enabled with frequency fFADC 64 101B fCTx is enabled with frequency fFADC 256 110B fCTx is enabled with frequency fFADC 1024 111B Reserved do not use this combination CTREL 23 16 rw Channel Timer Reload Value This bit field determines the reload value of the Channel Timer CHTIMx The divider fact...

Page 2095: ... Interrupt Enable This bit enables the generation of a service request when a conversion of channel x is finished 0B Channel x conversion service request generation is disabled 1B Channel x conversion service request generation is enabled 0 15 27 24 30 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 2096: ... 0 ENN ENP GAIN r rw rw r rw r rw rw rw Field Bits Type Description GAIN 1 0 rw Amplifier Gain This bit field determines the amplifier gain for channel x 00B The selected amplifier gain is 1 01B The selected amplifier gain is 2 10B The selected amplifier gain is 4 11B The selected amplifier gain is 8 ENP 2 rw Enable Positive Input This bit enables the voltage measurement on the FAINxP analog input...

Page 2097: ...s not available 1B Analog input FAINxN line is connected to the channel amplifier The lower half of the measuring range is available CALOFF 2 0 10 8 rw Calibrate Offset This bit field determines the value applied for the offset calibration for channel x The calibrate offset value is composed by the most significant bit CALOFF3 and bit field CALOFF 2 0 resulting in a 4 bit bit field CALOFF 3 0 CALO...

Page 2098: ...rsion Result Register 40H x 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ADRES r rwh Field Bits Type Description ADRES 9 0 rwh AD Conversion Result This bit field contains the conversion result of channel x ADRES can only be overwritten by software if GCR RESWEN 1 see also register GCR description on Page 26 38 0 31 10 r Rese...

Page 2099: ...4 3 2 1 0 IEN 0 INP 0 INSEL 0 MAVL 0 ADDL rw r rw r rw r rw r rw Field Bits Type Description ADDL 2 0 rw Addition Length This bit field determines the number of filter input values that are added to obtain one intermediate result 000B Each filter input value is considered as intermediate result 001B 2 filter input values are added up 010B 3 filter input values are added up 011B 4 filter input valu...

Page 2100: ...CR IRR1n IR IRR2n IR IRR3n IR Bit combinations 10B and 11B are not available in filter block 1 INSEL 10 8 rw Input Selection This bit field enables the filter block and determines which input value is taken for filter block n 000B The filter block is disabled Intermediate and final sum calculations are not executed The filter register values are not changed except by a filter block reset 001B Any ...

Page 2101: ...bit field selects which service request output line will be activated when a final result of filter block n is available while bit IEN is set 00B Service request output SR0 selected 01B Service request output SR1 selected 10B Service request output SR2 selected 11B Service request output SR3 selected IEN 15 rw Interrupt Enable This bit enables the generation of a new final result service request o...

Page 2102: ...MAVS 0 AC 0 r rh r rh r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CR r rh Field Bits Type Description CR 12 0 rh Current Result This bit field 12 0 for filter 0 17 0 for filter 1 contains the right aligned current result value of filter 0 CR is cleared when writing GCR RSTFn 1 AC 26 24 rh Addition Count This bit field indicates the number of additions of filter input values with remain to be execute...

Page 2103: ... calculation busy flag Therefore it is recommended to read a valid filter result from register FRRn only when the corresponding interrupt request flag CRSR IRQFn is set MAVS is cleared when writing GCR RSTFn 1 0 23 13 27 31 30 r Reserved Read as 0 CRR1 Filter 1 Current Result Register 84H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MAVS 0 AC 0 CR r rh r rh r rh 15 14 1...

Page 2104: ...9 28 rh Moving Average State This bit field indicates how many intermediate register transfers remain to be executed for the generation of the next final result MAVS 0 indicates the end of a filter calculation operation Since the filter calculation is executed very fast in comparison to a conversion MAVS 0 can be interpreted only as a kind of calculation busy flag Therefore it is recommended to re...

Page 2105: ... r rh Field Bits Type Description IR 12 0 rh Intermediate Result This bit field contains the right aligned intermediate result of filter 0 IR is cleared when writing GCR RSTFn 1 0 31 13 r Reserved Read as 0 IRR11 Filter 1 Intermediate Result Register 1 88H Reset Value 0000 0000H 31 18 17 0 0 IR r rh Field Bits Type Description IR 17 0 rh Intermediate Result This bit field contains the right aligne...

Page 2106: ... DMA operation after a corresponding interrupt request flag CRSR IRQFn has been set FRR0 Filter 0 Final Result Register 74H Reset Value 0000 0000H 31 15 14 0 0 FR r rh Field Bits Type Description FR 14 0 rh Final Result This bit field contains the right aligned 15 bit final result of filter 0 FR is cleared when writing GCR RSTFn 1 0 31 15 r Reserved Read as 0 FRR1 Filter 1 Final Result Register 94...

Page 2107: ...re 26 16 shows the TC1796 specific implementation details and interconnections of the FADC module Figure 26 16 FADC Module Implementation and Interconnections Clock Control Address Decoder MCA06053 VFAGND VDDAF VSSAF VDDMF VFAREF VSSMF Interrupt Control TS 7 0 GS 7 0 fFADC fCLC SR 3 0 FADC Module Kernel FAIN0P FAIN0N FAIN1P FAIN1N FAIN2P FAIN2N FAIN3P FAIN3N To DMA External Request Unit SCU GPTA0 ...

Page 2108: ...ht outputs of the GPTA0 module and two outputs of the external request unit The eight analog inputs are wired to analog inputs of the TC1796 The analog input lines of the FADC can also be used as input lines for ADC0 and ADC1 If both ADC0 ADC1 and FADC are connected to the same analog input pin at the same time the input impedances of both analog inputs must be taken into account in order to minim...

Page 2109: ...ck is the module clock that is used in the FADC as the clock for the Channel Timer and the analog part It also controls the conversion timing see Page 26 8 The fractional divider registers FADC_FDR controls the frequency of fFADC and allows it to be enabled disabled independently of fCLC Figure 26 18 FADC Clock Generation The following formulas define the frequency of fFADC 26 3 26 4 Equation 26 3...

Page 2110: ...96 User s Manual System Units part Volume 1 CLC Clock Control Register 00H Reset Value 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FS OE SB WE E DIS SP EN DIS S DIS R r rw w rw rw r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable disable control of the module DISS 1 r Module Disable Status Bit Bit indica...

Page 2111: ...iption STEP 9 0 rw Step Value Reload or addition value for RESULT SM 11 rw Suspend Mode SM selects between granted or immediate suspend mode SC 13 12 rw Suspend Control This bit field determines the behavior of the fractional divider in suspend mode DM 15 14 rw Divider Mode This bit field selects normal divider mode fractional divider mode and off state RESULT 25 16 rh Result Value Bit field for t...

Page 2112: ...own device connection capabilities The request input lines used by the FADC module are controlled by the port input output control registers P1_IOCR0 and P7_IOCR0 After reset for the external request inputs the input function with a pull up device is selected For reference the P1_IOCR0 and P7_IOCR0 functionality is shown on the next page in respect to the FADC external request inputs DISCLK 31 rwh...

Page 2113: ...r Field Bits Type Description PC0 PC1 7 4 15 12 rw Port Output Control for Port 7 Pins 0 31 These bit fields determine the output port functionality Port input output control for P7 0 REQ4 Port input output control for P7 1 REQ5 1 Coding of bit field see Table 26 8 Shaded bits and bit fields are don t care for FADC I O port control Table 26 9 PCx Coding for FADC Inputs PCx 3 0 I O Selected Input F...

Page 2114: ...6 User s Manual System Units part Volume 1 FADC_SRCm m 0 3 FADC Service Request Control Register m FCH m 4H Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET R CLR R SRR SRE 0 TOS 0 SRPN w w rh rw r rw r rw Field Bits Type Description SRPN 7 0 rw Service Request Priority Number TOS 10 rw Type of Service Control SRE 12 rw Service Re...

Page 2115: ...e inputs GS 7 0 and trigger source inputs TS 7 0 of the FADC module are connected to GPTA0 module outputs of GPIO port lines and external request unit outputs according to Table 26 10 Table 26 10 FADC Trigger Gating Source Input Connections Inputs Signal From Module Gating Source Inputs GS0 P1 0 REQ0 Port 1 GS1 P7 0 REQ4 Port 7 GS2 PDOUT2 External Request Unit ERU located in the SCU GS3 PDOUT3 GS4...

Page 2116: ...st lines interconnections Table 26 11 Service Request Lines Interconnections Module Service Request Line Connected To Description FADC SR0 FADC_SRC0 CH10_REQI2 CH14_REQI2 FADC Service Request Node 0 DMA Channel 10 Request Input 2 DMA Channel 14 Request Input 2 SR1 FADC_SRC1 CH11_REQI2 CH15_REQI2 FADC Service Request Node 1 DMA Channel 11 Request Input 2 DMA Channel 15 Request Input 2 SR2 FADC_SRC2...

Page 2117: ...78 2 ASCRP 25 77 2 CHCONm 25 60 2 CHIN 25 90 2 CHSTATm 25 63 2 CON 25 82 2 EXCRP 25 74 2 EXTC 25 73 2 ID 25 59 2 LCCONx 25 80 2 MSS0 25 94 2 MSS1 25 95 2 Offset addresses 25 58 2 QR 25 71 2 QUEUE0 25 69 2 REQ0 25 92 2 SAL 25 79 2 SCN 25 75 2 SCON 25 81 2 SRNP 25 97 2 STAT 25 86 2 SW0CRP 25 93 2 SYSTAT 25 84 2 TCON 25 66 2 TCRP 25 68 2 TSTAT 25 67 2 TTC 25 65 2 Service request processing 25 43 2 Sy...

Page 2118: ...PBCU 6 5 1 Bus agents and priorities 6 5 1 Error handling 6 6 1 Operation 6 5 1 Registers 6 7 1 SBCU and RBCU 6 24 1 Bus agents and priorities 6 24 1 Bus arbitration 6 24 1 Bus error handling 6 25 1 Registers 6 34 1 Starvation prevention 6 25 1 Boot 4 12 1 Normal boot 4 14 1 Scheme 4 12 1 Selection table 4 12 1 Boot ROM 4 16 1 Alternate Boot Mode 4 28 1 Program Structure 4 16 1 C CAN Address map 2...

Page 2119: ...lication watchdog 22 150 2 Automatic TUR adjust 22 115 2 Configuration 22 148 2 Cycle time 22 115 2 Error handling 22 150 2 Interrupt control 22 152 2 Local offset and global time 22 118 2 Local time generation 22 114 2 Master reference mark 22 117 2 MSC handling 22 151 2 Reference message 22 120 2 Scheduler 22 123 2 Scheduler entry setup 22 142 2 Scheduler entry types 22 125 2 ARBE 22 131 2 BCE 2...

Page 2120: ... 3 1 Execution unit 2 5 1 Features 2 2 1 General purpose register file 2 6 1 Implementation specific features 2 2 1 Instruction fetch unit 2 4 1 Registers 2 9 1 Core debug registers 2 17 1 CPS registers 2 13 1 CPU_SRCn 2 14 1 CSFRs 2 10 1 GPRs 2 15 1 Memory protection registers 2 20 1 MMU_CON 2 12 1 PSW 2 11 1 SBSRC0 2 19 1 TRnEVT 2 18 1 CPU see also Processor subsystem CSCOMB control 13 28 1 CSFR...

Page 2121: ...ol 12 20 1 DMI Dual ported RAM 2 32 1 Features 2 31 1 Registers DMI_ATR 2 39 1 DMI_CON 2 36 1 DMI_CON1 2 37 1 DMI_STR 2 38 1 DMU Access performance 8 7 1 Block diagram 8 1 1 Data access overlay operation 8 3 1 Data access redirection 8 4 1 Emulation memory overlay 8 7 1 Registers 8 10 1 ID 8 11 1 OMASKx 8 16 1 OTARx 8 15 1 RABRx 8 13 1 SBRCTR 8 12 1 SBRAM 8 2 1 SRAM 8 2 1 Document Structure 1 1 1 ...

Page 2122: ...RSELx 13 90 1 BFCON 13 86 1 BUSAPx 13 97 1 BUSCONx 13 92 1 CLC 13 82 1 CON 13 83 1 EMUAS 13 101 1 EMUBAP 13 106 1 EMUBC 13 102 1 EMUOVL 13 110 1 ID 13 81 1 Overview 13 79 1 USERCON 13 111 1 EBU see External bus interface unit EEPROM emulation 7 26 1 Emergency stop output control 5 57 1 for GPTA 5 58 1 Register SCU_EMSR 5 59 1 Entering Sleep Mode 5 6 1 Error correction in Flash 7 34 1 External bus ...

Page 2123: ...3 1 Enter Page Mode 7 15 1 Erase Sector 7 20 1 Erase User Configuration Block 7 22 1 Load Page Buffer 7 16 1 Reset to Read 7 15 1 Resume Protection 7 24 1 Write Page 7 18 1 Write User Configuration Page 7 19 1 Data Flash Bank sector and page definitions 7 8 1 Features 7 8 1 Overview 7 7 1 Structure 7 7 1 EEPROM emulation 7 26 1 Error correction 7 34 1 Interrupt 5 36 1 Interrupt generation and cont...

Page 2124: ...stop output control 5 58 1 Features of GPTA0 GPTA1 24 3 2 Input IN1 control 5 49 1 Interrupt processing and control 24 112 2 24 231 2 Module implementations 24 247 2 Block diagram 24 248 2 Cascading limits 24 272 2 External registers 24 249 2 Input output function selection 24 251 2 Module clock generation 24 265 2 On chip connections 24 256 2 Port control and connections 24 250 2 Overview 24 2 2 ...

Page 2125: ... 14 15 1 Overview 14 1 1 Priorities 14 19 1 Service request control register 14 3 1 14 4 1 Service request node table 14 23 1 Service request nodes 14 3 1 Service routine entering 14 13 1 Service routine exiting 14 14 1 Software initiated interrupts 14 22 1 Interrupts Special system interrupts 5 35 1 External interrupts 5 36 1 Flash interrupt 5 36 1 FPU interrupt 5 35 1 L LFI bridge 6 15 1 Address...

Page 2126: ...23 14 2 Write offset and data frame 23 13 2 Handshake signalling 23 19 2 Interrupts 23 55 2 Receiver interrupts 23 60 2 Transmitter interrupts 23 57 2 Kernel registers 23 75 2 Module implementation 23 124 2 Access protection 23 141 2 Clock generation 23 128 2 Input output function selection 23 130 2 MLI0 block diagram 23 125 2 23 126 2 On chip connections 23 139 2 Transfer window map 23 146 2 Nami...

Page 2127: ...1 34 2 Time frame finished interrupt 21 33 2 Kernel block diagram 1 19 1 21 3 2 Module implementation Input output function selection 21 70 2 Module clock control 21 65 2 Pad output driver characteristics selection 21 74 2 Overview 21 3 2 Registers DC 21 59 2 DD 21 59 2 DSC 21 41 2 DSDSH 21 47 2 DSDSL 21 46 2 DSS 21 44 2 ESR 21 48 2 ICR 21 49 2 ID 21 38 2 ISC 21 54 2 ISR 21 52 2 OCR 21 56 2 Offset...

Page 2128: ...CP 11 1 1 Accessing from FPI bus 11 48 1 Architecture 11 2 1 Channel programs 11 25 1 Context models 11 11 1 Control and interrupt registers 11 52 1 Debugging 11 50 1 Error handling 11 38 1 General purpose registers 11 6 1 Implementation in TC1796 11 125 1 Instruction set details 11 72 1 Instruction set overview 11 40 1 Instruction timing 11 108 1 Interrupt operation 11 32 1 Overview 11 1 1 Progra...

Page 2129: ...t 10 10 81 1 Configuration diagram 10 81 1 Register overview 10 82 1 Port 2 10 32 1 Configuration diagram 10 32 1 Function table 10 33 1 Register overview 10 37 1 Port 3 10 40 1 Configuration diagram 10 40 1 Function table 10 41 1 Register overview 10 45 1 Port 4 10 47 1 Configuration diagram 10 47 1 Function table 10 48 1 Register overview 10 51 1 Port 5 10 54 1 Configuration diagram 10 54 1 Func...

Page 2130: ... mode 5 6 1 Software configuration in TC1796 devices 10 25 1 via SWOPT bits 10 24 1 SSC Baud rate generation 20 18 2 20 48 2 Baud rate generation formulas 20 18 2 20 49 2 Block diagram 20 4 2 Chip select generation 20 21 2 DMA request outputs 20 60 2 Error detection 20 24 2 FIFO operation Receive FIFO 20 14 2 Transmit FIFO 20 12 2 Transparent Mode 20 16 2 Full duplex operation 20 6 2 Half duplex o...

Page 2131: ...Block diagram 5 42 1 Registers SCU_TCCLR1 5 47 1 SCU_TCCON 5 44 1 SCU_TCLR0 5 46 1 Switching thresholds 5 43 1 TTCAN see CAN W Watchdog timer 16 1 1 During power saving modes 16 17 1 Endinit function 16 3 1 Features 16 2 1 Functional description 16 5 1 in OCDS suspend mode 16 17 1 Modify access to WDT_CON0 16 11 1 Monitoring diagram 16 26 1 Operating modes 16 7 1 Disable mode 16 8 1 16 15 1 Normal...

Page 2132: ... 25 60 2 ADC0_CHIN 18 89 1 25 90 2 ADC0_CHSTAT0 18 89 1 ADC0_CHSTAT1 18 89 1 ADC0_CHSTAT10 18 90 1 ADC0_CHSTAT11 18 90 1 ADC0_CHSTAT12 18 90 1 ADC0_CHSTAT13 18 90 1 ADC0_CHSTAT14 18 90 1 ADC0_CHSTAT15 18 90 1 ADC0_CHSTAT2 18 89 1 ADC0_CHSTAT3 18 89 1 ADC0_CHSTAT4 18 89 1 ADC0_CHSTAT5 18 89 1 ADC0_CHSTAT6 18 89 1 ADC0_CHSTAT7 18 89 1 ADC0_CHSTAT8 18 89 1 ADC0_CHSTAT9 18 90 1 ADC0_CHSTATm 25 63 2 AD...

Page 2133: ... 1 ADC1_CHCON7 18 92 1 ADC1_CHCON8 18 92 1 ADC1_CHCON9 18 92 1 ADC1_CHCONm 25 60 2 ADC1_CHCONn 25 60 2 ADC1_CHIN 18 94 1 25 90 2 ADC1_CHSTAT0 18 94 1 ADC1_CHSTAT1 18 94 1 ADC1_CHSTAT10 18 94 1 ADC1_CHSTAT11 18 95 1 ADC1_CHSTAT12 18 95 1 ADC1_CHSTAT13 18 95 1 ADC1_CHSTAT14 18 95 1 ADC1_CHSTAT15 18 95 1 ADC1_CHSTAT2 18 94 1 ADC1_CHSTAT3 18 94 1 ADC1_CHSTAT4 18 94 1 ADC1_CHSTAT5 18 94 1 ADC1_CHSTAT6 ...

Page 2134: ... 1 BIV 2 10 1 18 109 1 BTV 2 10 1 18 109 1 C CAN module registers 22 59 2 CAN register address map 18 65 1 CAN_AWDR 18 69 1 22 168 2 CAN_CLC 18 65 1 22 202 2 CAN_CYCTMR 18 69 1 22 163 2 CAN_FDR 18 65 1 22 203 2 CAN_GMR 18 69 1 22 166 2 CAN_ID 18 65 1 22 61 2 CAN_LGMR 18 69 1 22 167 2 CAN_LIST0 18 66 1 CAN_LIST1 18 66 1 CAN_LIST2 18 66 1 CAN_LIST3 18 66 1 CAN_LIST4 18 66 1 CAN_LIST5 18 66 1 CAN_LIS...

Page 2135: ...67 1 CAN_MSID3 18 67 1 CAN_MSID4 18 67 1 CAN_MSID5 18 67 1 CAN_MSID6 18 67 1 CAN_MSID7 18 67 1 CAN_MSIDk 22 71 2 CAN_MSIMASK 18 67 1 22 72 2 CAN_MSPND0 18 66 1 CAN_MSPND1 18 66 1 CAN_MSPND2 18 66 1 CAN_MSPND3 18 67 1 CAN_MSPND4 18 67 1 CAN_MSPND5 18 67 1 CAN_MSPND6 18 67 1 CAN_MSPND7 18 67 1 CAN_MSPNDk 22 70 2 CAN_NBTR0 18 68 1 CAN_NBTR1 18 70 1 CAN_NBTR2 18 70 1 CAN_NBTR3 18 71 1 CAN_NBTRx 22 84 ...

Page 2136: ... 18 107 1 CPM1 2 22 1 2 23 1 18 108 1 CPMx 2 23 1 CPR0_0L 2 22 1 18 106 1 CPR0_0U 2 22 1 18 106 1 CPR0_1L 2 22 1 18 107 1 CPR0_1U 2 22 1 18 107 1 CPR1_0L 2 22 1 18 107 1 CPR1_0U 2 22 1 18 107 1 CPR1_1L 2 22 1 18 107 1 CPR1_1U 2 22 1 18 107 1 CPS register address map 18 104 1 CPS_ID 2 13 1 18 104 1 CPU_ID 2 10 1 18 109 1 CPU_SBSRC 2 13 1 CPU_SBSRC0 2 19 1 18 104 1 CPU_SRC0 18 104 1 CPU_SRC1 18 104 ...

Page 2137: ... 54 1 DMA_CHICR01 18 55 1 DMA_CHICR02 18 55 1 DMA_CHICR03 18 56 1 DMA_CHICR04 18 56 1 DMA_CHICR05 18 57 1 DMA_CHICR06 18 57 1 DMA_CHICR07 18 58 1 DMA_CHICR0x 12 81 1 DMA_CHICR10 18 58 1 DMA_CHICR11 18 59 1 DMA_CHICR12 18 59 1 DMA_CHICR13 18 60 1 DMA_CHICR14 18 60 1 DMA_CHICR15 18 61 1 DMA_CHICR16 18 61 1 DMA_CHICR17 18 62 1 DMA_CHICR1x 12 81 1 DMA_CHRSTR 12 51 1 18 53 1 DMA_CHSR00 18 54 1 DMA_CHSR...

Page 2138: ...SADR06 18 57 1 DMA_SADR07 18 58 1 DMA_SADR0x 12 88 1 DMA_SADR10 18 58 1 DMA_SADR11 18 59 1 DMA_SADR12 18 59 1 DMA_SADR13 18 60 1 DMA_SADR14 18 60 1 DMA_SADR15 18 61 1 DMA_SADR16 18 61 1 DMA_SADR17 18 62 1 DMA_SADR1x 12 88 1 DMA_SHADR00 18 55 1 DMA_SHADR01 18 55 1 DMA_SHADR02 18 56 1 DMA_SHADR03 18 56 1 DMA_SHADR04 18 57 1 DMA_SHADR05 18 57 1 DMA_SHADR06 18 58 1 DMA_SHADR07 18 58 1 DMA_SHADR0x 12 9...

Page 2139: ...1 DMU_OTARx 8 15 1 DMU_RABR0 18 118 1 DMU_RABR1 18 118 1 DMU_RABR10 18 120 1 DMU_RABR11 18 120 1 DMU_RABR12 18 120 1 DMU_RABR13 18 120 1 DMU_RABR14 18 121 1 DMU_RABR15 18 121 1 DMU_RABR2 18 118 1 DMU_RABR3 18 118 1 DMU_RABR4 18 119 1 DMU_RABR5 18 119 1 DMU_RABR6 18 119 1 DMU_RABR7 18 119 1 DMU_RABR8 18 119 1 DMU_RABR9 18 120 1 DMU_RABRx 8 13 1 DMU_SBRCTR 8 12 1 18 121 1 DPM0 2 22 1 18 107 1 DPM1 2...

Page 2140: ... FADC_FRR0 18 85 1 26 55 2 FADC_FRR1 18 86 1 26 55 2 FADC_GCR 18 84 1 26 37 2 FADC_ID 18 84 1 26 29 2 FADC_IRR10 18 85 1 26 54 2 FADC_IRR11 18 85 1 26 54 2 FADC_IRR20 18 85 1 26 54 2 FADC_IRR30 18 85 1 26 54 2 FADC_NCTR 18 84 1 26 34 2 FADC_RCH0 18 85 1 26 47 2 FADC_RCH1 18 85 1 26 47 2 FADC_RCH2 18 85 1 26 47 2 FADC_RCH3 18 85 1 26 47 2 FADC_SRC0 18 86 1 FADC_SRC1 18 86 1 FADC_SRC2 18 86 1 FADC_S...

Page 2141: ...M1 18 37 1 GPTA0_ID 18 33 1 24 154 2 GPTA0_LTCCTR63 24 188 2 GPTA0_LTCCTRk 24 180 2 GPTA0_LTCCTRn 18 38 1 GPTA0_LTCXR63 24 190 2 GPTA0_LTCXRk 24 190 2 GPTA0_LTCXRn 18 38 1 GPTA0_MMXCTR00 18 38 1 24 260 2 GPTA0_MMXCTR01 18 38 1 24 260 2 GPTA0_MMXCTR10 18 38 1 24 261 2 GPTA0_MMXCTR11 18 38 1 24 261 2 GPTA0_MRACTL 18 33 1 24 191 2 GPTA0_MRADIN 18 34 1 24 193 2 GPTA0_MRADOUT 18 34 1 24 193 2 GPTA0_PDL...

Page 2142: ... 1 GPTA1_DCMCTRk 24 161 2 GPTA1_DCMTIM0 18 44 1 GPTA1_DCMTIM1 18 44 1 GPTA1_DCMTIM2 18 45 1 GPTA1_DCMTIM3 18 45 1 GPTA1_DCMTIMk 24 163 2 GPTA1_FPCCTR0 18 43 1 GPTA1_FPCCTR1 18 43 1 GPTA1_FPCCTR2 18 43 1 GPTA1_FPCCTR3 18 43 1 GPTA1_FPCCTR4 18 43 1 GPTA1_FPCCTR5 18 44 1 GPTA1_FPCCTRk 24 156 2 GPTA1_FPCSTAT 18 43 1 24 155 2 GPTA1_FPCTIM0 18 43 1 GPTA1_FPCTIM1 18 43 1 GPTA1_FPCTIM2 18 43 1 GPTA1_FPCTI...

Page 2143: ...5 18 47 1 GPTA1_SRC36 18 47 1 GPTA1_SRC37 18 47 1 GPTA1_SRCk 24 273 2 GPTA1_SRNR 18 42 1 24 215 2 GPTA1_SRSC0 18 42 1 24 206 2 GPTA1_SRSC1 18 42 1 24 209 2 GPTA1_SRSC2 18 42 1 24 211 2 GPTA1_SRSC3 18 42 1 24 213 2 GPTA1_SRSS0 18 42 1 24 208 2 GPTA1_SRSS1 18 42 1 24 210 2 GPTA1_SRSS2 18 42 1 24 212 2 GPTA1_SRSS3 18 42 1 24 214 2 I ICR 2 10 1 14 8 1 18 109 1 IGCR0 5 26 1 18 9 1 IGCR1 5 29 1 18 9 1 I...

Page 2144: ...LI0_RP2STATR 18 99 1 23 113 2 MLI0_RP3BAR 18 98 1 23 115 2 MLI0_RP3STATR 18 99 1 23 113 2 MLI0_SCR 18 99 1 23 81 2 MLI0_TCBAR 23 104 2 MLI0_TCMDR 18 97 1 23 97 2 MLI0_TCR 18 97 1 23 90 2 MLI0_TDRAR 18 98 1 23 101 2 MLI0_TIER 18 99 1 23 105 2 MLI0_TINPR 18 99 1 23 108 2 MLI0_TISR 18 99 1 23 107 2 MLI0_TP0AOFR 18 97 1 23 103 2 MLI0_TP0BAR 18 98 1 23 102 2 MLI0_TP0DATAR 18 98 1 23 101 2 MLI0_TP0STATR...

Page 2145: ... 18 105 1 MPR register address map 18 105 1 MSC module registers 21 36 2 MSC0 register address map 18 16 1 MSC0_CLC 18 16 1 21 67 2 MSC0_DC 18 16 1 21 59 2 MSC0_DD 18 16 1 21 59 2 MSC0_DSC 18 16 1 21 41 2 MSC0_DSDSH 18 16 1 21 47 2 MSC0_DSDSL 18 16 1 21 46 2 MSC0_DSS 18 16 1 21 44 2 MSC0_ESR 18 16 1 21 48 2 MSC0_FDR 18 16 1 21 68 2 MSC0_ICR 18 17 1 21 49 2 MSC0_ID 18 16 1 21 38 2 MSC0_ISC 18 17 1 ...

Page 2146: ...25 1 P3_OUT 10 13 1 18 25 1 P3_PDR 10 46 1 18 25 1 P4_ESR 10 16 1 18 26 1 P4_IN 10 17 1 18 26 1 P4_IOCR0 10 7 1 18 26 1 P4_IOCR12 10 9 1 18 26 1 P4_IOCR4 10 8 1 18 26 1 P4_IOCR8 10 8 1 18 26 1 P4_OMR 10 14 1 18 26 1 P4_OUT 10 13 1 18 26 1 P4_PDR 10 53 1 18 26 1 P5_IN 10 57 1 18 27 1 P5_IOCR0 10 7 1 18 27 1 19 37 2 P5_IOCR4 10 8 1 18 27 1 21 71 2 23 135 2 P5_OMR 10 57 1 18 27 1 P5_OUT 10 57 1 18 27...

Page 2147: ... PMI_CON2 2 30 1 18 124 1 PMI_ID 2 27 1 18 124 1 PMU register address map 18 116 1 PMU_ID 7 42 1 18 116 1 Port 0 register address map 18 22 1 Port 1 register address map 18 23 1 Port 10 register address map 18 32 1 Port 2 register address map 18 24 1 Port 3 register address map 18 25 1 Port 4 register address map 18 26 1 Port 5 register address map 18 27 1 Port 6 register address map 18 28 1 Port ...

Page 2148: ... 18 81 1 20 38 2 SSC0_STAT 18 81 1 20 34 2 SSC0_TB 18 81 1 20 45 2 SSC0_TSRC 18 82 1 20 59 2 SSC0_TXFCON 18 81 1 20 42 2 SSC1 register address map 18 82 1 SSC1_BR 18 82 1 20 39 2 SSC1_CLC 18 82 1 20 50 2 SSC1_CON 18 82 1 20 32 2 SSC1_EFM 18 82 1 20 35 2 SSC1_ESRC 18 83 1 20 59 2 SSC1_FDR 18 82 1 20 51 2 SSC1_ID 18 82 1 20 29 2 SSC1_PISEL 18 82 1 20 30 2 SSC1_RB 18 82 1 20 45 2 SSC1_RSRC 18 83 1 20...

Page 2149: ...User s Manual L 33 V2 0 2007 07 TC1796 System and Peripheral Units Vol 1 and 2 Register Index WDT_SR 16 32 1 18 7 1 ...

Page 2150: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG ...

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