TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual
24-83
V2.0, 2007-07
GPTA, V2.0
shows another PCM example that demonstrates the difference between a
standard PWM signal and the derived PCM signal. During one PWM period (128 clock
cycles), the standard PWM signal is ON for 8 clock cycles and OFF for the remaining
120 clock cycles (duty cycle of 6.25%). The PCM signal operates with a PCM duty cycle
of 1/8 = 0.125 resulting in 8 ON pulses of 1 clock cycle width within 1 PWM period.
Figure 24-56 Pulse Count Modulation Example 2
Compare Value Switching
In both pulse modulation modes, it is possible to change the duty cycle either by software
or on an LTC input signal. LTC63 contains two registers, the compare register and a
shadow register. For software access, the compare register LTCXR63.X (= 16-bit low
part of LTCXR63) is written directly.
For compare value switching triggered by hardware, the shadow register LTCXR63.XS
(= 16-bit high part of LTCXR63) is pre-loaded with the desired duty cycle. On an LTC
input signal selected via the LTC input multiplexer,
•
The shadow register content LTCXR63.XS is copied to the compare register
LTCXR63.X,
•
The LTC63 service request flag is set,
•
An interrupt request will be activated if enabled by bit field LTCCTR63.REN.
The data input line LTC63IN can operate in two modes (selected by bit LTCCTR63.ILM):
•
Level Sensitive Mode or
•
Edge Sensitive Mode
In Edge Sensitive Mode, the active edges are selected by bits LTCCTR63.FED and
LTCCTR63.RED. In Level Sensitive Mode, the data input line LTCkIN is sensitive on a
high level.
PCM: 8 pulses with 1 clock cycle width
PWM: 1 pulse with 8 clock cycle width
8 Clock Cycles
MCT05965
PWM Period = 128 Clock Cycles
Standard
PWM Signal
PCM Signal
1 Clock Cycles
