TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual
22-147
V2.0, 2007-07
MultiCAN, V2.0
scheduler entries are then closed again with a BCE with GM = 0 (e.g. with a longer timing
value as a time-out criteria for a missing synchronization event).
22.6.5.3 Scheduler Sequence Example
The values given for CSM and BCC (both bit fields are located in register CYCTMR) lead
to valid scheduler entries RCE, TCE, ICE and ARBE (bit fields CYCLE, MCYCLE) and
the transmit control of the message objects (bit fields CYCLE, MCYCLE, COLUMN,
MCOLUMN). In the case that the programmed values for CYCLE, MCYCLE, etc. do not
match the given values of CSM and BCC, the respective entry is considered invalid and
its information is not taken into account for the corresponding time window. The following
example shows a scheduler instruction sequence for the basic cycle m with n time mark
entries:
•
TME1
•
RCE, ICE (CSM = n, BCC = m-1 or CSM = BCC = 0 when the Configuration Mode is
left)
•
TCE, ARBE (CSM = 0, BCC = m)
•
TME2
•
RCE, ICE (CSM = 1, BCC = m)
•
TCE, ARBE (CSM = 1, BCC = m)
•
TME3
•
RCE, ICE (CSM = 2, BCC = m)
•
TCE, ARBE (CSM = 2, BCC = m)
•
other time marks and instructions
•
TMEn
•
RCE, ICE (CSM = n-1, BCC = m)
•
TCE, ARBE (CSM = n-1, BCC = m)
•
RME (GM = 1, only for time masters)
•
BCE (GM = 1, for time masters and slaves)
•
RME (GM = 0, only for time masters)
•
BCE (GM = 0, for time masters and slaves)
