TC1796
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual
19-30
V2.0, 2007-07
ASC, V2.0
19.3
ASC0/ASC1 Module Implementation
This section describes ASC0/ASC1 module interfaces with the clock control, port
connections, interrupt control, and address decoding.
19.3.1
Interfaces of the ASC Modules
The serial I/O lines of both modules can be connected either to Port 5 or Port 6. Each of
the ASC modules is further supplied with interrupt control, address decoding, and port
control logic. Two DMA requests can be generated by each ASC module. Both ASC
modules are supplied by one common clock control unit.
Figure 19-12 ASC0/ASC1 Module Implementation and Interconnections
MCB05773
ASC0
Module
(Kernel)
Port 5
&
Port 6
Control
ASC1
Module
(Kernel)
P6.8 /
RXD0B
P6.9 /
TXD0B
Interrupt
Control
EIR
TBIR
TIR
RIR
Clock
Control
Address
Decoder
Interrupt
Control
f
ASC
EIR
TBIR
TIR
RIR
P5.0 /
RXD0A
P5.1 /
TXD0A
P6.10 /
RXD1B
P6.11 /
TXD1B
P5.2 /
RXD1A
P5.3 /
TXD1A
RXD_I1
RXD_O
RXD_I0
TXD_O
To
DMA
ASC0_RDR
ASC0_TDR
To
DMA
ASC1_RDR
ASC1_TDR
RXD_I1
RXD_O
RXD_I0
TXD_O
A2
A2
A2
A2
A2
A2
A2
A2