Infineon Technologies TC1796, User Manual

Page: 585 / 2150

TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-48 V2.0, 2007-07
PCP, V2.0
11.8 Accessing PCP Resources from the FPI Bus
Any FPI Bus master (on the TC1796’s System Peripheral Bus) can access the three
distinct PCP address ranges from the FPI Bus side. Normally, the CPU initializes the
control registers via FPI Bus access. Thereafter, the PCP should not access its control
registers itself through PCP instructions. Apart from the access via FPI Bus, there is no
direct way to the PCP control registers.
Accesses to the PCP control and status register, the PRAM, and the CMEM are detailed
in the following sections.
11.8.1 Access to the PCP Control Registers
FPI Bus accesses to the PCP control registers must always be performed in Supervisor
Mode with word accesses; byte or half-word accesses will result in a bus error.
All PCP control registers can be read at any time. Write operations are only possible to
the PCP_CS register, all other register are read-only. Register PCP_CS can be
optionally Endinit-protected via bit PCP_CS.EIE (see
Page 11-56 ).
11.8.2 Access to the PRAM
FPI Bus accesses to the PRAM must always be performed with word accesses; byte or
half-word accesses will result in a bus error.
Attention needs to be paid when accessing the CSAs and data sections of the PCP
channel programs. The location of a specific channel’s CSA is dependent on the chosen
Context Model, Full, Small or Minimum context.
Table 11-9 shows these addresses.
Table 11-9 FPI Bus Access to CSAs
Channel Full Context Small Context Minimum Context
0 (see
note) PRAM Base A
00
H
PRAM Base A
00
H
PRAM Base A
00
H
1 PRAM Base A
20
H
PRAM Base A
10
H
PRAM Base A
08
H
2 PRAM Base A
40
H
PRAM Base A
20
H
PRAM Base A
10
H
3 PRAM Base A
60
H
PRAM Base A
30
H
PRAM Base A
18
H
n PRAM Base A
n
×
20
H
PRAM Base A
n
×
10
H
PRAM Base A
n
×
08
H