TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual
3-29
V2.0, 2007-07
Clock, V2.0
A value of 00
H
in RMC disables the clock signals to these modules (CLC clock is
switched off). If RMC is not equal to 00
H
, the CLC clock for a unit is generated as
(3.4)
where RMC is the content of its CLC register RMC field with a range of 1 to 255. If RMC
is not available in a CLC register, the CLC clock frequency
f
CLC
is always equal to the
frequency of
f
SYS
.
Note: The number of module clock cycles (wait states) that are required for a
“destructive read” access (means: flags/bits are set/cleared by a read access) to
a module register of a peripheral unit depends on the selected CLC clock
frequency.
Therefore, a slower CLC clock (selected via bit field RMC in the CLC register) may
result in a longer read cycle access time on the FPI Buses for peripheral units with
“destructive read” access (e.g. the ASC).
3.3.3
Fractional Divider Operation
This section describes the module clock generation using the Fractional Divider.
3.3.3.1
Overview
The fractional divider makes it possible to generate a module clock from an input clock
using a programmable divider. The fractional divider divides the input clock
f
IN
either by
the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023, and outputs the
clock signal,
f
OUT
. The fractional divider is controlled by the FDR register.
shows the fractional divider block diagram.
The adder logic of the fractional divider can be configured for two operating modes:
•
Reload counter (addition of +1), generating an output clock pulse on counter overflow
•
Adder that adds a STEP value to the RESULT value and generates an output clock
pulse on counter overflow
f
CLC
=
f
SYS
/ RMC
MOD
