TC1796
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual
19-13
V2.0, 2007-07
ASC, V2.0
19.1.5.1 Baud Rates in Asynchronous Mode
For asynchronous operation, the baud rate generator provides a clock
f
BRT
with sixteen
times the rate of the established baud rate. Every received bit is sampled on the 7
th
, 8
th
and 9
th
cycle of this clock. The clock divider circuitry, which generates the input clock
f
DIV
for the 13-bit baud rate timer, is extended by a fractional divider circuitry that allows the
adjustment of more accurate baud rates and the extension of the baud rate range.
The baud rate of the baud rate generator depends on the settings of the following bits
and register values:
•
Input clock
f
ASC
•
Selection of the baud rate timer input clock
f
DIV
by bits CON.FDE and CON.BRS
•
If bit CON.FDE = 1 (fractional divider): value of register FDV
•
Value of the 13-bit reload register BG
The output clock of the baud rate timer with the reload register is the sample clock in the
asynchronous operating modes of the ASC. For baud rate calculations, this baud rate
clock
f
BR
is derived from the sample clock
f
BRT
by a devision of sixteen.
Figure 19-8 ASC Baud Rate Generator Circuitry in Asynchronous Modes
MCA05769
Sample
Clock
BRS
f
BRT
f
DIV
R
f
ASC
2
BRS
0
1
Selected Divider
3
Fractional
Divider
FDE
Baud
Rate
Clock
f
BR
FDE
0
0
X
1
Fractional Divider
MUX
3
2
16
13-Bit Baud Rate Timer
13-Bit Reload Register
