TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual
1-18
V2.0, 2007-07
Intro, V2.0
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
•
Baud rate generation from 37.5 MBaud to 572.2 Baud (@ 75 MHz module clock)
•
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
•
Flexible SSC pin configuration
•
Seven slave select inputs SLSI[7:1] in Slave Mode
•
Eight programmable slave select outputs SLSO[7:0] in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
•
SSC0 only: 8-stage Receive FIFO (RXFIFO) and 8-stage Transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 2- to 16-bit FIFO data width
– Programmable receive/transmit interrupt trigger level
– Receive and Transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation
