Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
4-2 Freescale Semiconductor
Execution Timing
instructions (which may have executed out of order) affect architected registers to ensure
the appearance of serial execution. This guarantees that the completed instruction and all
previous instructions can cause no exceptions. An instruction completes when it is retired,
that is, deleted from the CQ.
• Decode—The decode stage determines the issue queue to which each instruction is
dispatched (see Dispatch) and determines whether the required space is available in both
that issue queue and the completion queue. If space is available, it decodes instructions
supplied by the instruction queue, renames any source/target operands, and dispatches them
to the appropriate issue queues.
• Dispatch—Dispatch is the event at the end of the decode stage during which instructions
are passed to the issue queues and tracking of program order is passed to the completion
queue.
• Fetch—The process of bringing instructions from memory (such as a cache or system
memory) into the instruction queue.
• Finish—An executed instruction finishes by signaling the completion queue that execution
has concluded. An instruction is said to be finished (but not complete) when the execution
results have been saved in rename registers and made available to subsequent instructions,
but the completion unit has not yet updated the architected registers.
• Issue—The stage responsible for reading source operands from rename registers and
register files. This stage also assigns instructions to the proper execution unit.
• Latency— The number of clock cycles necessary to execute an instruction and make the
results of that execution available to subsequent instructions.
• Pipeline—In the context of instruction timing, this term refers to interconnected stages. The
events necessary to process an instruction are broken into several cycle-length tasks to
allow work to be performed on several instructions simultaneously—analogous to an
assembly line. As an instruction is processed, it passes from one stage to the next. When
work at one stage is done and the instruction passes to the next stage, another instruction
can begin work in the vacated stage.
Although an individual instruction may have multiple-cycle latency, pipelining makes it
possible to overlap processing so the number of instructions processed per clock cycle
(throughput) is greater than if pipelining were not implemented.
• Program order—The order of instructions in an executing program. More specifically, this
term is used to refer to the original order in which program instructions are fetched into the
instruction queue from the cache.
• Rename registers—Temporary buffers for holding results of instructions that have finished
execution but have not completed. The ability to forward results to rename registers allows
subsequent instructions to access the new values before they have been written back to the
architectural registers.