Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-19
Because the instruction cache never contains modified data, there is no need to flush the
instruction cache before it is invalidated.
The instruction cache can be invalidated by setting L1CSR1[ICFI]. The L1 caches can be flash
invalidated independently. The setting of L1CSR0[CFI] and L1CSR1[ICFI] must be preceded by
an msync and isync, respectively.
Both caches are invalidated automatically at power-up. Because a subsequent reset does not
invalidate caches automatically, software must set the CFI bits if invalidation is desired after a
warm reset. This causes a flash invalidation performed in a single CPU cycle, after which the CFI
bits are cleared automatically (CFI bits are not sticky). Note that flash invalidate operations are not
broadcast on the CCB.
Note that when an L2 tag parity error occurs on an attempt to write a new line, the L2 cache must
be flash invalidated. Performing a dcbi does not invalidate the line because it, like the write, is
treated as a cache miss, so the status of that line is not changed. L2 functionality is not guaranteed
if flash invalidation is not performed after a tag parity error.
Individual instruction or data cache blocks can be invalidated using icbi and dcbi, respectively.
Note that invalidating the caches resets all cache status bits, including lock bits. Also note that with
dcbi, the e500 core invalidates the cache block without pushing it out to memory. See
Section 3.3.1.8.1, “User-Level Cache Instructions .”
Exceptions and other events that can access the L1 cache should be disabled during this time so
that the PLRU algorithm can function undisturbed.
11.4.4 L1 Instruction and Data Cache Line Locking/Unlocking
User-mode instructions perform cache line locking/unlocking based on the complete address of
the cache line. dcblc, dcbtls, and dcbtstls are for data cache locking and unlocking and icblc and
icbtls are for instruction cache locking. For descriptions, see
Section 3.8.4, “Cache Locking
APU .”
The CT operand is used to indicate the cache target of the cache line locking instruction.
Lock instructions are treated as loads when translated by the data TLB, and they cause exceptions
when data TLB errors or data storage interrupts occur.
The user-mode cache lock enable bit, MSR[UCLE], is used to restrict user-mode cache line
locking by the operating system. If MSR[UCLE] = 0, any cache lock instruction executed in user
mode (MSR[PR] = 1) causes a cache-locking DSI exception and sets either ESR[DLK] or
ESR[ILK]. This allows the OS to manage and track the locking/unlocking of cache lines by
user-mode tasks. If MSR[UCLE] is set, the cache-locking instructions can be executed in user
mode and do not cause a DSI for cache locking. However, they may still cause a DSI for access
violations.