Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
1-30 Freescale Semiconductor
Core Complex Overview
1.10.4 Programmable Page Characteristics
Cache and memory attributes are programmable on a per-page basis. In addition to the
write-through, caching-inhibited, memory coherency enforced, and guarded characteristics
defined by the WIMG bits, Book E defines an endianness bit, E, that allows selection of big- or
little-endian byte ordering on a per-page basis.
In addition to the WIMGE bits, the Book E MMU model defines user-definable page attribute bits
(U0–U3).
1.11 Core Complex Bus (CCB)
The core complex defines a versatile local bus interface that allows a wide range of system
performance and system-complexity trade-offs. The interface defines the following buses.
• An address-out bus for mastering bus transactions
• An address-in bus for snooping internal resources
• Three tagged data buses
Two of the data buses are general-purpose data-in buses for reads, and the third is a data-out bus
for writes. The two data-in buses feature support for out-of-order read transactions from two
different sources simultaneously, and all three data buses may be operated concurrently. The
address-in bus supports snooping for external management of the L1 caches and TLBs by other
bus masters. The core complex broadcasts and snoops the cache and TLB management
instructions accordingly. It is envisioned that a wide range of system implementations can be
constructed from the defined interface.
1.12 Performance Monitoring
The e500 core provides a performance monitoring capability that allows counting of events such
as processor clocks, instruction cache misses, data cache misses, mispredicted branches, and
others. The count of these events may be configured to trigger a performance monitor exception
following the e500 interrupt model. This interrupt is assigned to vector offset register IVOR35.
The register set associated with the performance monitoring function consists of counter registers,
a global control register, and local control registers. These registers are read/write from supervisor
mode, and each register is reflected to a corresponding read-only register for user mode. Two
instructions, mtpmr and mfpmr, are provided for moving data to and from these registers. An
overview of the performance monitoring registers is provided in the following sections.