Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-25
4.4.1.3.4 BTB Special Cases—Phantom Branches and Multiple Matches
The following describes special cases:
• Phantom branches. BTB entries hold effective addresses associated with a branch
instruction. A process context switch might bring in another task whose MMU translations
are such that it uses the same effective address for another non-branch instruction for which
the BTB has an entry for a previously encountered branch. This causes the fetch unit to
redirect instruction fetch to the BTB’s target address. Later, during execution of the
instruction, the hardware realizes the error and evicts the BTB entry. However, locked BTB
entries are not evicted. Hardware guarantees correct execution under locked phantom
branches, but performance may suffer.
• Multiple matches. By ensuring that an entry is unique when it is allocated, the e500
hardware prevents multiple matches for the same fetch address.
4.4.2 Load/Store Unit Execution
The data cache supplies data to the GPRs by means of the LSU. The core complex LSU is directly
coupled to the data cache with a 64-bit (8-byte) interface to allow efficient movement of data to
and from the GPRs. The LSU provides all of the logic required to calculate effective addresses,
handles data alignment to and from the data cache, provides sequencing for load/store multiple
operations, and interfaces with the core interface unit. Write operations to the data cache can be
performed on a byte, half-word, word, or double-word basis.
When free of data dependencies, cacheable loads execute in the LSU in a speculative manner with
a maximum throughput of one per cycle and a total 3-cycle latency for integer loads. Data returned
from the cache on a load is held in a rename buffer until the completion logic commits the value
to the processor state.
4.4.2.1 Load/Store Unit Queueing Structures
This section describes the LSU queues that support the L1 data cache. See Section 11.3.5,
“Load/Store Operations ,” for more information on architectural coherency implications of
load/store operations and the LSU on the core complex. Also, see Section 4.4.4, “Load/Store
Execution ,” for more information on other aspects of the LSU and instruction scheduling
considerations.