Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
6-6 Freescale Semiconductor
Power Management
6.6 Interrupts and Power Management
In core-halted or core-stopped state, the core complex does not recognize interrupts. The power
management logic of the integrated device must monitor all external interrupt requests (as well as
the e500 tbint output) to detect interrupt requests. Upon sensing an interrupt request, the integrated
device ordinarily negates stop and halt to restore the core to full-on state, allowing it to service the
interrupt request.
MSR[WE], which gates the doze, nap, and sleep power management outputs from the core
complex, is always saved to save/restore register (SRR1, CSRR1, or MCSRR1, depending on the
interrupt) when an interrupt is taken and restored to the MSR when the handler issues an rfi, rfci,
or rfmci. As a result, doze, nap, and sleep outputs negate to the external power management logic
on entry to the interrupt service routine and then return to their previous state on return from the
interrupt when MSR[WE] value is restored. This function of MSR[WE] has the following
implications for the design of power management software:
• In previous devices, when the processor exits a low-power state, MSR[POW], which
enables power-down requests, is cleared without being automatically restored, unlike
Book E implementations which restore WE.
• Assuming that the system entered a low-power state in response to the assertion of doze,
nap, or sleep, the integrated device’s power management logic must recognize that these
outputs remain asserted for some time after the core complex is restored to full-on state (due
to the normal latency of restarting internal clock distribution and initiating the interrupt
request), and then negate as the interrupt is serviced.