Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Programming Examples
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor A-5
3. In some applications the second bc and/or the or can be omitted. The bc is needed only if
the application requires that if CR0[EQ] on exit indicates not equal then GPR4 and GPR6
are not equal. The or is needed only if the application requires that if the comparands are
not equal then the word from memory is loaded into the register with which it was
compared (rather than into a third register). If any of these instructions is omitted, the
resulting compare and swap does not obey System/370 semantics.
A.1.2 Lock Acquisition and Release
This example gives an algorithm for locking that demonstrates the use of synchronization with an
atomic read/modify/write operation. A shared memory location, the address of which is an
argument of the lock and unlock procedures given by GPR3, is used as a lock, to control access to
some shared resource such as a shared data structure. The lock is open when its value is 0 and
closed (locked) when its value is 1. Before accessing the shared resource the program executes the
lock procedure, which sets the lock by changing its value from 0 to 1. To do this, the lock
procedure calls test_and_set, which executes the code sequence shown in the test and set example
of
Section A.1.1, “Synchronization Primitives ,” thereby atomically loading the old value of the
lock, writing to the lock the new value (1) given in GPR4, returning the old value in GPR5 (not
used below), and setting the EQ bit of CR Field 0 according to whether the value loaded is 0. The
lock procedure repeats the test_and_set until it succeeds in changing the value of the lock from 0
to 1.
Because the shared resource must not be accessed until the lock has been set, the lock procedure
contains an isync after the bc that checks for the success of test_and_set. The isync delays all
subsequent instructions until all preceding instructions have completed.
lock: mfspr r6,LR #save Link Register
addi r4,r0,1 #obtain lock:
loop: bl test_and_set # test-and-set
bc 4,2,loop # retry till old = 0
# Delay subsequent instructions till prior instructions finish
isync
mtspr LR,r6 #restore Link Register
blr #return
The unlock procedure stores a 0 to the lock location. Most applications that use locking require,
for correctness, that if the access to the shared resource includes stores, the program must execute
an msync before releasing the lock. The msync ensures that the program’s modifications are
performed with respect to other processors before the store that releases the lock is performed with
respect to those processors. In this example, the unlock procedure begins with an msync for this
purpose.
unlock: msync #order prior stores
addi r1,r0,0 #before lock release
stw r1,0(r3) #store 0 to lock location
blr #return