Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
12-20 Freescale Semiconductor
Memory Management Units
Note that rA = 0 is the preferred form for tlbsx and that some Freescale implementations, such as
the e500, take an illegal instruction exception program interrupt if rA!=0.
The following RTL describes the e500 core complex tlbsx implementation:
if RA!=0 then generate illegal exception
EA =
32
0 || GPR(RB)
32:63
ProcessID = MAS6(SPID0), 0b0000_0000
AS = MAS6(SAS)
VA = AS || ProcessID || EA
if Valid_TLB_matching_entry_exists (VA)
then result = see Table 12-15 , column labelled “tlbsx hit”
else result = see Table 12-15 , column labelled “tlbsx miss”
MAS0, MAS1, MAS2, MAS3 = result
The tlbsx instruction searches both the TLB1 and TLB0 arrays using EPN[32–51] from the GPR
used as the instruction operand, and the SAS (search AS bit) and SPID0 (search PID) values from
MAS6. If the search results in a hit, the information for the TLB entry that hit is loaded into
MAS0–MAS3 and optionally, MAS7. The valid bit in MAS1 is used as the success flag as follows:
• If the search is successful, MAS1[V] is set.
• If the search is unsuccessful, MAS1[V] is cleared.
The tlbsx instruction is especially useful for finding the TLB entry that caused a DSI or ISI
exception. In this case, at most three tlbsx instructions are required: one for each of the current
PID values. Note that TID values of 0x00 always match with any PID value. Thus, if software only
uses one PID register, only one search is required.
12.4.4 TLB Invalidate (tlbivax) Instruction
The following RTL describes the e500 core complex tlbivax implementation:
if RA = 0, a = 0
else, a = GPR(RA)
EA = a + GPR(RB)
if (valid_TLB_matching_entry exists or INV_ALL) and Entry_IPROT_not_set
then invalidate entry
A TLB invalidate operation is performed whenever a tlbivax instruction is executed. This
instruction invalidates any TLB entry that corresponds to the virtual addresses calculated by this
instruction. This operation includes invalidating TLB entries contained in TLBs on other
processors and devices in addition to the processor executing the tlbivax instruction. Thus an
invalidate operation is broadcast throughout the coherent domain of the processor executing this
instruction.
Because the virtual address can be much larger than the physical address, the full virtual address
specified by the tlbivax instruction cannot be broadcast to all devices. Instead, a subset address is
broadcast that fits within the space of the implemented physical addressing model.