Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
3-6 Freescale Semiconductor
Instruction Model
Arithmetic and logical instructions do not read or modify memory. To use the contents of a
memory location in a computation and then modify the same or another location, the memory
contents must be loaded into a register, modified, and then written to the target location using load
and store instructions.
The description of each instruction includes the mnemonic and a formatted list of operands. To
simplify assembly language programming, a set of simplified mnemonics and symbols is provided
for some of the frequently used instructions; see
Appendix C, “Simplified Mnemonics for
PowerPC Instructions ,” for a complete list of simplified mnemonics. Programs written to be
portable across the various assemblers for the PowerPC architecture should not assume the
existence of mnemonics not described in that document.
3.2.1 Classes of Instructions
The e500 instructions belong to one of the following four classes:
• Defined instructions
• Allocated instructions
• Preserved instructions
• Reserved (illegal or no-op) instructions
These classes are defined in the “Instruction Model” chapter of the EREF. The class is determined
by examining the primary opcode and any extended opcode. If the opcode, or combination of
opcode and extended opcode, is not that of a defined, allocated, preserved, or reserved instruction,
the instruction is illegal.
3.2.2 Definition of Boundedly Undefined
If instructions are encoded with incorrectly set bits in reserved fields, the results on execution can
be said to be boundedly undefined. If a user-level program executes the incorrectly coded
instruction, the resulting undefined results are bounded in that a spurious change from user to
supervisor state is not allowed, and the level of privilege exercised by the program in relation to
memory access and other system resources cannot be exceeded. Boundedly undefined results for
a given instruction can vary between implementations and between execution attempts in the same
implementation.
3.2.3 Synchronization Requirements
This section discusses synchronization requirements for special registers and TLBs. The
synchronization described in this section refers to the state of the processor that is performing the
synchronization.