Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-21
Note that Book E provides this exception to assist implementations that cannot dynamically
switch byte ordering between consecutive accesses, do not support the byte order for a class of
accesses, or do not support misaligned accesses using a specific byte order.
When an instruction storage interrupt occurs, the processor suppresses execution of the instruction
causing the exception.
SRR0, SRR1, MSR, and ESR are updated as shown in Table 5-14 .
NOTE
Permissions violations and byte-ordering exceptions are not mutually
exclusive. Even if ESR[BO] is set, system software must examine the
TLB entry accessed by the fetch to determine whether a permissions
violation also may have occurred.
Instruction execution resumes at address IVPR[32–47]
||
IVOR3[48–59] || 0b0000.
5.7.5 External Input Interrupt
An external input interrupt occurs when no higher priority exception exists, an external input
exception is presented to the interrupt mechanism, and MSR[EE] = 1. The specific definition of
an external input exception is implementation-dependent and is typically caused by assertion of
an asynchronous signal that is part of the processing system. On the e500, this is the external
interrupt signal.
To guarantee that the core complex can take an external interrupt, the external interrupt pin must
be asserted until the interrupt is taken. Otherwise, whether the external interrupt is taken depends
on whether MSR[EE] is set when the external interrupt signal is asserted.
In addition to MSR[EE], implementations may provide other ways to mask this interrupt. The
e500 does not support additional masking mechanisms.
Table 5-14. Instruction Storage Interrupt Register Settings
Register Setting
SRR0 Set to the effective address of the instruction causing the instruction storage interrupt
SRR1 Set to the MSR contents at the time of the interrupt
MSR CE, ME, and DE are unchanged. All other MSR bits are cleared.
ESR BO is set if the instruction fetch caused a byte-ordering exception; otherwise cleared.
All other defined ESR bits are cleared.