Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 345 / 548

Auxiliary Processing Units (APUs)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 10-9
efdcfsf efdcfsf
Convert Floating-Point Double-Precision from Signed Fraction
efdcfsf rD,rB
rD
0:63
←
CnvtI32ToFP64(rB
32:63
, SIGN, F)
The signed fractional low element in rB is converted to a double-precision floating-point value
using the current rounding mode and the result is placed into rD.
Exceptions: None
efdcfsi efdcfsi
Convert Floating-Point Double-Precision from Signed Integer
efdcfsi rD,rB
rD
0:63
←
CnvtSI32ToFP64(rB
32:63
, SIGN, I)
The signed integer low element in rB is converted to a double-precision floating-point value using
the current rounding mode and the result is placed into rD.
Exceptions: None
efdcfuf efdcfuf
Convert Floating-Point Double-Precision from Unsigned Fraction
efdcfuf rD,rB
rD
0:63
←
CnvtI32ToFP64(rB
32:63
, UNSIGN, F)
The unsigned fractional low element in rB is converted to a double-precision floating-point value
using the current rounding mode and the result is placed into rD.
Exceptions: None
0 5 6 10 11 15 16 20 21 31
0 0 0 1 0 0 r D 0 0 0 0 0 r B 0 1 0 1 1 1 1 0 0 1 1
0 5 6 10 11 15 16 20 21 31
0 0 0 1 0 0 r D 0 0 0 0 0 r B 0 1 0 1 1 1 1 0 0 0 1
0 5 6 10 11 15 16 20 21 31
0 0 0 1 0 0 r D 0 0 0 0 0 r B 0 1 0 1 1 1 1 0 0 1 0