Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-33
When an embedded floating-point round interrupt occurs, the unrounded (truncated) result is
placed in the target register.
Table 5-31 describes register settings.
Instruction execution resumes at address IVPR[32–47] || IVOR34[48–59] || 0b0000.
5.8 Performance Monitor Interrupt
The performance monitor provides a performance monitor interrupt that is triggered by an enabled
condition or event. An enabled condition or event is as follows:
A PMCn register overflow condition occurs with the following settings:
• PMLCan[CE] = 1; that is, for the given counter the overflow condition is enabled.
• PMCn[OV] = 1; that is, the given counter indicates an overflow.
For a performance monitor interrupt to be signaled on an enabled condition or event,
PMGC0[PMIE] must be set.
The performance monitor can also freeze the performance monitor counters triggered by an
enabled condition or event. For the performance monitor counters to freeze on an enabled
condition or event, PMGC0[FCECE] must be set.
Although the interrupt condition could occur with MSR[EE] = 0, the interrupt cannot be taken
until MSR[EE] = 1. If a counter overflows while PMGC0[FCECE] = 0, PMLCan[CE] = 1, and
MSR[EE] = 0, it is possible for the counter to wrap around to all zeros again without the
performance monitor interrupt being taken.
The priority of the performance monitor interrupt is below that of the fixed-interval interrupt and
above that of the decrementer interrupt.
The APUs chapter of the EREF describes Book E and EIS aspects of the debug interrupt.
5.9 Partially Executed Instructions
In general, the PowerPC architecture permits load and store instructions to be partially executed,
interrupted, and then restarted from the beginning upon return from the interrupt. To guarantee that
a particular load or store instruction completes without being interrupted and restarted, software
Table 5-31. Embedded Floating-Point Round Interrupt Register Settings
Register Setting
SRR0 Set to the effective address of the instruction following the instruction causing the interrupt.
SRR1 Set to the MSR contents at the time of the interrupt.
MSR CE, ME, and DE are unchanged. All other MSR bits are cleared.
ESR SPE (bit 24) is set. All other ESR bits are cleared.
SPEFSCR FGH, FXH, FG, FX, and FRMC are set appropriately to indicate the interrupt type.