Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
12-24 Freescale Semiconductor
Memory Management Units
12.5.2 TLB Interrupt Routines
When an exception is reported by the MMUs, the machine drains (that is, all instructions
dispatched prior to the exception are executed). After all instructions are completed, the interrupt
is acknowledged and MAS0–MAS2 are loaded as described in
Section 12.5.1, “Automatic
Updates—TLB Miss Exceptions .”
As is recommended for most interrupt handler routines, the TLB miss, DSI, and ISI exception
handlers must first save the values of enough GPRs so that the handler has enough GPRs available
for its own use. The handler should then perform an mfcr to copy the CR data into one of the
GPRs. Before exiting the handler, an mtcrf must be executed to restore the CR, and then the
original GPR data must be restored.
The PID0–2 registers must also be restored (if modified) before exiting the handler. Note that PID
register updates must be followed by an isync. This isync instruction must reside in an instruction
page that is valid before the changes are made to the PID.
12.5.2.1 Permissions Violations (ISI, DSI) Interrupt Handlers
The only differences between the definition of actions on a permissions violation for Freescale
Book E devices and for the e500 is that the e500 only uses MAS6[SPID0] and the e500 does not
implement MAS5. Note that for a permissions violation case, software must explicitly load a value
into MAS6[SPID0] (this value will most likely be the value of PID0).
The permissions violations handlers can use the tlbsx instruction to load all necessary information
about the faulting access into the MAS registers and make the appropriate changes. If the access
was an instruction or data access, the handler can load the following effective address into rB in
order to load the faulting TLB entry into the MAS registers:
• Instruction access: load SRR0 value into rB
• Data access: load DEAR value into rB
See Section 12.4.3, “TLB Search (tlbsx) Instruction—Searching the TLB1 and TLB0 Arrays ,” for
more information about the actions performed by the tlbsx instruction.
The guidelines for the saving and restoring of resources for permissions violations interrupt
handlers are the same as that for TLB error interrupts.
12.6 TLB States after Reset
During reset, all TLB entries in the L1 and L2 MMUs are flash invalidated. Then entry 0 of TLB1
is loaded with the values shown in
Table 12-6 . Note that only the valid bits for other TLB entries
are cleared. Other fields of TLB entries are set not set to a known state and software should be
careful to insure that all fields of a TLB entry are appropriately initialized through the MAS
registers before it is used for translation.