Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
1-18 Freescale Semiconductor
Core Complex Overview
• The execute stage accepts instructions from its issue queue when the appropriate
reservation stations are not busy. In this stage, the operands assigned to the execution stage
from the issue stage are latched.
The execution unit executes the instruction (perhaps over multiple cycles), writes results on
its result bus, and notifies the CQ when the instruction finishes. The execution unit reports
any exceptions to the completion stage. Instruction-generated exceptions are not taken until
the excepting instruction is next to retire.
Most integer instructions have a 1-cycle latency, so results of these instructions are
available 1 clock cycle after an instruction enters the execution unit. The MU and LSU are
pipelined, as shown in
Figure 1-5 .
Branches resolve in execute stage. If a branch is mispredicted, it takes 5 cycles for the next
instruction to reach the execute stage.
• The complete and write-back stages maintain the correct architectural machine state and
commit results to the architecture-defined registers in the proper order. If completion logic
detects an instruction containing an exception status or a mispredicted branch, all following
instructions are cancelled, their execution results in rename registers are discarded, and the
correct instruction stream is fetched.
The complete stage ends when the instruction is retired. Two instructions can be retired per
clock cycle. If no dependencies exist, as many as two instructions are retired in program
order.
Section 4.7.4, “Completion Unit Resource Requirements ,” describes completion
dependencies.
The write-back stage occurs in the clock cycle after the instruction is retired.
The e500 core also provides new instructions that perform single-instruction, multiple-data (SIMD)
operations. These signal processing instructions consist of parallel operations on both the upper and
lower 32 bits of two 64-bit GPR values and produce two 32-bit results written to a 64-bit GPR.
As shown in Figure 1-5 , the LSU, MU, and SU1 replicate logic to support 64-bit operations.
Although a vector instruction generates separate, discrete results in the upper and lower halves of
the target GPR, latency and throughput for vector instructions are the same as those for their scalar
equivalents.
1.6 Programming Model
The following section describes the e500 core registers defined in Book E, the Freescale
Semiconductor Book E implementation standards (EIS), and registers that are specific to the e500.
Figure 1-7 shows the e500 register set.