Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-23
• Automatic loading into SRR0 of the effective address of the instruction that causes a TLB
miss exception or a permissions violation.
• Automatic updates of the next victim (NV) field and MAS0[ESEL] fields for TLB0 entry
replacement on TLB misses (TLB error interrupts); this occurs if TLBSELD = 00. See
Section 12.3.2.2, “Replacement Algorithms for L2 MMU .”
• When tlbwe is executed, the information for the selected victim is read from the selected
L2 TLB (TLB1 or TLB0). The victim’s EPN and TS are sent to both L1 MMUs to provide
back-invalidation. Thus if the selected victim in the L2 MMU is also resident in an L1
MMU, it is invalidated (or victimized) in the L1 MMU. This forces inclusion in the TLB
hierarchy. Additionally, the new TLB entry contained in MAS0–MAS3 (and MAS7 on the
e500v2) is written into the selected TLB.
Note that while the tlbwe instruction loads an entry in the L2 TLB array, it does not load an entry
in the L1 TLB array. The L1 arrays are loaded with new entries (automatically by the hardware)
only when an access misses in the L1 array, but hits in a corresponding L2 array.
See Section 12.7.2, “MAS Register Updates ,” for a complete description of automatic fields loaded
into the MAS registers on execution of TLB instructions and for various exception conditions.
The EREF provides more information on some of the actions taken by Freescale Book E devices
on MMU exceptions.
The following subsections provide supplementary information that applies for the e500.
12.5.1 Automatic Updates—TLB Miss Exceptions
When a TLB miss exception occurs, MAS0–MAS2 are automatically updated using the defaults
specified in MAS4, as well as the AS and EPN[32–51] values corresponding to the access that
caused the exception, as described in
Section 12.7.2, “MAS Register Updates .”
In addition, if TLBSELD = 00 (selecting TLB0), MAS0[ESEL] is updated with the next victim
information for TLB0. Finally, the MAS0[NV] field is updated with the incremented value of
TLB0[NV]. Thus, ESEL points to the current victim (the entry to be replaced), while MAS0[NV]
points to the next victim to be used if a TLB0 entry is replaced. See
Section 12.3.2.2,
“Replacement Algorithms for L2 MMU ,” for more information.
The process described above sets up all the TLB entry data necessary for a TLB write except for
RPN[32–51] and RPN[28–31], the U0–U3 user attribute bits, and the UX, SX, UW, SW, UR, and
SR permission bits for the new entry, all of which are stored in MAS3 (and MAS7). Thus, if the
defaults stored in MAS4 are applicable to the TLB entry to be loaded, the TLB miss exception
handler only has to update MAS3 (and MAS7) with an mtspr before executing tlbwe. If the
defaults are not applicable to the TLB entry being loaded, then the TLB miss exception handler
must update MAS0–MAS2 appropriately before performing the TLB write. See
Section 12.5.2,
“TLB Interrupt Routines ,” for more information on the handling of TLB miss exceptions.