Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor A-1
Appendix A
Programming Examples
This appendix gives examples of how memory synchronization instructions can be used to
emulate various synchronization primitives and to provide more complex forms of
synchronization. It also describes multiple-precision shifts.
A.1 Synchronization
Examples in this appendix have a common form. After possible initialization, a conditional
sequence begins with a load and reserve instruction that may be followed by memory accesses and
computations that include neither a load and reserve nor a store conditional. The sequence ends
with a store conditional with the same target address as the initial load and reserve. In most of the
examples, failure of the store conditional causes a branch back to the load and reserve for a
repeated attempt. On the assumption that contention is low, the conditional branch in the examples
is optimized for the case in which the store conditional succeeds, by setting the branch-prediction
bit appropriately. These examples focus on techniques for the correct modification of shared
storage locations: see note 4 in
Section A.1.3.1, “Notes ,” for a discussion of how the retry strategy
can affect performance.
Load and reserve and store conditional instructions depend on the coherence mechanism of the
system. Stores to a given location are coherent if they are serialized in some order, and no
processor is able to observe a subset of those stores as occurring in a conflicting order. The
“Memory and Cache Background” chapter of the EREF provides details about memory access
ordering.
Each load operation, whether ordinary or load and reserve, returns a value that has a well-defined
source. The source can be the store or store conditional instruction that wrote the value, an
operation by some other mechanism that accesses storage (for example, an I/O device), or the
initial state of storage.
The function of an atomic read/modify/write operation is to read a location and write its next value,
possibly as a function of its current value, all as a single atomic operation. We assume that
locations accessed by read/modify/write operations are accessed coherently, so the concept of a
value being the next in the sequence of values for a location is well defined. The conditional
sequence, as defined above, provides the effect of an atomic read/modify/write operation, but not
with a single atomic instruction. Let addr be the location that is the common target of the load and
reserve and store conditional instructions. Then the guarantee the architecture makes for the