Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-1
Chapter 5
Interrupts and Exceptions
This chapter provides a general description of the PowerPC Book E interrupt and exception model
as it is implemented in the e500 core complex. It identifies and describes the portions of the
interrupt model that are defined by the Book E architecture and by the Freescale implementation
standards (EIS).
5.1 Overview
A note on terminology:
The Book E architecture has defined additional resources for interrupt handling. As a result, the
terms ‘interrupt’ and ‘exception’ differ somewhat from their use in previous Freescale
documentation, such as the Programming Environments Manual. Use of these terms in this
document are as follows:
• An interrupt is the action in which the processor saves its context (typically the machine
state register (MSR) and next instruction address) and begins execution at a predetermined
interrupt handler address with a modified MSR.
• An exception is the event that, if enabled, causes the processor to take an interrupt. Book E
describes exceptions as being generated by signals from internal and external peripherals,
instructions, the internal timer facility, debug events, or error conditions.
There are three categories of interrupts, described as follows:
• Noncritical interrupts—First-level interrupts that let the processor change program flow to
handle conditions generated by external signals, errors, or unusual conditions arising from
program execution, or from programmable timer-related events.
These interrupts are largely identical to those defined by the OEA portion of the PowerPC
architecture. They use save and restore registers (SRR0/SRR1) to save state when they are
taken, and they use the rfi instruction to restore state. Asynchronous noncritical interrupts
can be masked by the external interrupt enable bit, MSR[EE].
• Critical interrupts—Critical interrupts (critical input, watchdog timer, and debug interrupts)
can be taken during a noncritical interrupt or during regular program flow. They use the
critical save and restore registers (CSRR0/CSRR1) to save state when they are taken, and
they use the rfci instruction to restore state.
Critical input and watchdog timer critical interrupts can be masked by the critical enable
bit, MSR[CE]. Debug events can be masked by the debug enable bit MSR[DE]. Book E