Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-5
Figure 12-2 shows the same translation flow for the e500v2 core.
Figure 12-2. Effective-to-Real Address Translation Flow (e500v2)
12.2.1 Virtual Addresses with Three PID Registers
As shown in Figure 12-1 and Figure 12-2 , the address translation process starts with an effective
address that is prepended with an address space (AS) value and a process ID to construct a virtual
address (VA). A virtual address is then translated into a real address based on the translation
information found in the on-chip TLB of the appropriate L1 MMU. The AS bit for the access is
selected from the value of MSR[IS] or MSR[DS] for instruction or data accesses, respectively.
The e500 constructs three virtual addresses for each access. The core complex implements three
process ID (PID) registers, PID0–PID2, as SPRs shown in
Section 2.12.1, “Process ID Registers
(PID0–PID2) .” All of the current values in the PID registers are used in the TLB look-up process
and compared with the TID field in all the TLBs. If any of the PID values in PID0–PID2 matches
with a TLB entry in which all the other match criteria are met, that entry is used for translation.
Effective Page Number Byte Address
Real Page Number Byte Address
32-bit Effective Address (EA)
36-bit Real Address
0–20 bits*
4–24 bits* 12–32 bits*
L2 MMU (unified)
Three 41-bit Virtual Addresses (VAs)
8 bits
MSR
••• IS DS •••
Instruction Access
Data Access
AS
PID0
PID1
PID2
L1 MMUs
Instruction L1 MMU Data L1 MMU
2 TLBs 2 TLBs
* Number of bits depends on page size
(4 Kbytes–4 Gbytes)
16-Entry Fully-Assoc. VSP Array (TLB1)
512-Entry 4-Way Set Assoc. Array (TLB0)
12–32 bits*