Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
8-14 Freescale Semiconductor
Debug Support
If DE is zero (either at the time of the execution of the rfi or after the MSR is updated by the rfi)
at the time of the return debug exception, a debug interrupt does not occur.
Provided the debug exception has not been reset by clearing DBSR[RET], a delayed imprecise
debug interrupt occurs when MSR[DE] is set. In this case, CSRR0 contains the address of the
instruction following the one that set MSR[DE]. The interrupt handler can observe DBSR[IDE] to
determine how to interpret the value in CSRR0 unless MSR[DE] was cleared by the rfi. In that
case, DBSR[IDE] has not been set and the software cannot determine that the interrupt was
precise.
8.4.8 Unconditional Debug Event
An unconditional debug event occurs when the debug mechanism asserts the ude signal. The exact
definition of ude and how it is activated are implementation dependent. See the reference manual
for the device that implements the e500 core for details. An unconditional debug event can occur
regardless of the value of MSR[DE] and is the only debug event that does not have a corresponding
debug control register enable bit.
If MSR[DE] is set, an unconditional debug event causes the following:
• A debug interrupt is taken immediately, if no higher priority exception caused an interrupt.
• CSRR0 is loaded with the address of the instruction that would have executed next had the
interrupt not occurred.
When an unconditional debug event occurs, DBSR[UDE] is set to record the exception. If the
event occurs while debug interrupts are disabled, DBSR[IDE] is set and the interrupt is delayed
until MSR[DE] is set, provided the exception has not been cleared from the DBSR in the
meantime. IDE indicates whether the associated DBSR exception bit was set while debug
interrupts were disabled. Debug interrupt handler software can use this bit to determine whether
the address recorded in CSRR0 should be interpreted as the address associated with the instruction
causing the debug exception or is simply the address of the instruction after the one that set
MSR[DE], thereby enabling the delayed debug interrupt.