Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-5
The e500v2 implements an extra status bit in each LFB entry, indicating whether data in the entry
is bad (due to address errors, data bus errors or faults, or data bus parity). Any load that hits in an
entry marked bad does not finish. Therefore, completion eventually stalls on the unfinished load
until an interrupt occurs. (Under normal operation, this generates an interrupt from the system
logic; however, if HID0[RFXE] = 1 (and MSR[ME] = 1), a machine check interrupt is generated.)
11.1.1.1.5 Data Write Buffer (DWB)
When a full line of data is available in the DLFB, the data cache is updated. If a data cache update
requires that a line currently in the cache be evicted, that line is cast out and placed in the data write
buffer (DWB) until the data has been transferred through the core interface unit to the CCB. If
global memory’s coherency needs to be maintained, as a result of bus snooping, the L1 cache can
also evict a line to the DWB. This write is called a snoop push operation. Note that all cast-out and
snoop push writes from the L1 cache are cache-line aligned (critical word is not written first). This
is independent of which word in a modified cache line is accessed.
There are three DWB entries: one for snoop pushes, one for castouts, and one that can be used for
either.
11.1.1.2 Instruction Unit
The instruction unit interfaces with the L1 instruction cache and the core interface unit. When
instructions miss in the instruction cache they are accumulated in the two-entry instruction line fill
buffer (ILFB) as they are fetched. After an entire line is available, it is written into the instruction
cache and the ILFB is emptied.
The e500v2 implements an extra status bit in each LFB entry, indicating whether data in the entry
is bad (due to address errors, data bus errors or faults, or data bus parity). Any load that hits in an
entry marked bad does not finish. Therefore, completion eventually stalls on the unfinished load
until an interrupt occurs. (Under normal operation, this generates an interrupt from the system
logic; however, if HID0[RFXE] = 1 (and MSR[ME] = 1), a machine check interrupt is generated.)
11.1.1.3 Core Interface Unit
The core interface unit handles all bus transactions initiated by the ILFB, DLFB, and DWB. The
core interface unit handles all ordering and bus protocol and is the interface between the core
complex and the external memory and caches.
The core interface unit performs transactions through the CCB by transferring either the critical
double word first (8 bytes) or the critical quad word first (16 bytes). It then forwards the
transaction to the instruction or data line fill buffer critical double word first. The CCB also
captures snoop addresses for the L1 data cache and the memory reservation (lwarx and stwcx.)
operations.