PowerPC e500 Core Family Reference Manual, Rev. 1
11-8
Freescale Semiconductor
L1 Caches
The instruction cache differs from the data cache in that it does not implement a multiple-state
cache coherency protocol. A single status bit indicates whether a cache block is valid or invalid
and there is a single bit for locking.
NOTE
On the e500v1, it is possible for multiple entries in the L1 instruction
cache to contain data for the same physical memory location. This
error can occur when two different effective addresses (EA) map to
the same physical address and accesses to these two EAs occur within
the same context and relatively close together in time.
This is avoided by not fetching instructions from one physical address
through two or more different EAs within any given context.
11.2.3 L1 Cache Parity
The L1 caches are protected by parity. Parity information is written into the L1 caches whenever
one of the following occurs:
•
A store instruction (or dcbz or dcba) modifies the data cache
•
A line fill occurs into the instruction or data cache
L1 cache parity is checked whenever:
•
A load instruction hits in the L1 data cache
•
An instruction fetch hits in the L1 instruction cache
•
A line is cast out of the L1 data cache
L1 cache parity checking is disabled by default, and can be enabled by setting L1CSR0[CPE] and
L1CSR1[ICPE].
The CCB is also protected by parity. Parity is checked whenever data is read on either of the two
CCB read buses; a machine check is generated if errors occur. Additionally, parity is generated
whenever data is written on the CCB write bus, giving the SoC platform an opportunity to identify
and report errors when data is cast out of the cache or written with a cache-inhibited or
write-through store. Parity checking on the CCB read buses is disabled by default and can be
enabled by setting HID1[R1DPE] and HID1[R2DPE].
If a cache parity error is detected, a machine check interrupt occurs (as described in
Section 5.7.2,
“Machine Check Interrupt
”).
Summary of Contents for PowerPC e500 Core
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