Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor
3-59
The embedded floating-point APUs are described as follows:
•
Vector SPFP instructions operate on a vector of two 32-bit, single-precision floating-point
numbers that reside in the upper and lower halves of the 64-bit GPRs.
•
Scalar SPFP instructions operate on single 32-bit operands that reside in the lower 32-bits
of the GPRs.
•
Scalar DPFP instructions (e500v2 only) operate on single 64-bit operands that reside in the
64-bit GPRs. Full descriptions of these instructions is provided in
Section 10.4,
“Double-Precision Floating-Point APU (e500 v2 Only)
.”
These instructions are listed in
Table 3-37
.
NOTE
Vector and scalar versions of the instructions have the same syntax.
Table 3-37. Vector and Scalar Floating-Point APU Instructions
Instruction
Single-Precision
Scalar
Double-Precision
Scalar (e500v2)
Vector
Syntax
Convert Floating-Point Double- from Single-Precision
—
efdcfs
—
r
D
,r
B
Convert Floating-Point from Signed Fraction
efscfsf efdcfsf
evfscfsf
r
D
,r
B
Convert Floating-Point from Signed Integer
efscfsi efdcfsi
evfscfsi
r
D
,r
B
Convert Floating-Point from Unsigned Fraction
efscfuf
efdcfuf
evfscfuf
r
D
,r
B
Convert Floating-Point from Unsigned Integer
efscfui efdcfui
evfscfui
r
D
,r
B
Convert Floating-Point Single- from Double-Precision
—
efscfd
—
r
D
,r
B
Convert Floating-Point to Signed Fraction
efsctsf
efdctsf
evfsctsf
r
D
,r
B
Convert Floating-Point to Signed Integer
efsctsi
efdctsi
evfsctsi
r
D
,r
B
Convert Floating-Point to Signed Integer with Round toward
Zero
efsctsiz
efdctsiz
evfsctsiz
r
D
,r
B
Convert Floating-Point to Unsigned Fraction
efsctuf
efdctuf
evfsctuf
r
D
,r
B
Convert Floating-Point to Unsigned Integer
efsctui
efdctui
evfsctui
r
D
,r
B
Convert Floating-Point to Unsigned Integer with Round
toward Zero
efsctuiz
efdctuiz
evfsctuiz
r
D
,r
B
Floating-Point Absolute Value
efsabs
1
efdabs evfsabs
r
D
,r
A
Floating-Point Add
efsadd efdadd
evfsadd
r
D
,r
A
,r
B
Floating-Point Compare Equal
efscmpeq efdcmpeq
evfscmpeq
cr
D
,r
A
,r
B
Floating-Point Compare Greater Than
efscmpgt efdcmpgt
evfscmpgt
cr
D
,r
A
,r
B
Floating-Point Compare Less Than
efscmplt efdcmplt
evfscmplt
cr
D
,r
A
,r
B
Floating-Point Divide
efsdiv efddiv
evfsdiv
r
D
,r
A
,r
B
Floating-Point Multiply
efsmul
efdmul
evfsmul
r
D
,r
A
,r
B
Floating-Point Negate
efsneg
1
efdneg evfsneg
r
D
,r
A
Floating-Point Negative Absolute Value
efsnabs
1
efdnabs
evfsnabs
r
D
,r
A
Floating-Point Subtract
efssub
efdsub
evfssub
r
D
,r
A
,r
B
Summary of Contents for PowerPC e500 Core
Page 1: ...PowerPC e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev 1 4 2005...
Page 36: ...PowerPC e500 Core Family Reference Manual Rev 1 xxxvi Freescale Semiconductor...
Page 38: ...PowerPC e500 Core Family Reference Manual Rev 1 Part I 2 Freescale Semiconductor...
Page 332: ...PowerPC e500 Core Family Reference Manual Rev 1 Part II 2 Freescale Semiconductor...
Page 530: ...Opcode Listings PowerPC e500 Core Family Reference Manual Rev 1 D 50 Freescale Semiconductor...
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