Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
5-36 Freescale Semiconductor
Interrupts and Exceptions
5.10.1 Guidelines for System Software
Table 5-32 lists actions system software must avoid before saving save/restore register contents.
It is unnecessary for hardware or software to avoid critical-class interrupts from within
noncritical-class interrupt handlers (hence hardware does not automatically clear
MSR[CE,ME,DE] on a noncritical interrupt), since the two interrupt classes use different
save/restore registers. However, because a critical-class interrupt can occur within a noncritical
handler before the noncritical handler saves SRR0/SRR1, hardware and software must cooperate
to avoid both critical and noncritical-class interrupts from within critical class-interrupt handlers.
Therefore, within the critical-class interrupt handler, both pairs of save/restore registers may
contain data necessary to system software.
Table 5-32. Operations to Avoid
Operation Reason
Reenabling MSR[EE] (or MSR[CE,DE] in critical
class interrupt handlers) Prevents any asynchronous interrupts, as well as (in the case of MSR[DE])
any debug interrupts, including synchronous and asynchronous types
Branching (or sequential execution) to addresses
not mapped by the TLB, mapped without UX = 1 or
SX = 1 permission, or causing large address or
instruction address overflow exceptions. Prevents instruction storage, instruction TLB error, and instruction address
overflow interrupts
Load, store, or cache management instructions to
addresses not mapped by the TLB or not having
required access permissions. Prevents data storage and data TLB error interrupts
Execution of System Call ( sc ) or trap ( tw , twi , td ,
tdi ) instructions
Prevents system call and trap exception-type program interrupts
Reenabling of MSR[PR] Prevents privileged instruction exception-type program interrupts.
Alternatively, software could reenable MSR[PR] but avoid executing any
privileged instructions.
Execution of any illegal instructions Prevents illegal instruction exception-type program interrupts
Execution of any instruction that could cause an
alignment interrupt Prevents alignment interrupts, including string or multiple instructions and
misaligned elementary load or store instructions.
Section 5.7.6, “Alignment
Interrupt ,” lists instructions that cause alignment interrupts.