Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
3-46 Freescale Semiconductor
Instruction Model
The following example uses the ‘Fetch and Add’ primitive (see the section entitled ‘Synchronization
Primitives’ in Section I) to obtain and increment the pointer.
In this example it is assumed that the address of the pointer is in GPR 3, the value to be added to the pointer
is in GPR 4, and the old value of the pointer is returned in GPR 5.
loop: lwarx r5,0,r3 # load pointer and reserve
add r0,r4,r5 # increment the pointer
stwcx. r0,0,r3 # try to store new value
bc 4,2,loop # loop if lost reservation
lwz r7,data1(r5) # load shared data
The load from data1 cannot be performed until the pointer value has been loaded into GPR 5 by the lwarx.
The load from data1 may be performed out-of-order before the stwcx.. But if the stwcx. fails, the branch
is taken and the value returned by the load from data1 is discarded. If the stwcx. succeeds, the value
returned by the load from data1 is valid even if the load is performed out-of-order, because the load uses
the pointer value returned by the instance of the lwarx that created the reservation used by the successful
stwcx..
An isync could be placed between the bne- and the subsequent lwz, but no isync is needed if all accesses
to the shared data structure depend on the value returned by the lwarx.
3.5.1.3 Lock Release and Export Barriers
An export barrier is an instruction or sequence of instructions that prevents the store that releases a lock
from being performed before stores caused by instructions preceding the barrier have been performed. An
export barrier can be used to ensure that all stores to a shared data structure protected by a lock be
performed with respect to any other processor (to the extent required by the associated memory coherence
required attributes) before the store that releases the lock is performed with respect to that processor.
3.5.1.3.1 Export Shared Memory and Release Lock
An msync instruction can always be used as an export barrier, independent of the memory control
attributes (for example, presence or absence of the caching inhibited attribute) of the memory containing
the lock and the shared data structure. Unless both the lock and the shared data structure are in memory
that is neither caching inhibited nor write-through required, an msync instruction must be used as the
export barrier.
In this example it is assumed that the lock is in memory that is caching inhibited, the shared data structure
is in memory that is not caching inhibited, the address of the lock is in GPR 3, the value indicating that the
lock is free is in GPR 4, and the address of the shared data structure is in GPR 9.
stw r7,data1(r9) # store shared data (last)
msync # export barrier
stw r4,lock(r3) # release lock
The msync ensures that the store that releases the lock are not performed with respect to any other
processor until all stores caused by instructions preceding the msync have been performed with respect to
that processor.