Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-9
5.5 Interrupt Classes
All interrupts except machine check are categorized by two independent characteristics:
• Critical/noncritical. Some interrupt types demand immediate attention even if other
interrupt types being processed have not had the opportunity to save the machine state (that
is, return address and captured state of the MSR). To enable taking a critical interrupt
immediately after a noncritical interrupt is taken (that is, before the machine state is saved),
two sets of save/restore register pairs are provided. Critical interrupts use CSRR0/CSRR1,
and noncritical interrupts use SRR0/SRR1.
• Asynchronous/synchronous. Asynchronous interrupts are caused by events external to
instruction execution; synchronous interrupts are caused by instruction execution and are
either precise or imprecise.
Table 5-5 describes asynchronous and synchronous interrupts.
Table 5-5. Asynchronous and Synchronous Interrupts
Class Description
Asynchronous Caused by events independent from instruction execution. For asynchronous interrupts, the address reported to
the interrupt handling routine is the address of the instruction that would have executed next, had the
asynchronous interrupt not occurred.
Synchronous,
Precise
Caused directly by instruction execution. Synchronous interrupts are precise or imprecise.
These interrupts precisely indicate the address of the instruction causing the exception or, for certain
synchronous, precise interrupt types, the address of the immediately following instruction. When the execution
or attempted execution of an instruction causes a synchronous, precise interrupt, the following conditions exist
at the interrupt point:
• Whether SRR0 or CSRR0 addresses the instruction causing the exception or the next instruction is
determined by the interrupt type and status bits.
• An interrupt is generated such that all instructions before the instruction causing the exception appear to have
completed with respect to the executing processor. However, some accesses associated with these preceding
instructions may not have been performed with respect to other processors and mechanisms.
• The exception-causing instruction may appear not to have begun execution (except for causing the exception),
may be partially executed, or may have completed, depending on the interrupt type. See Section 5.9, “Partially
Executed Instructions .”
• Architecturally, no instruction beyond the exception-causing instruction executed.