Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-45
4.7.1 Fetch/Branch Considerations
The following lists the resources required to avoid stalling the fetch unit in the course of branch
resolution:
• The bclr instruction requires LR availability for resolution.
• The branch conditional on counter decrement and the CR condition requires CTR
availability or the CR condition must be false.
4.7.1.1 Dynamic Prediction versus No Branch Prediction
No branch prediction (BUCSR[BPEN] = 0) means that the e500 predicts every branch as not
taken. The dynamic predictor is ignored. Sometimes this simplistic prediction is superior, either
through informed guessing or through available profile-directed feedback. Run time for code with
no prediction is more nearly deterministic, which can be useful in embedded systems.
Note that disabling and enabling the BTB (by clearing and setting BPEN) do not affect the BTB’s
contents or locks.
4.7.1.1.1 Position-Independent Code
Position-independent code is used when not all addresses are known at compile time or link time.
Because performance is typically not good, position-independent code should be avoided when
possible.
4.7.2 Dispatch Unit Resource Requirements
The following is a general list of the most common reasons that instructions may stall in the
dispatch unit:
• Presync serializing instructions cannot decode until all previous instructions have completed.
• Postsync serializing instructions inhibit the decoding of any further instructions until they
have completed.
• Decode stalls if there is no room in the CQ for two instructions, regardless of how many are
eligible for decode.
• When an unconditional branch misses in the BTB, the decoder stalls any further decode
until it receives an indication that the unconditional branch executed and redirected fetch.
• A branch-class instruction cannot be decoded if there is no room in the BIQ. Although
mtctr and mtlr do not go to the BIQ, they are also affected by this stall.
• The decode stage cannot decode a second branch-class instruction in a single cycle. This
applies only to IQ1.
• Decoding stops if there are no free entries in the GIQ, even if the next instruction to decode
is to the BU or does not require an issues queue slot.