PowerPC e500 Core Family Reference Manual, Rev. 1
8-8
Freescale Semiconductor
Debug Support
8.4.1.2
Effective Address Mode
The debug control registers specify effective address modes as follows:
•
DBCR1[IAC1ER] specifies whether effective addresses alone, effective addresses and
MSR[IS] cleared, or effective addresses and MSR[IS] set are used in determining an
address match on IAC1 debug events.
•
DBCR1[IAC2ER] specifies whether effective addresses alone, effective addresses and
MSR[IS] cleared, or effective addresses and MSR[IS] set are used in determining an
address match on IAC2 debug events.
8.4.1.3
Instruction Address Compare Mode
The debug control registers specify instruction address compare modes as follows:
•
DBCR1[IAC12M] specifies the following:
— Whether all or some of the bits of the address of the instruction fetch must match the
contents of IAC1 or IAC2
— Whether the address must be inside or outside of a specific range specified by IAC1 and
IAC2 to trigger a corresponding debug event.
The four instruction address compare modes are described in
Table 8-7
.
Section 2.13.1, “Debug Control Registers (DBCR0–DBCR2)
,” describes DBCR0 and DBCR1
and modes for detecting IAC register debug events. Instruction address compare debug events can
occur regardless of the values of MSR[DE] or DBCR0[IDM].
When an instruction address compare debug event occurs, the corresponding DBSR[IACn] bits
are set to record the debug exception. If MSR[DE] is cleared, DBSR[IDE] is also set to capture
the imprecise debug event.
If MSR[DE] is set at the time of the instruction address compare debug exception, a debug
interrupt occurs immediately (if no higher priority exception has caused an interrupt). Execution
of the instruction causing the exception is suppressed, and CSRR0 is set to the address of the
excepting instruction.
Table 8-7. Instruction Address Compare Modes
Mode
Instruction Address Match Condition
Exact address compare The fetch address equals the value in the enabled IAC register.
Address bit match
For IAC1 and IAC2 debug events, if the fetch address, ANDed with the contents of IAC2, is
equal to the contents of IAC1, also ANDed with the contents of IAC2.
Inclusive address range
compare mode
For IAC1 and IAC2 debug events, if the fetch address is greater than or equal to the contents
of IAC1 and less than the contents of IAC2.
Exclusive address
range compare mode
For IAC1 and IAC2 debug events, if the instruction fetch address is less than the contents of
IAC1 or greater than or equal to the contents of IAC2.
Summary of Contents for PowerPC e500 Core
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