Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
6-4 Freescale Semiconductor
Power Management
NOTE
The e500 does not implement its own doze, nap, and sleep modes. The
core-halted and core-stopped states may correlate to the integrated
device’s doze, nap, and sleep modes, but the e500 cannot be put into
core-halted or core-stopped state without interaction with system
integration logic.
6.4.1 Software Considerations for Power Management
Setting MSR[WE] generates a request to the power management logic of the integrated device
(external to the core complex) to enter a power-saving state. It is assumed that the desired
power-saving state (doze, nap, or sleep) has been previously set up by setting the appropriate HID0
bit, typically at system start-up time. Setting MSR[WE] does not directly affect instruction
execution, but it is reflected on the core doze, nap, and sleep signals, depending on the
HID0[DOZE,NAP,SLEEP] settings.
To ensure a clean transition into and out of a power-saving mode, the following program sequence
is recommended:
msync
mtmsr (WE)
isync
loop: br loop
HID0[SLEEP] If MSR[WE] = 1, signals power management logic to initiate device sleep mode. The core complex remains in
core-stopped state and stops its time base after integrated device logic negates tben.
HID0[TBEN] Time base and decrementer enable
0 Time base disabled (no counting)
• 1Time base enabled
Table 6-3. Core Power Management Control Bits (continued)
Bit Description