Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
2-12 Freescale Semiconductor
Register Model
2.5.2 Processor ID Register (PIR)
The e500 implements the processor ID register (PIR) as defined by the Book E architecture. The
PIR contains a value that can be used to distinguish the processor from other processors in the
system.
50 FP Floating-point available. Book E defines the operation of FP as follows:
0 The processor cannot execute floating-point instructions, including floating-point loads, stores, and moves.
1 The processor can execute floating-point instructions.
On the e500, this bit is reserved and permanently cleared, indicating that it does not implement a Book E
floating-point unit (FPU). Setting it has no effect.
51 ME Machine check enable.
0 Machine check interrupts are disabled. On e500 cores, a machine check condition causes a checkstop.
1 Machine check interrupts are enabled.
52 FE0 Floating-point exception mode 0. On the e500, this bit is reserved and permanently cleared, indicating that the
e500 does not implement a Book E FPU. Setting it has no effect.
53 UBLE Allocated for implementation-dependent use. On the e500, it is the user BTB lock enable bit.
0 Execution of the BTB lock instructions for user mode is disabled; a privileged instruction exception is taken
instead.
1 Execution of the BTB lock instructions for user mode is enabled.
54 DE Debug interrupt enable
0 Debug interrupts are disabled.
1 Debug interrupts are enabled if DBCR0[IDM] = 1.
For the e500, see the description of the DBSR[UDE] in
Section 2.13.2, “Debug Status Register (DBSR) .”
55 FE1 Floating-point exception mode 1. On the e500, this bit is reserved and permanently cleared, indicating that the
e500 does not implement a Book E FPU. Setting it has no effect.
56–57 — Reserved, should be cleared.
1
58 IS Instruction address space
0 The processor directs all instruction fetches to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs all instruction fetches to address space 1 (TS = 1 in the relevant TLB entry).
59 DS Data address space
0 The processor directs data memory accesses to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs data memory accesses to address space 1 (TS = 1 in the relevant TLB entry).
60 — Reserved, should be cleared.
1
61 PMM Performance monitor mark bit. System software can set PMM when a marked process is running to enable
statistics to be gathered only during the execution of the marked process. MSR[PR] and MSR[PMM] together
define a state that the processor (supervisor or user) and the process (marked or unmarked) may be in at any
tim e. If this state matches an individual state specified in the PMLCa
n, the state for which monitoring is enabled,
counting is enabled.
62–63 — Reserved, should be cleared.
1
1
An MSR bit that is reserved may be altered by return from interrupt instructions.
Table 2-3. MSR Field Descriptions (continued)
Bits Name Description