PowerPC e500 Core Family Reference Manual, Rev. 1
2-54
Freescale Semiconductor
Register Model
2.15.2 User Global Control Register 0 (UPMGC0)
The contents of PMGC0 are reflected to UPMGC0, which is read by user-level software.
UPMGC0 is read with the mfpmr instruction using PMR384.
Table 2-38. PMGC0 Field Descriptions
Bits Name
Description
32
FAC
Freeze all counters. When FAC is set by hardware or software, PMLCx[FC] maintains its current value until it
is changed by software.
0 The PMCs are incremented (if permitted by other PM control bits).
1 The PMCs are not incremented.
33
PMIE
Performance monitor interrupt enable
0 Performance monitor interrupts are disabled.
1 Performance monitor interrupts are enabled and occur when an enabled condition or event occurs.
34
FCECE Freeze counters on enabled condition or event
0 The PMCs can be incremented (if permitted by other PM control bits).
1 The PMCs can be incremented (if permitted by other PM control bits) only until an enabled condition or
event occurs. When an enabled condition or event occurs, PMGC0[FAC] is set. It is up to software to clear
FAC.
35–50
—
Reserved, should be cleared.
51–52
TBSEL Time base selector. Selects the time base bit that can cause a time base transition event (the event occurs
when the selected bit changes from 0 to 1). (e500v2 only)
00 TB[63] (TBL[31])
01 TB[55] (TBL[23])
10 TB[51] (TBL[19])
11 TB[47] (TBL[15])
Time base transition events can be used to periodically collect information about processor activity. In
multiprocessor systems in which TB registers are synchronized among processors, time base transition
events can be used to correlate the performance monitor data obtained by the several processors. For this
use, software must specify the same TBSEL value for all processors in the system. Because the time-base
frequency is implementation-dependent, software should invoke a system service program to obtain the
frequency before choosing a value for TBSEL.
53–54
—
Reserved, should be cleared.
55
TBEE Time base transition event exception enable. (e500v2 only)
0 Exceptions from time base transition events are disabled.
1 Exceptions from time base transition events are enabled. A time base transition is signaled to the
performance monitor if the TB bit specified in PMGC0[TBSEL] changes from 0 to 1. Time base transition
events can be used to freeze the counters (PMGC0[FCECE]) or signal an exception (PMGC0[PMIE]).
Changing PMGC0[TBSEL] while PMGC0[TBEE] is enabled may cause a false 0 to 1 transition that signals
the specified action (freeze, exception) to occur immediately. Although the interrupt signal condition may
occur with MSR[EE] = 0, the interrupt cannot be taken until MSR[EE] = 1.
56–63
—
Reserved, should be cleared.
Summary of Contents for PowerPC e500 Core
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