Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
5-38 Freescale Semiconductor
Interrupts and Exceptions
For any single instruction attempting to cause multiple exceptions for which the corresponding
synchronous interrupt types are enabled, this section defines the priority order by which the
instruction is permitted to cause a single enabled exception, thus generating a particular
synchronous interrupt. Note that it is this exception priority mechanism, along with the
requirement that synchronous interrupts be generated in program order, that guarantees that at any
given time there exists for consideration only one of the synchronous interrupt types listed in
item 1 of
Section 5.10.2, “Interrupt Order .” The exception priority mechanism also prevents
certain debug exceptions from existing in combination with certain other synchronous
interrupt-generating exceptions.
This section does not define the permitted setting of multiple exceptions for which the
corresponding interrupt types are disabled. The generation of exceptions for which the
corresponding interrupt types are disabled has no effect on the generation of other exceptions for
which the corresponding interrupt types are enabled. Conversely, if a particular exception for
which the corresponding interrupt type is enabled is shown in the following sections to be of a
higher priority than another exception, it prevents the setting of that other exception, independent
of whether that other exception’s corresponding interrupt type is enabled or disabled.
Except as specifically noted, only one of the exception types listed for a given instruction type is
permitted to be generated at any given time.
NOTE
Some exception types may even be mutually exclusive of each other
and could otherwise be considered the same priority. In these cases,
the exceptions are listed in the order suggested by the sequential
execution model.
Exception priorities within each instruction type are listed in the following sections. Priority is
shown highest to lowest.