Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 391 / 548

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-1
Chapter 12
Memory Management Units
This chapter describes the implementation details of the e500v1 core complex MMU relative to
the Book E architecture and the Freescale Book E standards. In addition, it describes the e500v2
core with its extended page sizes and extended physical addressing. All text denoted as e500
applies to both the e500v1 and the e500v2, unless specifically noted as applying to only one core
or the other. For background on the MMU definition in Book E and the Freescale Book E
standards, see the EREF: A Reference for Freescale Book E and the e500 Core (EREF).
12.1 e500 MMU Overview
The e500 core complex employs a two-level memory management unit (MMU) architecture.
There are separate data and instruction level 1 (L1) MMUs in hardware backed up by a unified
level 2 (L2) MMU. The L1 MMUs are completely invisible with respect to the architecture. The
programming model for implementing translation lookaside buffers (TLBs) provided in Book E
and the Freescale Book E standard applies to the L2 MMU of the core complex.
12.1.1 MMU Features
The e500 core has the following features:
• 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual
address) for the e500v1 core and 36-bit real address for the e500v2 core
• Two-level MMU containing a total of six TLBs for maximizing TLB hit rates
• Three 8-bit PID registers (PID0–PID2) for supporting up to 255 translation IDs at any time
in the TLB, with three concurrent translation IDs as potential matches for each access
• TLB entries for variable-sized (4-Kbyte–256-Mbyte pages for the e500v1 and
4-Kbyte–4-Gbyte pages for the e500v2) and fixed-size (4-Kbyte) pages
• No page table format is defined; software is free to use its own page table format.
• TLBs maintained by system software through the TLB instructions and six (e500v1) or
seven (e500v2) MAS registers