Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
4-46 Freescale Semiconductor
Execution Timing
Additional conditions are described in the e500 Software Optimization Guide. The following
sections describe how to optimize code for dispatch.
4.7.2.1 Dispatch Groupings
Maximum dispatch throughput is two instructions per cycle. The dispatch process includes
checking for availability of CQ and issue queue entries and a branch ready check.
The dispatcher can send two instructions to the two issues queues, with a maximum of two to the
GIQ and one to the BIQ.
The dispatcher can rename as many as two GPRs per cycle, so a two-instruction dispatch window
composed of add and mulli could be dispatched in one cycle.
Note that a load/store update form (for example, lwzu), requires a rename register for the update.
This means an lwzu needs two GPR renames. The restriction to two GPR renames in a dispatch
group means that the sequence, lwzu, add, cannot be dispatched in one cycle.
4.7.3 Issue Queue Resource Requirements
Instructions cannot be issued unless the specified execution unit is available. The following
sections describe how to optimize use of the issue queues.
4.7.3.1 General Issue Queue (GIQ)
As many as two instructions can be dispatched to the four-entry general issue queue (GIQ) per
cycle. As many as two instructions can be issued in any order from GIQ0 and GIQ1 to the LSU,
MU, SU1, and SU2 reservation stations.
Issuing instructions out-of-order can help in a number of situations. For example, if the MU is busy
and a multiply is stalled at the bottom GIQ entry, the instruction in the next GIQ entry can be issued
to LSU or SU1, bypassing that multiply.
4.7.3.2 Branch Issue Queue (BIQ)
One instruction per clock cycle can be dispatched to the BIQ. One instruction can be issued to the
branch execution unit out of BIQ0.
4.7.4 Completion Unit Resource Requirements
The e500 completion queue has 14 entries, so as many as 14 instructions can be in execution. The
following resources are required to avoid stalls in the completion unit; note that the two
completion entries are described as CQ0–CQ1, where CQ0 is located at the end of the CQ (see