Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
11-18 Freescale Semiconductor
L1 Caches
All cache control instructions except dcba, dcbt, and dcbtst generate TLB miss exceptions if the
effective address cannot be translated. The dcba, dcbt, and dcbtst instructions are treated as
no-ops if the address cannot be translated.
If a dcbt or dcbtst instruction accesses a page marked caching-inhibited, it is treated as a no-op.
The icbt instruction is treated as a no-op when the CT operand is equal to zero. The dcbst
instruction maps to dcbf.
The core complex broadcasts the cache control instructions according to the value of HID1[ABE].
If ABE is cleared, most cache control instructions are not broadcast. If it is set, cache control
instructions are broadcast.
11.4.2 L1 Instruction and Data Cache Enabling/Disabling
The instruction and data caches are enabled and disabled with the cache enable (CE) bits in
L1CSR1 and L1CSR0, respectively. Disabling a cache does not cause all memory accesses to be
performed as caching inhibited. When caching-inhibited accesses are desired, the pages must be
marked as caching inhibited in the MMU pages.
When either the instruction or data cache is disabled, the cache tag state bits are ignored and the
corresponding cache is not accessed. The default power-up state of L1CSR0[CE] and
L1CSR1[ICE] is zero (caches disabled).
When the data cache is disabled, snooping of lines in the cache is not performed. Before the data
cache is disabled it must be invalidated to prevent coherency problems when it is enabled again.
All cache operations are affected by disabling the cache. Touch instructions (dcbt, dcbtst, dcblc,
dcbtls, dcbtstls, icblc, and icbtls) performed on the CCB by the e500 do not affect the cache when
it is disabled. A dcba or dcbz instruction to a disabled data cache zeros the cache line in memory,
but does not affect the cache when it is disabled.
If CE = 0, the dcbi and dcbf instructions do not affect the L1 data cache.
The setting of L1CSR0[CE] must be preceded by an msync and isync instruction, to prevent a
cache from being disabled or enabled in the middle of a data or instruction access. See
Table 2-42
for more information on synchronization requirements.
11.4.3 L1 Instruction and Data Cache Flash Invalidation
The data cache can be invalidated by executing a series of dcbi instructions or by setting
L1CSR0[CFI].
If software can guarantee that data is not modified, the cache can be invalidated without updating
system memory; if a modified line is invalidated, the data is lost. To prevent the loss of data,
modified cache lines must be flushed, as described in
Section 11.5, “L1 Data Cache Flushing .”