PowerPC e500 Core Family Reference Manual, Rev. 1
A-2
Freescale Semiconductor
Programming Examples
successful execution of the conditional sequence is that no store into addr by another processor or
mechanism has intervened between the source of the load and reserve and the store conditional.
For each of these examples, it is assumed that a similar sequence of instructions is used by all
processes requiring synchronization on the accessed data.
NOTE
Because memory synchronization instructions have implementation
dependencies (for example, the granularity at which reservations are
managed), they must be used with care. The operating system should
provide system library programs that use these instructions to
implement the high-level synchronization functions (such as test and
set or compare and swap) needed by application programs.
Application programs should use these library programs, rather than
use storage synchronization instructions directly.
A.1.1
Synchronization Primitives
The following examples show how the lwarx and stwcx. instructions can be used to implement
various synchronization primitives.
The sequences used to emulate the various primitives consist primarily of a loop using lwarx and
stwcx.. No additional synchronization is necessary, because the stwcx. will fail, clearing EQ, if the
word loaded by lwarx has changed before the stwcx. is executed: see
Section 3.3.1.7, “Atomic
Update Primitives Using lwarx and stwcx.
,” for details.
A.1.1.1
Fetch and No-op
The fetch and no-op primitive atomically loads the current value in a word in storage.
In this example, it is assumed that the address of the word to be loaded is in GPR3 and the data
loaded is returned in GPR4.
loop: lwarx r4,0,r3
#load
and
reserve
stwcx.
r4,0,r3
#store old value if still reserved
bc
4,2,loop
#loop if lost reservation
If the stwcx. succeeds, it stores to the target location the same value that was loaded by the
preceding lwarx. While the store is redundant with respect to the value in the location, its success
ensures that the value loaded by the lwarx was the current value, that is, that the source of the value
loaded by the lwarx was the last store to the location that preceded the stwcx. in the coherence
order for the location.
Summary of Contents for PowerPC e500 Core
Page 1: ...PowerPC e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev 1 4 2005...
Page 36: ...PowerPC e500 Core Family Reference Manual Rev 1 xxxvi Freescale Semiconductor...
Page 38: ...PowerPC e500 Core Family Reference Manual Rev 1 Part I 2 Freescale Semiconductor...
Page 332: ...PowerPC e500 Core Family Reference Manual Rev 1 Part II 2 Freescale Semiconductor...
Page 530: ...Opcode Listings PowerPC e500 Core Family Reference Manual Rev 1 D 50 Freescale Semiconductor...
Page 534: ...PowerPC e500 Core Family Reference Manual Rev 1 E 4 Freescale Semiconductor Revision History...