PowerPC e500 Core Family Reference Manual, Rev. 1
5-16
Freescale Semiconductor
Interrupts and Exceptions
When a machine check interrupt is taken, registers are updated as shown in
Table 5-9
.
Instruction execution resumes at address IVPR[32–47] || IVOR1[48–59] || 0b0000.
NOTES
If a machine check interrupt is caused by a memory subsystem error,
the subsystem may return incorrect data, which may be placed into
registers or on-chip caches.
For implementations on which a machine check interrupt is caused by
referring to an invalid physical address, executing dcbz or dcba can
cause a delayed machine check interrupt by establishing a data cache
block associated with an invalid physical address. A machine check
interrupt can occur later if and when an attempt is made to write that
block to main memory, for example as the result of executing an
instruction that causes a cache miss for which the block is the target
for replacement or as the result of executing dcbst or dcbf.
5.7.2.1
Core Complex Bus (CCB) and L1 Cache Machine Check Errors
This section describes machine checks caused by bus and L1 cache errors. It describes error
signaling and detection, and it contains information about error recoverability.
The L1 caches in the e500 core complex are protected by parity. Parity information is written into
the L1 caches when one of the following occurs:
•
A store instruction, dcbz, or dcba modifies the data cache.
•
A line fill occurs into the instruction or data cache.
L1 cache parity is checked when one of the following occurs:
•
A load instruction hits in the L1 data cache.
•
An instruction fetch hits in the L1 instruction cache.
•
A line is cast out of the L1 data cache.
Table 5-9. Machine Check Interrupt Settings
Register
Setting
MCSRR0 On a best-effort basis, the core complex sets this to an effective address of some instruction that was
executing or about to be executing when the machine check condition occurred.
MCSRR1 MSR[37–38,46–55,57–59,61–63] are loaded with equivalent MSR bits. All other bits are reserved.
MCAR
When a machine check interrupt is taken, the machine check address register is updated with the address
of the data associated with the machine check. Note that if a machine check interrupt is caused by a signal,
the MCAR contents are not meaningful. See
Section 2.7.2.3, “Machine Check Address Register (MCAR)
.”
MCSR
Set according to the machine check condition. See
Table 5-4
.
Summary of Contents for PowerPC e500 Core
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